Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * wb_epbuf.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com> |
| 7 | * SPDX-License-Identifier: CERN-OHL-P-2.0 |
| 8 | */ |
| 9 | |
| 10 | `default_nettype none |
| 11 | |
| 12 | module wb_epbuf #( |
| 13 | parameter integer AW = 9, |
| 14 | parameter integer DW = 32 |
| 15 | )( |
| 16 | // Wishbone slave |
| 17 | input wire [AW-1:0] wb_addr, |
| 18 | output wire [DW-1:0] wb_rdata, |
| 19 | input wire [DW-1:0] wb_wdata, |
| 20 | input wire wb_we, |
| 21 | input wire wb_cyc, |
| 22 | output wire wb_ack, |
| 23 | |
| 24 | // USB EP-Buf master |
| 25 | output wire [AW-1:0] ep_tx_addr_0, |
| 26 | output wire [DW-1:0] ep_tx_data_0, |
| 27 | output wire ep_tx_we_0, |
| 28 | |
| 29 | output wire [AW-1:0] ep_rx_addr_0, |
| 30 | input wire [DW-1:0] ep_rx_data_1, |
| 31 | output wire ep_rx_re_0, |
| 32 | |
| 33 | // Clock / Reset |
| 34 | input wire clk, |
| 35 | input wire rst |
| 36 | ); |
| 37 | |
| 38 | reg ack_i; |
| 39 | |
| 40 | assign ep_tx_addr_0 = wb_addr; |
| 41 | assign ep_rx_addr_0 = wb_addr; |
| 42 | |
| 43 | assign ep_tx_data_0 = wb_wdata; |
| 44 | assign wb_rdata = ep_rx_data_1; |
| 45 | |
| 46 | assign ep_tx_we_0 = wb_cyc & wb_we & ~ack_i; |
| 47 | assign ep_rx_re_0 = 1'b1; |
| 48 | |
| 49 | assign wb_ack = ack_i; |
| 50 | |
| 51 | always @(posedge clk or posedge rst) |
| 52 | if (rst) |
| 53 | ack_i <= 1'b0; |
| 54 | else |
| 55 | ack_i <= wb_cyc & ~ack_i; |
| 56 | |
| 57 | endmodule // wb_epbuf |