Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * top.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Top-level for the e1-tracer boards. |
| 7 | * |
| 8 | * Note that some things here are only to maintain bitstream compatibility |
| 9 | * with the icepick based proto setup. |
| 10 | * |
| 11 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 12 | * SPDX-License-Identifier: CERN-OHL-S-2.0 |
| 13 | */ |
| 14 | |
| 15 | `default_nettype none |
| 16 | |
| 17 | module top ( |
| 18 | // LIU data |
| 19 | input wire e1A_rx_data, |
| 20 | input wire e1A_rx_clk, |
| 21 | input wire e1B_rx_data, |
| 22 | input wire e1B_rx_clk, |
| 23 | |
| 24 | // LIU control |
| 25 | inout wire liu_mosi, |
| 26 | inout wire liu_miso, |
| 27 | inout wire liu_clk, |
| 28 | inout wire [1:0] liu_cs_n, |
| 29 | |
| 30 | // USB |
| 31 | inout wire usb_dp, |
| 32 | inout wire usb_dn, |
| 33 | output wire usb_pu, |
| 34 | |
| 35 | // Flash |
| 36 | inout wire flash_mosi, |
| 37 | inout wire flash_miso, |
| 38 | inout wire flash_clk, |
| 39 | inout wire flash_cs_n, |
| 40 | |
| 41 | // VIO PDM |
| 42 | output wire vio_pdm, |
| 43 | |
| 44 | // Button |
| 45 | input wire btn, |
| 46 | |
| 47 | // Clock (12 MHz) |
| 48 | input wire clk_in, |
| 49 | |
| 50 | // Debug UART |
| 51 | output wire dbg_tx, |
| 52 | |
| 53 | // RGB LEDs |
| 54 | output wire [2:0] rgb |
| 55 | ); |
| 56 | |
| 57 | localparam integer WB_N = 2; |
| 58 | |
| 59 | genvar i; |
| 60 | |
| 61 | |
| 62 | // Signals |
| 63 | // ------- |
| 64 | |
| 65 | // Flash SPI internal signals |
| 66 | wire flash_mosi_i, flash_miso_i, flash_clk_i; |
| 67 | wire flash_mosi_o, flash_miso_o, flash_clk_o; |
| 68 | wire flash_mosi_oe, flash_miso_oe, flash_clk_oe; |
| 69 | wire flash_csn_o; |
| 70 | |
| 71 | // Peripheral wishbone |
| 72 | wire [15:0] wb_addr; |
| 73 | wire [31:0] wb_rdata [0:WB_N-1]; |
| 74 | wire [31:0] wb_wdata; |
| 75 | wire [ 3:0] wb_wmsk; |
| 76 | wire wb_we; |
| 77 | wire [WB_N-1:0] wb_cyc; |
| 78 | wire [WB_N-1:0] wb_ack; |
| 79 | |
| 80 | wire [(WB_N*32)-1:0] wb_rdata_flat; |
| 81 | |
| 82 | // Ticks |
| 83 | wire [1:0] tick_e1_rx; |
| 84 | wire tick_usb_sof; |
| 85 | |
| 86 | // Clocks / Reset |
| 87 | wire rst_req; |
| 88 | |
| 89 | wire clk_sys; |
| 90 | wire rst_sys; |
| 91 | wire clk_48m; |
| 92 | wire rst_48m; |
| 93 | |
| 94 | |
| 95 | // SoC base |
| 96 | // -------- |
| 97 | |
| 98 | // Instance |
| 99 | soc_base #( |
| 100 | .WB_N(WB_N), |
| 101 | .E1_N(2), |
| 102 | .E1_UNIT_HAS_RX(2'b11), |
| 103 | .E1_UNIT_HAS_TX(2'b00), |
| 104 | .E1_LIU(1) |
| 105 | ) soc_I ( |
| 106 | .e1_rx_hi_p (), |
| 107 | .e1_rx_hi_n (), |
| 108 | .e1_rx_lo_p (), |
| 109 | .e1_rx_lo_n (), |
| 110 | .e1_tx_hi (), |
| 111 | .e1_tx_lo (), |
| 112 | .e1_rx_data ({e1B_rx_data, e1A_rx_data}), |
| 113 | .e1_rx_clk ({e1B_rx_clk, e1A_rx_clk }), |
| 114 | .e1_tx_data (), |
| 115 | .e1_tx_clk (), |
| 116 | .usb_dp (usb_dp), |
| 117 | .usb_dn (usb_dn), |
| 118 | .usb_pu (usb_pu), |
| 119 | .flash_mosi_i (flash_mosi_i), |
| 120 | .flash_mosi_o (flash_mosi_o), |
| 121 | .flash_mosi_oe(flash_mosi_oe), |
| 122 | .flash_miso_i (flash_miso_i), |
| 123 | .flash_miso_o (flash_miso_o), |
| 124 | .flash_miso_oe(flash_miso_oe), |
| 125 | .flash_clk_i (flash_clk_i), |
| 126 | .flash_clk_o (flash_clk_o), |
| 127 | .flash_clk_oe (flash_clk_oe), |
| 128 | .flash_csn_o (flash_csn_o), |
| 129 | .dbg_rx (1'b1), |
| 130 | .dbg_tx (dbg_tx), |
| 131 | .rgb (rgb), |
| 132 | .wb_m_addr (wb_addr), |
| 133 | .wb_m_rdata (wb_rdata_flat), |
| 134 | .wb_m_wdata (wb_wdata), |
| 135 | .wb_m_wmsk (wb_wmsk), |
| 136 | .wb_m_we (wb_we), |
| 137 | .wb_m_cyc (wb_cyc), |
| 138 | .wb_m_ack (wb_ack), |
| 139 | .tick_e1_rx (tick_e1_rx), |
| 140 | .tick_usb_sof (tick_usb_sof), |
| 141 | .clk_sys (clk_sys), |
| 142 | .rst_sys (rst_sys), |
| 143 | .clk_48m (clk_48m), |
| 144 | .rst_48m (rst_48m) |
| 145 | ); |
| 146 | |
| 147 | // WB read data flattening |
| 148 | for (i=0; i<WB_N; i=i+1) |
| 149 | assign wb_rdata_flat[i*32+:32] = wb_rdata[i]; |
| 150 | |
| 151 | // SPI IO |
| 152 | SB_IO #( |
| 153 | .PIN_TYPE(6'b101001), |
| 154 | .PULLUP(1'b1) |
| 155 | ) spi_io_I[2:0] ( |
| 156 | .PACKAGE_PIN ({flash_mosi, flash_miso, flash_clk }), |
| 157 | .OUTPUT_ENABLE({flash_mosi_oe, flash_miso_oe, flash_clk_oe}), |
| 158 | .D_OUT_0 ({flash_mosi_o, flash_miso_o, flash_clk_o }), |
| 159 | .D_IN_0 ({flash_mosi_i, flash_miso_i, flash_clk_i }) |
| 160 | ); |
| 161 | |
| 162 | assign flash_cs_n = flash_csn_o; |
| 163 | |
| 164 | |
| 165 | // Misc [0] |
| 166 | // ---- |
| 167 | |
| 168 | misc misc_I ( |
| 169 | .btn (btn), |
| 170 | .tick_e1_rx (tick_e1_rx), |
| 171 | .tick_usb_sof (tick_usb_sof), |
| 172 | .rst_req (rst_req), |
| 173 | .wb_addr (wb_addr[7:0]), |
| 174 | .wb_rdata (wb_rdata[0]), |
| 175 | .wb_wdata (wb_wdata), |
| 176 | .wb_we (wb_we), |
| 177 | .wb_cyc (wb_cyc[0]), |
| 178 | .wb_ack (wb_ack[0]), |
| 179 | .clk (clk_sys), |
| 180 | .rst (rst_sys) |
| 181 | ); |
| 182 | |
| 183 | |
| 184 | // LIU SPI [1] |
| 185 | // ------- |
| 186 | |
| 187 | ice40_spi_wb #( |
| 188 | .N_CS(2), |
| 189 | .WITH_IOB(1), |
| 190 | .UNIT(1) |
| 191 | ) spi_I ( |
| 192 | .pad_mosi (liu_mosi), |
| 193 | .pad_miso (liu_miso), |
| 194 | .pad_clk (liu_clk), |
| 195 | .pad_csn (liu_cs_n), |
| 196 | .wb_addr (wb_addr[3:0]), |
| 197 | .wb_rdata (wb_rdata[1]), |
| 198 | .wb_wdata (wb_wdata), |
| 199 | .wb_we (wb_we), |
| 200 | .wb_cyc (wb_cyc[1]), |
| 201 | .wb_ack (wb_ack[1]), |
| 202 | .clk (clk_sys), |
| 203 | .rst (rst_sys) |
| 204 | ); |
| 205 | |
| 206 | |
| 207 | // Vio PDM |
| 208 | // ------- |
| 209 | |
| 210 | // Compat with iCEpick |
| 211 | assign vio_pdm = 1'b1; |
| 212 | |
| 213 | |
| 214 | // Clock / Reset |
| 215 | // ------------- |
| 216 | |
| 217 | sysmgr sys_mgr_I ( |
| 218 | .clk_in (clk_in), |
| 219 | .rst_in (rst_req), |
| 220 | .clk_sys(clk_sys), |
| 221 | .rst_sys(rst_sys), |
| 222 | .clk_48m(clk_48m), |
| 223 | .rst_48m(rst_48m) |
| 224 | ); |
| 225 | |
| 226 | endmodule // top |