Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * sysmgr.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * System Clock / Reset generation |
| 7 | * |
| 8 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 9 | * SPDX-License-Identifier: CERN-OHL-S-2.0 |
| 10 | */ |
| 11 | |
| 12 | `default_nettype none |
| 13 | |
| 14 | module sysmgr ( |
| 15 | input wire clk_in, |
| 16 | input wire rst_in, |
| 17 | output wire clk_sys, |
| 18 | output wire rst_sys, |
| 19 | output wire clk_48m, |
| 20 | output wire rst_48m |
| 21 | ); |
| 22 | |
| 23 | // Signals |
| 24 | wire pll_lock; |
| 25 | wire pll_reset_n; |
| 26 | |
| 27 | wire clk_12m_i; |
| 28 | wire clk_24m_i; |
| 29 | wire clk_48m_i; |
| 30 | |
| 31 | wire rst_i; |
| 32 | wire rst_out; |
| 33 | reg [3:0] rst_cnt; |
| 34 | |
| 35 | // Global input buffer for 12 MHz clock |
| 36 | SB_GB_IO #( |
| 37 | .PIN_TYPE(6'b000001) |
| 38 | ) gb_in ( |
| 39 | .PACKAGE_PIN(clk_in), |
Sylvain Munaut | 7b22884 | 2020-09-22 20:00:13 +0200 | [diff] [blame] | 40 | .GLOBAL_BUFFER_OUTPUT(clk_12m_i) |
Sylvain Munaut | 546493e | 2020-09-14 10:12:56 +0200 | [diff] [blame] | 41 | ); |
| 42 | |
| 43 | // PLL instance |
| 44 | SB_PLL40_2F_CORE #( |
| 45 | .DIVR(4'b0000), |
| 46 | .DIVF(7'b0111111), |
| 47 | .DIVQ(3'b100), |
| 48 | .FILTER_RANGE(3'b001), |
| 49 | .FEEDBACK_PATH("SIMPLE"), |
| 50 | .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), |
| 51 | .FDA_FEEDBACK(4'b0000), |
| 52 | .SHIFTREG_DIV_MODE(2'b00), |
| 53 | .PLLOUT_SELECT_PORTA("GENCLK"), |
| 54 | .PLLOUT_SELECT_PORTB("GENCLK_HALF"), |
| 55 | .ENABLE_ICEGATE_PORTA(1'b0), |
| 56 | .ENABLE_ICEGATE_PORTB(1'b0) |
| 57 | ) pll_I ( |
| 58 | .REFERENCECLK(clk_12m_i), |
| 59 | .PLLOUTCOREA(), |
| 60 | .PLLOUTGLOBALA(clk_48m_i), |
| 61 | .PLLOUTCOREB(), |
| 62 | .PLLOUTGLOBALB(clk_24m_i), |
| 63 | .EXTFEEDBACK(1'b0), |
| 64 | .DYNAMICDELAY(8'h00), |
| 65 | .RESETB(pll_reset_n), |
| 66 | .BYPASS(1'b0), |
| 67 | .LATCHINPUTVALUE(1'b0), |
| 68 | .LOCK(pll_lock), |
| 69 | .SDI(1'b0), |
| 70 | .SDO(), |
| 71 | .SCLK(1'b0) |
| 72 | ); |
| 73 | |
| 74 | assign clk_sys = clk_24m_i; |
| 75 | assign clk_48m = clk_48m_i; |
| 76 | |
| 77 | // PLL reset generation |
| 78 | assign pll_reset_n = ~rst_in; |
| 79 | |
| 80 | // Logic reset generation |
| 81 | always @(posedge clk_24m_i or negedge pll_lock) |
| 82 | if (!pll_lock) |
| 83 | rst_cnt <= 4'h0; |
| 84 | else if (~rst_cnt[3]) |
| 85 | rst_cnt <= rst_cnt + 1; |
| 86 | |
| 87 | assign rst_i = ~rst_cnt[3]; |
| 88 | |
| 89 | SB_GB rst_gbuf_I ( |
| 90 | .USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i), |
| 91 | .GLOBAL_BUFFER_OUTPUT(rst_out) |
| 92 | ); |
| 93 | |
| 94 | assign rst_sys = rst_out; |
| 95 | assign rst_48m = rst_out; |
| 96 | |
| 97 | endmodule // sysmgr |