Sylvain Munaut | bc9f5c4 | 2020-09-14 10:22:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * e1.c |
| 3 | * |
| 4 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 5 | * SPDX-License-Identifier: GPL-3.0-or-later |
| 6 | */ |
| 7 | |
| 8 | #include <stdint.h> |
| 9 | #include <stdbool.h> |
| 10 | #include <string.h> |
| 11 | |
| 12 | #include "config.h" |
| 13 | #include "console.h" |
| 14 | #include "e1.h" |
| 15 | |
| 16 | #include "dma.h" |
| 17 | #include "led.h" // FIXME |
| 18 | |
| 19 | |
| 20 | // Hardware |
| 21 | // -------- |
| 22 | |
| 23 | struct e1_chan { |
| 24 | uint32_t csr; |
| 25 | uint32_t bd; |
| 26 | } __attribute__((packed,aligned(4))); |
| 27 | |
| 28 | struct e1_core { |
| 29 | struct e1_chan rx; |
| 30 | struct e1_chan tx; |
| 31 | } __attribute__((packed,aligned(4))); |
| 32 | |
| 33 | #define E1_RX_CR_ENABLE (1 << 0) |
| 34 | #define E1_RX_CR_MODE_TRSP (0 << 1) |
| 35 | #define E1_RX_CR_MODE_BYTE (1 << 1) |
| 36 | #define E1_RX_CR_MODE_BFA (2 << 1) |
| 37 | #define E1_RX_CR_MODE_MFA (3 << 1) |
| 38 | #define E1_RX_CR_OVFL_CLR (1 << 12) |
| 39 | #define E1_RX_SR_ENABLED (1 << 0) |
| 40 | #define E1_RX_SR_ALIGNED (1 << 1) |
| 41 | #define E1_RX_SR_BD_IN_EMPTY (1 << 8) |
| 42 | #define E1_RX_SR_BD_IN_FULL (1 << 9) |
| 43 | #define E1_RX_SR_BD_OUT_EMPTY (1 << 10) |
| 44 | #define E1_RX_SR_BD_OUT_FULL (1 << 11) |
| 45 | #define E1_RX_SR_OVFL (1 << 12) |
| 46 | |
| 47 | #define E1_TX_CR_ENABLE (1 << 0) |
| 48 | #define E1_TX_CR_MODE_TRSP (0 << 1) |
| 49 | #define E1_TX_CR_MODE_TS0 (1 << 1) |
| 50 | #define E1_TX_CR_MODE_TS0_CRC (2 << 1) |
| 51 | #define E1_TX_CR_MODE_TS0_CRC_E (3 << 1) |
| 52 | #define E1_TX_CR_TICK_LOCAL (0 << 3) |
| 53 | #define E1_TX_CR_TICK_REMOTE (1 << 3) |
| 54 | #define E1_TX_CR_ALARM (1 << 4) |
| 55 | #define E1_TX_CR_LOOPBACK (1 << 5) |
| 56 | #define E1_TX_CR_UNFL_CLR (1 << 12) |
| 57 | #define E1_TX_SR_ENABLED (1 << 0) |
| 58 | #define E1_TX_SR_BD_IN_EMPTY (1 << 8) |
| 59 | #define E1_TX_SR_BD_IN_FULL (1 << 9) |
| 60 | #define E1_TX_SR_BD_OUT_EMPTY (1 << 10) |
| 61 | #define E1_TX_SR_BD_OUT_FULL (1 << 11) |
| 62 | #define E1_TX_SR_UNFL (1 << 12) |
| 63 | |
| 64 | #define E1_BD_VALID (1 << 15) |
| 65 | #define E1_BD_CRC1 (1 << 14) |
| 66 | #define E1_BD_CRC0 (1 << 13) |
| 67 | #define E1_BD_ADDR(x) ((x) & 0x7f) |
| 68 | #define E1_BD_ADDR_MSK 0x7f |
| 69 | #define E1_BD_ADDR_SHFT 0 |
| 70 | |
| 71 | |
| 72 | static volatile struct e1_core * const e1_regs = (void *)(E1_CORE_BASE); |
| 73 | static volatile uint8_t * const e1_data = (void *)(E1_DATA_BASE); |
| 74 | |
| 75 | |
| 76 | volatile uint8_t * |
| 77 | e1_data_ptr(int mf, int frame, int ts) |
| 78 | { |
| 79 | return &e1_data[(mf << 9) | (frame << 5) | ts]; |
| 80 | } |
| 81 | |
| 82 | unsigned int |
| 83 | e1_data_ofs(int mf, int frame, int ts) |
| 84 | { |
| 85 | return (mf << 9) | (frame << 5) | ts; |
| 86 | } |
| 87 | |
| 88 | |
| 89 | // FIFOs |
| 90 | // ----- |
| 91 | /* Note: FIFO works at 'frame' level (i.e. 32 bytes) */ |
| 92 | |
| 93 | struct e1_fifo { |
| 94 | /* Buffer zone associated with the FIFO */ |
| 95 | unsigned int base; |
| 96 | unsigned int mask; |
| 97 | |
| 98 | /* Pointers / Levels */ |
| 99 | unsigned int wptr[2]; /* 0=committed 1=allocated */ |
| 100 | unsigned int rptr[2]; /* 0=discared 1=peeked */ |
| 101 | }; |
| 102 | |
| 103 | /* Utils */ |
| 104 | static void |
| 105 | e1f_reset(struct e1_fifo *fifo, unsigned int base, unsigned int len) |
| 106 | { |
| 107 | memset(fifo, 0x00, sizeof(struct e1_fifo)); |
| 108 | fifo->base = base; |
| 109 | fifo->mask = len - 1; |
| 110 | } |
| 111 | |
| 112 | static unsigned int |
| 113 | e1f_allocd_frames(struct e1_fifo *fifo) |
| 114 | { |
| 115 | /* Number of frames that are allocated (i.e. where we can't write to) */ |
| 116 | return (fifo->wptr[1] - fifo->rptr[0]) & fifo->mask; |
| 117 | } |
| 118 | |
| 119 | static unsigned int |
| 120 | e1f_valid_frames(struct e1_fifo *fifo) |
| 121 | { |
| 122 | /* Number of valid frames */ |
| 123 | return (fifo->wptr[0] - fifo->rptr[0]) & fifo->mask; |
| 124 | } |
| 125 | |
| 126 | static unsigned int |
| 127 | e1f_unseen_frames(struct e1_fifo *fifo) |
| 128 | { |
| 129 | /* Number of valid frames that haven't been peeked yet */ |
| 130 | return (fifo->wptr[0] - fifo->rptr[1]) & fifo->mask; |
| 131 | } |
| 132 | |
| 133 | static unsigned int |
| 134 | e1f_free_frames(struct e1_fifo *fifo) |
| 135 | { |
| 136 | /* Number of frames that aren't allocated */ |
| 137 | return (fifo->rptr[0] - fifo->wptr[1] - 1) & fifo->mask; |
| 138 | } |
| 139 | |
| 140 | static unsigned int |
| 141 | e1f_ofs_to_dma(unsigned int ofs) |
| 142 | { |
| 143 | /* DMA address are 32-bits word address. Offsets are 32 byte address */ |
| 144 | return (ofs << 3); |
| 145 | } |
| 146 | |
| 147 | static unsigned int |
| 148 | e1f_ofs_to_mf(unsigned int ofs) |
| 149 | { |
| 150 | /* E1 Buffer Descriptors are always multiframe aligned */ |
| 151 | return (ofs >> 4); |
| 152 | } |
| 153 | |
| 154 | |
| 155 | /* Debug */ |
| 156 | static void |
| 157 | e1f_debug(struct e1_fifo *fifo, const char *name) |
| 158 | { |
| 159 | unsigned int la, lv, lu, lf; |
| 160 | |
| 161 | la = e1f_allocd_frames(fifo); |
| 162 | lv = e1f_valid_frames(fifo); |
| 163 | lu = e1f_unseen_frames(fifo); |
| 164 | lf = e1f_free_frames(fifo); |
| 165 | |
| 166 | printf("%s: R: %u / %u | W: %u / %u | A:%u V:%u U:%u F:%u\n", |
| 167 | name, |
| 168 | fifo->rptr[0], fifo->rptr[1], fifo->wptr[0], fifo->wptr[1], |
| 169 | la, lv, lu, lf |
| 170 | ); |
| 171 | } |
| 172 | |
| 173 | /* Frame level read/write */ |
| 174 | static unsigned int |
| 175 | e1f_frame_write(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames) |
| 176 | { |
| 177 | unsigned int lf, le; |
| 178 | |
| 179 | lf = e1f_free_frames(fifo); |
| 180 | le = fifo->mask - fifo->wptr[0] + 1; |
| 181 | |
| 182 | if (max_frames > le) |
| 183 | max_frames = le; |
| 184 | if (max_frames > lf) |
| 185 | max_frames = lf; |
| 186 | |
| 187 | *ofs = fifo->base + fifo->wptr[0]; |
| 188 | fifo->wptr[1] = fifo->wptr[0] = (fifo->wptr[0] + max_frames) & fifo->mask; |
| 189 | |
| 190 | return max_frames; |
| 191 | } |
| 192 | |
| 193 | static unsigned int |
| 194 | e1f_frame_read(struct e1_fifo *fifo, unsigned int *ofs, int max_frames) |
| 195 | { |
| 196 | unsigned int lu, le; |
| 197 | |
| 198 | lu = e1f_unseen_frames(fifo); |
| 199 | le = fifo->mask - fifo->rptr[1] + 1; |
| 200 | |
| 201 | if (max_frames > le) |
| 202 | max_frames = le; |
| 203 | if (max_frames > lu) |
| 204 | max_frames = lu; |
| 205 | |
| 206 | *ofs = fifo->base + fifo->rptr[1]; |
| 207 | fifo->rptr[0] = fifo->rptr[1] = (fifo->rptr[1] + max_frames) & fifo->mask; |
| 208 | |
| 209 | return max_frames; |
| 210 | } |
| 211 | |
| 212 | |
| 213 | /* MultiFrame level split read/write */ |
| 214 | static bool |
| 215 | e1f_multiframe_write_prepare(struct e1_fifo *fifo, unsigned int *ofs) |
| 216 | { |
| 217 | unsigned int lf; |
| 218 | |
| 219 | lf = e1f_free_frames(fifo); |
| 220 | if (lf < 16) |
| 221 | return false; |
| 222 | |
| 223 | *ofs = fifo->base + fifo->wptr[1]; |
| 224 | fifo->wptr[1] = (fifo->wptr[1] + 16) & fifo->mask; |
| 225 | |
| 226 | return true; |
| 227 | } |
| 228 | |
| 229 | static void |
| 230 | e1f_multiframe_write_commit(struct e1_fifo *fifo) |
| 231 | { |
| 232 | fifo->wptr[0] = (fifo->wptr[0] + 16) & fifo->mask; |
| 233 | } |
| 234 | |
| 235 | static bool |
| 236 | e1f_multiframe_read_peek(struct e1_fifo *fifo, unsigned int *ofs) |
| 237 | { |
| 238 | unsigned int lu; |
| 239 | |
| 240 | lu = e1f_unseen_frames(fifo); |
| 241 | if (lu < 16) |
| 242 | return false; |
| 243 | |
| 244 | *ofs = fifo->base + fifo->rptr[1]; |
| 245 | fifo->rptr[1] = (fifo->rptr[1] + 16) & fifo->mask; |
| 246 | |
| 247 | return true; |
| 248 | } |
| 249 | |
| 250 | static void |
| 251 | e1f_multiframe_read_discard(struct e1_fifo *fifo) |
| 252 | { |
| 253 | fifo->rptr[0] = (fifo->rptr[0] + 16) & fifo->mask; |
| 254 | } |
| 255 | |
| 256 | static void |
| 257 | e1f_multiframe_empty(struct e1_fifo *fifo) |
| 258 | { |
| 259 | fifo->rptr[0] = fifo->rptr[1] = (fifo->wptr[0] & ~15); |
| 260 | } |
| 261 | |
| 262 | |
| 263 | |
| 264 | // Main logic |
| 265 | // ---------- |
| 266 | |
| 267 | enum e1_pipe_state { |
| 268 | IDLE = 0, |
| 269 | BOOT = 1, |
| 270 | RUN = 2, |
| 271 | RECOVER = 3, |
| 272 | }; |
| 273 | |
| 274 | static struct { |
| 275 | struct { |
| 276 | uint32_t cr; |
| 277 | struct e1_fifo fifo; |
| 278 | int in_flight; |
| 279 | enum e1_pipe_state state; |
| 280 | } rx; |
| 281 | |
| 282 | struct { |
| 283 | uint32_t cr; |
| 284 | struct e1_fifo fifo; |
| 285 | int in_flight; |
| 286 | enum e1_pipe_state state; |
| 287 | } tx; |
| 288 | } g_e1; |
| 289 | |
| 290 | |
| 291 | |
| 292 | |
| 293 | void |
| 294 | e1_init(bool clk_mode) |
| 295 | { |
| 296 | /* Global state init */ |
| 297 | memset(&g_e1, 0x00, sizeof(g_e1)); |
| 298 | |
| 299 | /* Reset FIFOs */ |
| 300 | e1f_reset(&g_e1.rx.fifo, 0, 128); |
| 301 | e1f_reset(&g_e1.tx.fifo, 128, 128); |
| 302 | |
| 303 | /* Enable Rx */ |
| 304 | g_e1.rx.cr = E1_RX_CR_OVFL_CLR | |
| 305 | E1_RX_CR_MODE_MFA | |
| 306 | E1_RX_CR_ENABLE; |
| 307 | e1_regs->rx.csr = g_e1.rx.cr; |
| 308 | |
| 309 | /* Enable Tx */ |
| 310 | g_e1.tx.cr = E1_TX_CR_UNFL_CLR | |
| 311 | (clk_mode ? E1_TX_CR_TICK_REMOTE : E1_TX_CR_TICK_LOCAL) | |
| 312 | E1_TX_CR_MODE_TS0_CRC_E | |
| 313 | E1_TX_CR_ENABLE; |
| 314 | e1_regs->tx.csr = g_e1.tx.cr; |
| 315 | |
| 316 | /* State */ |
| 317 | g_e1.rx.state = BOOT; |
| 318 | g_e1.tx.state = BOOT; |
| 319 | } |
| 320 | |
| 321 | |
| 322 | #include "dma.h" |
| 323 | |
| 324 | unsigned int |
| 325 | e1_rx_need_data(unsigned int usb_addr, unsigned int max_frames) |
| 326 | { |
| 327 | unsigned int ofs; |
| 328 | int tot_frames = 0; |
| 329 | int n_frames; |
| 330 | |
| 331 | while (max_frames) { |
| 332 | /* Get some data from the FIFO */ |
| 333 | n_frames = e1f_frame_read(&g_e1.rx.fifo, &ofs, max_frames); |
| 334 | if (!n_frames) |
| 335 | break; |
| 336 | |
| 337 | /* Copy from FIFO to USB */ |
| 338 | dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), false, NULL, NULL); |
| 339 | |
| 340 | /* Prepare Next */ |
| 341 | usb_addr += n_frames * (32 / 4); |
| 342 | max_frames -= n_frames; |
| 343 | tot_frames += n_frames; |
| 344 | |
| 345 | /* Wait for DMA completion */ |
| 346 | while (dma_poll()); |
| 347 | } |
| 348 | |
| 349 | return tot_frames; |
| 350 | } |
| 351 | |
| 352 | unsigned int |
| 353 | e1_tx_feed_data(unsigned int usb_addr, unsigned int frames) |
| 354 | { |
| 355 | unsigned int ofs; |
| 356 | int n_frames; |
| 357 | |
| 358 | while (frames) { |
| 359 | /* Get some space in FIFO */ |
| 360 | n_frames = e1f_frame_write(&g_e1.tx.fifo, &ofs, frames); |
| 361 | if (!n_frames) { |
| 362 | printf("[!] TX FIFO Overflow %d %d\n", frames, n_frames); |
| 363 | break; |
| 364 | } |
| 365 | |
| 366 | /* Copy from USB to FIFO */ |
| 367 | dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), true, NULL, NULL); |
| 368 | |
| 369 | /* Prepare next */ |
| 370 | usb_addr += n_frames * (32 / 4); |
| 371 | frames -= n_frames; |
| 372 | |
| 373 | /* Wait for DMA completion */ |
| 374 | while (dma_poll()); |
| 375 | } |
| 376 | |
| 377 | return frames; |
| 378 | } |
| 379 | |
| 380 | unsigned int |
| 381 | e1_tx_level(void) |
| 382 | { |
| 383 | return e1f_valid_frames(&g_e1.tx.fifo); |
| 384 | } |
| 385 | |
| 386 | unsigned int |
| 387 | e1_rx_level(void) |
| 388 | { |
| 389 | return e1f_valid_frames(&g_e1.rx.fifo); |
| 390 | } |
| 391 | |
| 392 | void |
| 393 | e1_poll(void) |
| 394 | { |
| 395 | uint32_t bd; |
| 396 | unsigned int ofs; |
| 397 | |
| 398 | /* Active ? */ |
| 399 | if ((g_e1.rx.state == IDLE) && (g_e1.tx.state == IDLE)) |
| 400 | return; |
| 401 | |
| 402 | /* HACK: LED link status */ |
| 403 | if (e1_regs->rx.csr & 2) |
| 404 | led_color(0, 48, 0); |
| 405 | else |
| 406 | led_color(48, 0, 0); |
| 407 | |
| 408 | /* Recover any done TX BD */ |
| 409 | while ( (bd = e1_regs->tx.bd) & E1_BD_VALID ) { |
| 410 | e1f_multiframe_read_discard(&g_e1.tx.fifo); |
| 411 | g_e1.tx.in_flight--; |
| 412 | } |
| 413 | |
| 414 | /* Recover any done RX BD */ |
| 415 | while ( (bd = e1_regs->rx.bd) & E1_BD_VALID ) { |
| 416 | /* FIXME: CRC status ? */ |
| 417 | e1f_multiframe_write_commit(&g_e1.rx.fifo); |
| 418 | if ((bd & (E1_BD_CRC0 | E1_BD_CRC1)) != (E1_BD_CRC0 | E1_BD_CRC1)) |
| 419 | printf("b: %03x\n", bd); |
| 420 | g_e1.rx.in_flight--; |
| 421 | } |
| 422 | |
| 423 | /* Boot procedure */ |
| 424 | if (g_e1.tx.state == BOOT) { |
| 425 | if (e1f_unseen_frames(&g_e1.tx.fifo) < (16 * 5)) |
| 426 | return; |
| 427 | /* HACK: LED flow status */ |
| 428 | led_blink(true, 200, 1000); |
| 429 | led_breathe(true, 100, 200); |
| 430 | } |
| 431 | |
| 432 | /* Handle RX */ |
| 433 | /* Misalign ? */ |
| 434 | if (g_e1.rx.state == RUN) { |
| 435 | if (!(e1_regs->rx.csr & E1_RX_SR_ALIGNED)) { |
| 436 | printf("[!] E1 rx misalign\n"); |
| 437 | g_e1.rx.state = RECOVER; |
| 438 | } |
| 439 | } |
| 440 | |
| 441 | /* Overflow ? */ |
| 442 | if (g_e1.rx.state == RUN) { |
| 443 | if (e1_regs->rx.csr & E1_RX_SR_OVFL) { |
| 444 | printf("[!] E1 overflow %d\n", g_e1.rx.in_flight); |
| 445 | g_e1.rx.state = RECOVER; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | /* Recover ready ? */ |
| 450 | if (g_e1.rx.state == RECOVER) { |
| 451 | if (g_e1.rx.in_flight != 0) |
| 452 | goto done_rx; |
| 453 | e1f_multiframe_empty(&g_e1.rx.fifo); |
| 454 | } |
| 455 | |
| 456 | /* Fill new RX BD */ |
| 457 | while (g_e1.rx.in_flight < 4) { |
| 458 | if (!e1f_multiframe_write_prepare(&g_e1.rx.fifo, &ofs)) |
| 459 | break; |
| 460 | e1_regs->rx.bd = e1f_ofs_to_mf(ofs); |
| 461 | g_e1.rx.in_flight++; |
| 462 | } |
| 463 | |
| 464 | /* Clear overflow if needed */ |
| 465 | if (g_e1.rx.state != RUN) { |
| 466 | e1_regs->rx.csr = g_e1.rx.cr | E1_RX_CR_OVFL_CLR; |
| 467 | g_e1.rx.state = RUN; |
| 468 | } |
| 469 | done_rx: |
| 470 | |
| 471 | /* Handle TX */ |
| 472 | /* Underflow ? */ |
| 473 | if (g_e1.tx.state == RUN) { |
| 474 | if (e1_regs->tx.csr & E1_TX_SR_UNFL) { |
| 475 | printf("[!] E1 underflow %d\n", g_e1.tx.in_flight); |
| 476 | g_e1.tx.state = RECOVER; |
| 477 | } |
| 478 | } |
| 479 | |
| 480 | /* Recover ready ? */ |
| 481 | if (g_e1.tx.state == RECOVER) { |
| 482 | if (e1f_unseen_frames(&g_e1.tx.fifo) < (16 * 5)) |
| 483 | return; |
| 484 | } |
| 485 | |
| 486 | /* Fill new TX BD */ |
| 487 | while (g_e1.tx.in_flight < 4) { |
| 488 | if (!e1f_multiframe_read_peek(&g_e1.tx.fifo, &ofs)) |
| 489 | break; |
| 490 | e1_regs->tx.bd = e1f_ofs_to_mf(ofs); |
| 491 | g_e1.tx.in_flight++; |
| 492 | } |
| 493 | |
| 494 | /* Clear underflow if needed */ |
| 495 | if (g_e1.tx.state != RUN) { |
| 496 | e1_regs->tx.csr = g_e1.tx.cr | E1_TX_CR_UNFL_CLR; |
| 497 | g_e1.tx.state = RUN; |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | void |
| 502 | e1_debug_print(bool data) |
| 503 | { |
| 504 | volatile uint8_t *p; |
| 505 | |
| 506 | puts("E1\n"); |
| 507 | printf("CSR: Rx %04x / Tx %04x\n", e1_regs->rx.csr, e1_regs->tx.csr); |
| 508 | printf("InF: Rx %d / Tx %d\n", g_e1.rx.in_flight, g_e1.tx.in_flight); |
| 509 | printf("Sta: Rx %d / Tx %d\n", g_e1.rx.state, g_e1.tx.state); |
| 510 | |
| 511 | e1f_debug(&g_e1.rx.fifo, "Rx FIFO"); |
| 512 | e1f_debug(&g_e1.tx.fifo, "Tx FIFO"); |
| 513 | |
| 514 | if (data) { |
| 515 | puts("\nE1 Data\n"); |
| 516 | for (int f=0; f<16; f++) { |
| 517 | p = e1_data_ptr(0, f, 0); |
| 518 | for (int ts=0; ts<32; ts++) |
| 519 | printf(" %02x", p[ts]); |
| 520 | printf("\n"); |
| 521 | } |
| 522 | } |
| 523 | } |