Sylvain Munaut | bd83e53 | 2020-09-15 22:11:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * i2c_master_tb.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 7 | * SPDX-License-Identifier: CERN-OHL-P-2.0 |
| 8 | */ |
| 9 | |
| 10 | `default_nettype none |
| 11 | `timescale 1ns / 100ps |
| 12 | |
| 13 | module i2c_master_tb; |
| 14 | |
| 15 | // Signals |
| 16 | // ------- |
| 17 | |
| 18 | reg rst = 1'b1; |
| 19 | reg clk = 1'b0; |
| 20 | |
| 21 | |
| 22 | // Test bench |
| 23 | // ---------- |
| 24 | |
| 25 | // Setup recording |
| 26 | initial begin |
| 27 | $dumpfile("i2c_master_tb.vcd"); |
| 28 | $dumpvars(0,i2c_master_tb); |
| 29 | end |
| 30 | |
| 31 | // Reset pulse |
| 32 | initial begin |
| 33 | # 200 rst = 0; |
| 34 | # 1000000 $finish; |
| 35 | end |
| 36 | |
| 37 | // Clocks |
| 38 | always #10 clk = !clk; |
| 39 | |
| 40 | |
| 41 | // DUT |
| 42 | // --- |
| 43 | |
| 44 | wire scl_oe; |
| 45 | wire sda_oe; |
| 46 | wire sda_i; |
| 47 | |
| 48 | reg [7:0] data_in; |
| 49 | reg ack_in; |
| 50 | reg [1:0] cmd; |
| 51 | reg stb; |
| 52 | |
| 53 | wire [7:0] data_out; |
| 54 | wire ack_out; |
| 55 | |
| 56 | wire ready; |
| 57 | |
| 58 | i2c_master #( |
| 59 | .DW(3) |
| 60 | ) dut_I ( |
| 61 | .scl_oe(scl_oe), |
| 62 | .sda_oe(sda_oe), |
| 63 | .sda_i(sda_i), |
| 64 | .data_in(data_in), |
| 65 | .ack_in(ack_in), |
| 66 | .cmd(cmd), |
| 67 | .stb(stb), |
| 68 | .data_out(data_out), |
| 69 | .ack_out(ack_out), |
| 70 | .ready(ready), |
| 71 | .clk(clk), |
| 72 | .rst(rst) |
| 73 | ); |
| 74 | |
| 75 | |
| 76 | // Stimulus |
| 77 | // -------- |
| 78 | |
| 79 | assign sda_i = 1'b0; |
| 80 | |
| 81 | task i2c_cmd; |
| 82 | input [1:0] a_cmd; |
| 83 | input [7:0] a_data; |
| 84 | input a_ack; |
| 85 | begin |
| 86 | cmd <= a_cmd; |
| 87 | data_in <= a_data; |
| 88 | ack_in <= a_ack; |
| 89 | stb <= 1'b1; |
| 90 | @(posedge clk); |
| 91 | stb <= 1'b0; |
| 92 | @(posedge clk); |
| 93 | wait (ready == 1'b1); |
| 94 | @(posedge clk); |
| 95 | end |
| 96 | endtask |
| 97 | |
| 98 | initial begin |
| 99 | // Reset |
| 100 | data_in <= 8'h00; |
| 101 | ack_in <= 1'b0; |
| 102 | cmd <= 2'b00; |
| 103 | stb <= 1'b0; |
| 104 | |
| 105 | wait (rst == 1'b0); |
| 106 | wait (ready == 1'b1); |
| 107 | @(posedge clk); |
| 108 | |
| 109 | // Issue commands |
| 110 | i2c_cmd(2'b00, 8'h00, 1'b0); |
| 111 | i2c_cmd(2'b10, 8'ha5, 1'b0); |
| 112 | i2c_cmd(2'b11, 8'h00, 1'b0); |
| 113 | i2c_cmd(2'b01, 8'h00, 1'b0); |
| 114 | |
| 115 | end |
| 116 | |
| 117 | endmodule |