Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * soc_bram.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com> |
| 7 | * SPDX-License-Identifier: CERN-OHL-P-2.0 |
| 8 | */ |
| 9 | |
| 10 | `default_nettype none |
| 11 | |
| 12 | module soc_bram #( |
| 13 | parameter integer AW = 8, |
| 14 | parameter INIT_FILE = "" |
| 15 | )( |
| 16 | input wire [AW-1:0] addr, |
| 17 | output reg [31:0] rdata, |
| 18 | input wire [31:0] wdata, |
| 19 | input wire [ 3:0] wmsk, |
| 20 | input wire we, |
| 21 | input wire clk |
| 22 | ); |
| 23 | |
| 24 | reg [31:0] mem [0:(1<<AW)-1]; |
| 25 | |
| 26 | initial |
| 27 | if (INIT_FILE != "") |
| 28 | $readmemh(INIT_FILE, mem); |
| 29 | |
| 30 | always @(posedge clk) begin |
| 31 | rdata <= mem[addr]; |
| 32 | if (we & ~wmsk[0]) mem[addr][ 7: 0] <= wdata[ 7: 0]; |
| 33 | if (we & ~wmsk[1]) mem[addr][15: 8] <= wdata[15: 8]; |
| 34 | if (we & ~wmsk[2]) mem[addr][23:16] <= wdata[23:16]; |
| 35 | if (we & ~wmsk[3]) mem[addr][31:24] <= wdata[31:24]; |
| 36 | end |
| 37 | |
| 38 | endmodule // soc_bram |