| Sylvain Munaut | 26bc465 | 2020-09-14 10:19:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * start.S |
| 3 | * |
| 4 | * Startup code taken from picosoc/picorv32 and adapted for use here |
| 5 | * |
| 6 | * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> |
| 7 | * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com> |
| 8 | * |
| 9 | * Permission to use, copy, modify, and/or distribute this software for any |
| 10 | * purpose with or without fee is hereby granted, provided that the above |
| 11 | * copyright notice and this permission notice appear in all copies. |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | .section .text.start |
| 23 | .global _start |
| 24 | _start: |
| 25 | |
| 26 | // zero-initialize register file |
| 27 | addi x1, zero, 0 |
| 28 | // x2 (sp) is initialized by reset |
| 29 | addi x3, zero, 0 |
| 30 | addi x4, zero, 0 |
| 31 | addi x5, zero, 0 |
| 32 | addi x6, zero, 0 |
| 33 | addi x7, zero, 0 |
| 34 | addi x8, zero, 0 |
| 35 | addi x9, zero, 0 |
| 36 | addi x10, zero, 0 |
| 37 | addi x11, zero, 0 |
| 38 | addi x12, zero, 0 |
| 39 | addi x13, zero, 0 |
| 40 | addi x14, zero, 0 |
| 41 | addi x15, zero, 0 |
| 42 | addi x16, zero, 0 |
| 43 | addi x17, zero, 0 |
| 44 | addi x18, zero, 0 |
| 45 | addi x19, zero, 0 |
| 46 | addi x20, zero, 0 |
| 47 | addi x21, zero, 0 |
| 48 | addi x22, zero, 0 |
| 49 | addi x23, zero, 0 |
| 50 | addi x24, zero, 0 |
| 51 | addi x25, zero, 0 |
| 52 | addi x26, zero, 0 |
| 53 | addi x27, zero, 0 |
| 54 | addi x28, zero, 0 |
| 55 | addi x29, zero, 0 |
| 56 | addi x30, zero, 0 |
| 57 | addi x31, zero, 0 |
| 58 | |
| 59 | #ifdef BOOT_DEBUG |
| 60 | // Set UART divisor |
| 61 | li a0, 0x81000000 |
| 62 | li a1, 28 |
| 63 | sw a1, 4(a0) |
| 64 | |
| 65 | // Output '1' |
| 66 | li a1, 49 |
| 67 | sw a1, 0(a0) |
| 68 | #endif |
| 69 | |
| 70 | // copy data section |
| 71 | la a0, _sidata |
| 72 | la a1, _sdata |
| 73 | la a2, _edata |
| 74 | bge a1, a2, end_init_data |
| 75 | loop_init_data: |
| 76 | lw a3, 0(a0) |
| 77 | sw a3, 0(a1) |
| 78 | addi a0, a0, 4 |
| 79 | addi a1, a1, 4 |
| 80 | blt a1, a2, loop_init_data |
| 81 | end_init_data: |
| 82 | |
| 83 | #ifdef BOOT_DEBUG |
| 84 | // Output '2' |
| 85 | li a0, 0x81000000 |
| 86 | li a1, 50 |
| 87 | sw a1, 0(a0) |
| 88 | #endif |
| 89 | |
| 90 | // zero-init bss section |
| 91 | la a0, _sbss |
| 92 | la a1, _ebss |
| 93 | bge a0, a1, end_init_bss |
| 94 | loop_init_bss: |
| 95 | sw zero, 0(a0) |
| 96 | addi a0, a0, 4 |
| 97 | blt a0, a1, loop_init_bss |
| 98 | end_init_bss: |
| 99 | |
| 100 | #ifdef BOOT_DEBUG |
| 101 | // Output '3' |
| 102 | li a0, 0x81000000 |
| 103 | li a1, 51 |
| 104 | sw a1, 0(a0) |
| 105 | #endif |
| 106 | |
| 107 | // call main |
| 108 | call main |
| 109 | loop: |
| 110 | j loop |