Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * boot.S |
| 3 | * |
| 4 | * SPI boot code |
| 5 | * |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 6 | * Copyright (C) 2020-2022 Sylvain Munaut <tnt@246tNt.com> |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: MIT |
| 8 | */ |
| 9 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 10 | // #define BOOT_DEBUG |
| 11 | // (also set UART_DIV for the board below !) |
| 12 | |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 13 | #ifndef APP_FLASH_ADDR |
| 14 | #define APP_FLASH_ADDR 0x00100000 |
| 15 | #endif |
| 16 | |
| 17 | #ifndef APP_SRAM_ADDR |
| 18 | #define APP_SRAM_ADDR 0x00020000 |
| 19 | #endif |
| 20 | |
| 21 | #ifndef APP_SIZE |
| 22 | #define APP_SIZE 0x00010000 |
| 23 | #endif |
| 24 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 25 | .equ UART_BASE, 0x81000000 |
| 26 | .equ UART_DIV, 29 // 30.72 MHz / (29+2) ~= 1 Mbaud (icE1usb) |
| 27 | //.equ UART_DIV, 22 // 24 MHz / (22+2) ~= 1 Mbaud (e1-tracer) |
| 28 | |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 29 | .section .text.start |
| 30 | .global _start |
| 31 | _start: |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 32 | // Debug |
| 33 | #ifdef BOOT_DEBUG |
| 34 | // Set UART divisor |
| 35 | li a0, UART_BASE |
| 36 | li a1, UART_DIV |
| 37 | sw a1, 4(a0) |
| 38 | |
| 39 | // Output 'a' |
| 40 | li a1, 97 |
| 41 | sw a1, 0(a0) |
| 42 | #endif |
| 43 | |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 44 | // SPI init |
| 45 | jal spi_init |
| 46 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 47 | // Debug |
| 48 | #ifdef BOOT_DEBUG |
| 49 | // Output 'b' |
| 50 | li a0, UART_BASE |
| 51 | li a1, 98 |
| 52 | sw a1, 0(a0) |
| 53 | #endif |
| 54 | |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 55 | // Read from flash to SRAM |
| 56 | li a0, APP_SRAM_ADDR |
| 57 | li a1, APP_SIZE |
| 58 | li a2, APP_FLASH_ADDR |
| 59 | jal spi_flash_read |
| 60 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 61 | // Debug |
| 62 | #ifdef BOOT_DEBUG |
| 63 | // Output 'c' |
| 64 | li a0, UART_BASE |
| 65 | li a1, 99 |
| 66 | sw a1, 0(a0) |
| 67 | #endif |
| 68 | |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 69 | // Setup reboot code |
| 70 | li t0, 0x0002006f |
| 71 | sw t0, 0(zero) |
| 72 | |
| 73 | // Jump to main code |
| 74 | j APP_SRAM_ADDR |
| 75 | |
| 76 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 77 | // --------------------------------------------------------------------------- |
| 78 | // SB_SPI driver code |
| 79 | // --------------------------------------------------------------------------- |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 80 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 81 | // Register definitions |
| 82 | |
| 83 | .equ SPI_BASE, 0x80000000 |
| 84 | |
| 85 | .equ SPICR0, 4 * 0x08 |
| 86 | .equ SPICR1, 4 * 0x09 |
| 87 | .equ SPICR2, 4 * 0x0a |
| 88 | .equ SPIBR, 4 * 0x0b |
| 89 | .equ SPISR, 4 * 0x0c |
| 90 | .equ SPITXDR, 4 * 0x0d |
| 91 | .equ SPIRXDR, 4 * 0x0e |
| 92 | .equ SPICSR, 4 * 0x0f |
| 93 | |
| 94 | |
| 95 | // Initializes te SPI hardware |
| 96 | // |
| 97 | // Clobbers a0, a1 |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 98 | |
| 99 | spi_init: |
| 100 | li a0, SPI_BASE |
| 101 | |
| 102 | li a1, 0xff |
| 103 | sw a1, SPICR0(a0) |
| 104 | |
| 105 | li a1, 0x80 |
| 106 | sw a1, SPICR1(a0) |
| 107 | |
| 108 | li a1, 0xc0 |
| 109 | sw a1, SPICR2(a0) |
| 110 | |
| 111 | li a1, 0x03 |
| 112 | sw a1, SPIBR(a0) |
| 113 | |
| 114 | li a1, 0x0f |
| 115 | sw a1, SPICSR(a0) |
| 116 | |
| 117 | ret |
| 118 | |
| 119 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 120 | // Reads a block of memory from SPI flash |
| 121 | // |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 122 | // Params: |
| 123 | // a0 - destination pointer |
| 124 | // a1 - length (bytes) |
| 125 | // a2 - flash offset |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 126 | // Clobbers t0, t1, s0, s1, s2 |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 127 | |
| 128 | spi_flash_read: |
| 129 | // Save params |
| 130 | mv s0, a0 |
| 131 | mv s1, a1 |
| 132 | mv s2, ra |
| 133 | |
| 134 | // Setup CS |
| 135 | li t0, SPI_BASE |
| 136 | li t1, 0x0e |
| 137 | sw t1, SPICSR(t0) |
| 138 | |
| 139 | // Send command |
| 140 | li a0, 0x03 |
| 141 | jal _spi_do_one |
| 142 | |
| 143 | srli a0, a2, 16 |
| 144 | and a0, a0, 0xff |
| 145 | jal _spi_do_one |
| 146 | |
| 147 | srli a0, a2, 8 |
| 148 | and a0, a0, 0xff |
| 149 | jal _spi_do_one |
| 150 | |
| 151 | and a0, a2, 0xff |
| 152 | jal _spi_do_one |
| 153 | |
| 154 | // Read loop |
| 155 | _spi_loop: |
| 156 | li a0, 0x00 |
| 157 | jal _spi_do_one |
| 158 | sb a0, 0(s0) |
| 159 | addi s0, s0, 1 |
| 160 | addi s1, s1, -1 |
| 161 | bne s1, zero, _spi_loop |
| 162 | |
| 163 | // Release CS |
| 164 | li t0, SPI_BASE |
| 165 | li t1, 0x0f |
| 166 | sw t1, SPICSR(t0) |
| 167 | |
| 168 | // Done |
| 169 | jr s2 |
| 170 | |
| 171 | |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 172 | // Performs a single 8 bit SPI xfer |
| 173 | // |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 174 | // Params: a0 - Data to TX |
| 175 | // Returns: a0 - RX data |
| 176 | // Clobbers t0, t1 |
Sylvain Munaut | 90ca05d | 2022-05-02 20:45:08 +0200 | [diff] [blame] | 177 | |
Sylvain Munaut | 21b03ba | 2020-09-14 10:01:45 +0200 | [diff] [blame] | 178 | _spi_do_one: |
| 179 | li t0, SPI_BASE |
| 180 | li t1, 0x08 |
| 181 | |
| 182 | // Write TX data |
| 183 | sw a0, SPITXDR(t0) |
| 184 | |
| 185 | // Wait for RXRDY |
| 186 | 1: |
| 187 | lw a0, SPISR(t0) |
| 188 | and a0, a0, t1 |
| 189 | bne a0, t1, 1b |
| 190 | |
| 191 | // Read RX data |
| 192 | lw a0, SPIRXDR(t0) |
| 193 | |
| 194 | // Done |
| 195 | ret |