Sylvain Munaut | bd83e53 | 2020-09-15 22:11:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * top.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Top-level for the icE1usb production boards |
| 7 | * |
| 8 | * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com> |
| 9 | * SPDX-License-Identifier: CERN-OHL-S-2.0 |
| 10 | */ |
| 11 | |
| 12 | `default_nettype none |
| 13 | |
| 14 | module top ( |
| 15 | // E1 PHY |
| 16 | input wire e1A_rx_hi_p, |
| 17 | // input wire e1A_rx_hi_n, |
| 18 | input wire e1A_rx_lo_p, |
| 19 | // input wire e1A_rx_lo_n, |
| 20 | output wire e1A_tx_hi, |
| 21 | output wire e1A_tx_lo, |
| 22 | |
| 23 | input wire e1B_rx_hi_p, |
| 24 | // input wire e1B_rx_hi_n, |
| 25 | input wire e1B_rx_lo_p, |
| 26 | // input wire e1B_rx_lo_n, |
| 27 | output wire e1B_tx_hi, |
| 28 | output wire e1B_tx_lo, |
| 29 | |
| 30 | output wire [1:0] e1_rx_bias, |
| 31 | |
| 32 | // USB |
| 33 | inout wire usb_dp, |
| 34 | inout wire usb_dn, |
| 35 | output wire usb_pu, |
| 36 | |
| 37 | // Flash |
| 38 | inout wire flash_mosi, |
| 39 | inout wire flash_miso, |
| 40 | inout wire flash_clk, |
| 41 | inout wire flash_cs_n, |
| 42 | |
| 43 | // LED Shift register + Button input |
| 44 | inout wire e1_led_rclk, |
| 45 | |
| 46 | // GPS |
| 47 | output wire gps_reset_n, |
| 48 | input wire gps_rx, |
| 49 | output wire gps_tx, |
| 50 | input wire gps_pps, |
| 51 | |
| 52 | // I2C |
| 53 | inout wire i2c_sda, |
| 54 | inout wire i2c_scl, |
| 55 | |
| 56 | // GPIOs |
| 57 | inout wire [2:0] gpio, |
| 58 | |
| 59 | // Clock (30.72 MHz) |
| 60 | input wire clk_in, |
| 61 | output wire clk_tune_hi, |
| 62 | output wire clk_tune_lo, |
| 63 | |
| 64 | // Debug UART |
| 65 | input wire dbg_rx, |
| 66 | output wire dbg_tx, |
| 67 | |
| 68 | // RGB LEDs |
| 69 | output wire [2:0] rgb |
| 70 | ); |
| 71 | |
| 72 | localparam integer WB_N = 3; |
| 73 | |
| 74 | genvar i; |
| 75 | |
| 76 | |
| 77 | // Signals |
| 78 | // ------- |
| 79 | |
| 80 | // Flash SPI internal signals |
| 81 | wire flash_mosi_i, flash_miso_i, flash_clk_i; |
| 82 | wire flash_mosi_o, flash_miso_o, flash_clk_o; |
| 83 | wire flash_mosi_oe, flash_miso_oe, flash_clk_oe; |
| 84 | wire flash_csn_o; |
| 85 | |
| 86 | // Peripheral wishbone |
| 87 | wire [15:0] wb_addr; |
| 88 | wire [31:0] wb_rdata [0:WB_N-1]; |
| 89 | wire [31:0] wb_wdata; |
| 90 | wire [ 3:0] wb_wmsk; |
| 91 | wire wb_we; |
| 92 | wire [WB_N-1:0] wb_cyc; |
| 93 | wire [WB_N-1:0] wb_ack; |
| 94 | |
| 95 | wire [(WB_N*32)-1:0] wb_rdata_flat; |
| 96 | |
| 97 | // Ticks |
| 98 | wire [1:0] tick_e1_rx; |
| 99 | wire [1:0] tick_e1_tx; |
| 100 | wire tick_usb_sof; |
| 101 | |
| 102 | // I2C |
| 103 | wire i2c_scl_oe; |
| 104 | wire i2c_sda_oe; |
| 105 | wire i2c_sda_i; |
| 106 | |
| 107 | // Led & Button |
| 108 | wire [7:0] e1_led_state; |
| 109 | wire e1_led_run; |
| 110 | wire e1_led_active; |
| 111 | |
| 112 | wire spi_req; |
| 113 | wire spi_gnt; |
| 114 | |
| 115 | wire [7:0] sr_val; |
| 116 | wire sr_go; |
| 117 | wire sr_rdy; |
| 118 | |
| 119 | wire btn_val; |
| 120 | wire btn_stb; |
| 121 | |
| 122 | // Clocks / Reset |
| 123 | wire rst_req; |
| 124 | |
| 125 | wire clk_sys; |
| 126 | wire rst_sys; |
| 127 | wire clk_48m; |
| 128 | wire rst_48m; |
| 129 | |
| 130 | |
| 131 | // SoC base |
| 132 | // -------- |
| 133 | |
| 134 | // Instance |
| 135 | soc_base #( |
| 136 | .WB_N(WB_N), |
| 137 | .E1_N(2), |
| 138 | .E1_UNIT_HAS_RX(2'b01), |
| 139 | .E1_UNIT_HAS_TX(2'b01), |
| 140 | .E1_LIU(0) |
| 141 | ) soc_I ( |
| 142 | .e1_rx_hi_p ({e1B_rx_hi_p, e1A_rx_hi_p}), |
| 143 | // .e1_rx_hi_n ({e1B_rx_hi_n, e1A_rx_hi_n}), |
| 144 | .e1_rx_lo_p ({e1B_rx_lo_p, e1A_rx_lo_p}), |
| 145 | // .e1_rx_lo_n ({e1B_rx_lo_n, e1A_rx_lo_n}), |
| 146 | .e1_tx_hi ({e1B_tx_hi, e1A_tx_hi }), |
| 147 | .e1_tx_lo ({e1B_tx_lo, e1A_tx_lo }), |
| 148 | .e1_rx_data (), |
| 149 | .e1_rx_clk (), |
| 150 | .e1_tx_data (), |
| 151 | .e1_tx_clk (), |
| 152 | .usb_dp (usb_dp), |
| 153 | .usb_dn (usb_dn), |
| 154 | .usb_pu (usb_pu), |
| 155 | .flash_mosi_i (flash_mosi_i), |
| 156 | .flash_mosi_o (flash_mosi_o), |
| 157 | .flash_mosi_oe(flash_mosi_oe), |
| 158 | .flash_miso_i (flash_miso_i), |
| 159 | .flash_miso_o (flash_miso_o), |
| 160 | .flash_miso_oe(flash_miso_oe), |
| 161 | .flash_clk_i (flash_clk_i), |
| 162 | .flash_clk_o (flash_clk_o), |
| 163 | .flash_clk_oe (flash_clk_oe), |
| 164 | .flash_csn_o (flash_csn_o), |
| 165 | .dbg_rx (dbg_rx), |
| 166 | .dbg_tx (dbg_tx), |
| 167 | .rgb (rgb), |
| 168 | .wb_m_addr (wb_addr), |
| 169 | .wb_m_rdata (wb_rdata_flat), |
| 170 | .wb_m_wdata (wb_wdata), |
| 171 | .wb_m_wmsk (wb_wmsk), |
| 172 | .wb_m_we (wb_we), |
| 173 | .wb_m_cyc (wb_cyc), |
| 174 | .wb_m_ack (wb_ack), |
| 175 | .tick_e1_rx (tick_e1_rx), |
| 176 | .tick_e1_tx (tick_e1_tx), |
| 177 | .tick_usb_sof (tick_usb_sof), |
| 178 | .clk_sys (clk_sys), |
| 179 | .rst_sys (rst_sys), |
| 180 | .clk_48m (clk_48m), |
| 181 | .rst_48m (rst_48m) |
| 182 | ); |
| 183 | |
| 184 | // WB read data flattening |
| 185 | for (i=0; i<WB_N; i=i+1) |
| 186 | assign wb_rdata_flat[i*32+:32] = wb_rdata[i]; |
| 187 | |
| 188 | |
| 189 | // Dummy channel |
| 190 | // ------------- |
| 191 | |
| 192 | wire [1:0] e1_dummy; |
| 193 | |
| 194 | SB_IO #( |
| 195 | .PIN_TYPE(6'b000000), |
| 196 | .PULLUP(1'b0), |
| 197 | .NEG_TRIGGER(1'b0), |
| 198 | .IO_STANDARD("SB_LVDS_INPUT") |
| 199 | ) e1_dummy_rx_I[1:0] ( |
| 200 | .PACKAGE_PIN({e1B_rx_hi_p, e1B_rx_lo_p}), |
| 201 | .LATCH_INPUT_VALUE(1'b0), |
| 202 | .CLOCK_ENABLE(1'b1), |
| 203 | .INPUT_CLK(clk_sys), |
| 204 | .OUTPUT_CLK(1'b0), |
| 205 | .OUTPUT_ENABLE(1'b0), |
| 206 | .D_OUT_0(1'b0), |
| 207 | .D_OUT_1(1'b0), |
| 208 | .D_IN_0(e1_dummy), |
| 209 | .D_IN_1() |
| 210 | ); |
| 211 | |
| 212 | SB_IO #( |
| 213 | .PIN_TYPE(6'b010100), |
| 214 | .PULLUP(1'b0), |
| 215 | .NEG_TRIGGER(1'b0), |
| 216 | .IO_STANDARD("SB_LVCMOS") |
| 217 | ) e1_dummy_tx_I[1:0] ( |
| 218 | .PACKAGE_PIN({e1B_tx_hi, e1B_tx_lo}), |
| 219 | .LATCH_INPUT_VALUE(1'b0), |
| 220 | .CLOCK_ENABLE(1'b1), |
| 221 | .INPUT_CLK(1'b0), |
| 222 | .OUTPUT_CLK(clk_sys), |
| 223 | .OUTPUT_ENABLE(1'b0), |
| 224 | .D_OUT_0(e1_dummy), |
| 225 | .D_OUT_1(1'b0), |
| 226 | .D_IN_0(), |
| 227 | .D_IN_1() |
| 228 | ); |
| 229 | |
| 230 | |
| 231 | // Misc [0] |
| 232 | // ---- |
| 233 | |
| 234 | misc misc_I ( |
| 235 | .e1_rx_bias (e1_rx_bias), |
| 236 | .clk_tune_hi (clk_tune_hi), |
| 237 | .clk_tune_lo (clk_tune_lo), |
| 238 | .gps_reset_n (gps_reset_n), |
| 239 | .gps_pps (gps_pps), |
| 240 | .gpio (gpio), |
| 241 | .e1_led_state (e1_led_state), |
| 242 | .e1_led_run (e1_led_run), |
| 243 | .e1_led_active (e1_led_active), |
| 244 | .btn_val (btn_val), |
| 245 | .btn_stb (btn_stb), |
| 246 | .tick_e1_rx (tick_e1_rx), |
| 247 | .tick_e1_tx (tick_e1_tx), |
| 248 | .tick_usb_sof (tick_usb_sof), |
| 249 | .rst_req (rst_req), |
| 250 | .wb_addr (wb_addr[7:0]), |
| 251 | .wb_rdata (wb_rdata[0]), |
| 252 | .wb_wdata (wb_wdata), |
| 253 | .wb_we (wb_we), |
| 254 | .wb_cyc (wb_cyc[0]), |
| 255 | .wb_ack (wb_ack[0]), |
| 256 | .clk (clk_sys), |
| 257 | .rst (rst_sys) |
| 258 | ); |
| 259 | |
| 260 | |
| 261 | // GPS UART [1] |
| 262 | // -------- |
| 263 | |
| 264 | uart_wb #( |
| 265 | .DIV_WIDTH(12), |
| 266 | .DW(32) |
| 267 | ) gps_uart_I ( |
| 268 | .uart_tx (gps_tx), |
| 269 | .uart_rx (gps_rx), |
| 270 | .wb_addr (wb_addr[1:0]), |
| 271 | .wb_rdata (wb_rdata[1]), |
| 272 | .wb_wdata (wb_wdata), |
| 273 | .wb_we (wb_we), |
| 274 | .wb_cyc (wb_cyc[1]), |
| 275 | .wb_ack (wb_ack[1]), |
| 276 | .clk (clk_sys), |
| 277 | .rst (rst_sys) |
| 278 | ); |
| 279 | |
| 280 | |
| 281 | // I2C [2] |
| 282 | // --- |
| 283 | |
| 284 | // Controller |
| 285 | i2c_master_wb #( |
| 286 | .DW(3), |
| 287 | .FIFO_DEPTH(0) |
| 288 | ) i2c_I ( |
| 289 | .scl_oe (i2c_scl_oe), |
| 290 | .sda_oe (i2c_sda_oe), |
| 291 | .sda_i (i2c_sda_i), |
| 292 | .wb_rdata(wb_rdata[2]), |
| 293 | .wb_wdata(wb_wdata), |
| 294 | .wb_we (wb_we), |
| 295 | .wb_cyc (wb_cyc[2]), |
| 296 | .wb_ack (wb_ack[2]), |
| 297 | .ready (), |
| 298 | .clk (clk_sys), |
| 299 | .rst (rst_sys) |
| 300 | ); |
| 301 | |
| 302 | // IOBs |
| 303 | SB_IO #( |
| 304 | .PIN_TYPE(6'b110101), |
| 305 | .PULLUP(1'b1), |
| 306 | .IO_STANDARD("SB_LVCMOS") |
| 307 | ) i2c_scl_iob_I ( |
| 308 | .PACKAGE_PIN (i2c_scl), |
| 309 | .OUTPUT_CLK (clk_sys), |
| 310 | .OUTPUT_ENABLE(i2c_scl_oe), |
| 311 | .D_OUT_0 (1'b0) |
| 312 | ); |
| 313 | |
| 314 | SB_IO #( |
| 315 | .PIN_TYPE(6'b110100), |
| 316 | .PULLUP(1'b1), |
| 317 | .IO_STANDARD("SB_LVCMOS") |
| 318 | ) i2c_sda_iob_I ( |
| 319 | .PACKAGE_PIN (i2c_sda), |
| 320 | .INPUT_CLK (clk_sys), |
| 321 | .OUTPUT_CLK (clk_sys), |
| 322 | .OUTPUT_ENABLE(i2c_sda_oe), |
| 323 | .D_OUT_0 (1'b0), |
| 324 | .D_IN_0 (i2c_sda_i) |
| 325 | ); |
| 326 | |
| 327 | |
| 328 | // E1 LEDs & Button |
| 329 | // ---------------- |
| 330 | |
| 331 | // Blink pattern generator |
| 332 | led_blinker blinker_I ( |
| 333 | .led_state(e1_led_state), |
| 334 | .sr_val (sr_val), |
| 335 | .sr_go (sr_go), |
| 336 | .sr_rdy (sr_rdy), |
| 337 | .clk (clk_sys), |
| 338 | .rst (rst_sys) |
| 339 | ); |
| 340 | |
| 341 | // Interface |
| 342 | sr_btn_if #( |
| 343 | .TICK_LOG2_DIV(3) |
| 344 | ) spi_mux_I ( |
| 345 | .flash_mosi (flash_mosi), |
| 346 | .flash_miso (flash_miso), |
| 347 | .flash_clk (flash_clk), |
| 348 | .flash_cs_n (flash_cs_n), |
| 349 | .e1_led_rclk (e1_led_rclk), |
| 350 | .spi_mosi_i (flash_mosi_i), |
| 351 | .spi_mosi_o (flash_mosi_o), |
| 352 | .spi_mosi_oe (flash_mosi_oe), |
| 353 | .spi_miso_i (flash_miso_i), |
| 354 | .spi_miso_o (flash_miso_o), |
| 355 | .spi_miso_oe (flash_miso_oe), |
| 356 | .spi_clk_i (flash_clk_i), |
| 357 | .spi_clk_o (flash_clk_o), |
| 358 | .spi_clk_oe (flash_clk_oe), |
| 359 | .spi_csn_o (flash_csn_o), |
| 360 | .spi_csn_oe (1'b1), |
| 361 | .spi_req (spi_req), |
| 362 | .spi_gnt (spi_gnt), |
| 363 | .sr_val (sr_val), |
| 364 | .sr_go (sr_go), |
| 365 | .sr_rdy (sr_rdy), |
| 366 | .btn_val (btn_val), |
| 367 | .btn_stb (btn_stb), |
| 368 | .clk (clk_sys), |
| 369 | .rst (rst_sys) |
| 370 | ); |
| 371 | |
| 372 | assign spi_req = ~e1_led_run; |
| 373 | assign e1_led_active = ~spi_gnt; |
| 374 | |
| 375 | |
| 376 | // Clock / Reset |
| 377 | // ------------- |
| 378 | |
| 379 | sysmgr sys_mgr_I ( |
| 380 | .clk_in (clk_in), |
| 381 | .rst_in (rst_req), |
| 382 | .clk_sys(clk_sys), |
| 383 | .rst_sys(rst_sys), |
| 384 | .clk_48m(clk_48m), |
| 385 | .rst_48m(rst_48m) |
| 386 | ); |
| 387 | |
| 388 | endmodule // top |