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Sylvain Munaut546493e2020-09-14 10:12:56 +02001/*
2 * misc.v
3 *
4 * vim: ts=4 sw=4
5 *
6 * Misc peripheral functions
7 *
8 * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
9 * SPDX-License-Identifier: CERN-OHL-S-2.0
10 */
11
12`default_nettype none
13
14module misc (
15 // Button
16 input wire btn,
17
18 // Ticks
19 input wire [1:0] tick_e1_rx,
20 input wire tick_usb_sof,
21
22 // Reset request
23 output wire rst_req,
24
25 // Wishbone
26 input wire [ 7:0] wb_addr,
27 output reg [31:0] wb_rdata,
28 input wire [31:0] wb_wdata,
29 input wire wb_we,
30 input wire wb_cyc,
31 output reg wb_ack,
32
33 // Clock / Reset
34 input wire clk,
35 input wire rst
36);
37
38 // Signals
39 // -------
40
41 genvar i;
42
43 // Bus
44 wire bus_clr;
45 reg bus_we_boot;
46
47 // Counters
48 reg [15:0] cnt_e1_rx[0:1];
49 reg [15:0] cap_e1_rx[0:1];
50 reg [31:0] cnt_time;
51
52 // Boot
53 reg [1:0] boot_sel;
54 reg boot_now;
55
56
57 // Bus interface
58 // -------------
59
60 // Ack
61 always @(posedge clk)
62 wb_ack <= wb_cyc & ~wb_ack;
63
64 assign bus_clr = ~wb_cyc | wb_ack;
65
66 // Write enables
67 always @(posedge clk)
68 if (bus_clr | ~wb_we)
69 bus_we_boot <= 1'b0;
70 else
71 bus_we_boot <= wb_addr == 4'h0;
72
73 // Read mux
74 always @(posedge clk)
75 if (bus_clr)
76 wb_rdata <= 32'h00000000;
77 else
78 case (wb_addr[3:0])
Sylvain Munautc1d117b2020-09-15 21:57:52 +020079 4'h4: wb_rdata <= { 16'h000, cap_e1_rx[0] };
80 4'h5: wb_rdata <= { 16'h000, cap_e1_rx[1] };
Sylvain Munaut546493e2020-09-14 10:12:56 +020081 4'h7: wb_rdata <= cnt_time;
82 default: wb_rdata <= 32'hxxxxxxxx;
83 endcase
84
85
86 // Counters
87 // --------
88
89 // E1 ticks
90 for (i=0; i<2; i=i+1) begin
91
92 always @(posedge clk or posedge rst)
93 if (rst)
94 cnt_e1_rx[i] <= 16'h0000;
95 else if (tick_e1_rx[i])
96 cnt_e1_rx[i] <= cnt_e1_rx[i] + 1;
97
98 always @(posedge clk)
99 if (tick_usb_sof)
100 cap_e1_rx[i] <= cnt_e1_rx[i];
101
102 end
103
104 // Time counter
105 always @(posedge clk)
106 if (rst)
107 cnt_time <= 32'h00000000;
108 else
109 cnt_time <= cnt_time + 1;
110
111
112 // DFU / Reboot
113 // ------------
114
115 always @(posedge clk or posedge rst)
116 if (rst) begin
117 boot_now <= 1'b0;
118 boot_sel <= 2'b00;
119 end else if (bus_we_boot) begin
120 boot_now <= wb_wdata[2];
121 boot_sel <= wb_wdata[1:0];
122 end
123
124 dfu_helper #(
125 .TIMER_WIDTH(26),
126 .BTN_MODE(3),
127 .DFU_MODE(0)
128 ) dfu_I (
129 .boot_sel(boot_sel),
130 .boot_now(boot_now),
131 .btn_pad (btn),
132 .btn_val (),
133 .rst_req (rst_req),
134 .clk (clk),
135 .rst (rst)
136 );
137
138endmodule // misc