Sylvain Munaut | ff0ab3e | 2020-10-03 20:15:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * capcnt.v |
| 3 | * |
| 4 | * Simple capture/counter blocks |
| 5 | * |
| 6 | * vim: ts=4 sw=4 |
| 7 | * |
| 8 | * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com> |
| 9 | * SPDX-License-Identifier: CERN-OHL-P-2.0 |
| 10 | */ |
| 11 | |
| 12 | `define WITH_SB_MAC16 |
| 13 | |
| 14 | module capcnt #( |
| 15 | parameter integer W = 16, |
| 16 | )( |
| 17 | output wire [W-1:0] cnt_cur, |
| 18 | output wire [W-1:0] cnt_cap, |
| 19 | input wire inc, |
| 20 | input wire cap, |
| 21 | input wire clk, |
| 22 | input wire rst |
| 23 | ); |
| 24 | |
| 25 | `ifdef WITH_SB_MAC16 |
| 26 | generate |
| 27 | |
| 28 | if (W == 16) |
| 29 | capcnt16_sb_mac16 sub_I ( |
| 30 | .cnt_cur (cnt_cur), |
| 31 | .cnt_cap (cnt_cap), |
| 32 | .inc (inc), |
| 33 | .cap (cap), |
| 34 | .clk (clk), |
| 35 | .rst (rst) |
| 36 | ); |
| 37 | |
| 38 | else if (W == 32) |
| 39 | capcnt32_sb_mac16 sub_I ( |
| 40 | .cnt_cur (cnt_cur), |
| 41 | .cnt_cap (cnt_cap), |
| 42 | .inc (inc), |
| 43 | .cap (cap), |
| 44 | .clk (clk), |
| 45 | .rst (rst) |
| 46 | ); |
| 47 | |
| 48 | endgenerate |
| 49 | `else |
| 50 | |
| 51 | reg [W-1:0] cnt_cur_i; |
| 52 | reg [W-1:0] cnt_cap_i; |
| 53 | |
| 54 | always @(posedge clk) |
| 55 | if (rst) |
| 56 | cnt_cur_i <= 0; |
| 57 | else if (inc) |
| 58 | cnt_cur_i <= cnt_cur_i + 1; |
| 59 | |
| 60 | always @(posedge clk) |
| 61 | if (rst) |
| 62 | cnt_cap_i <= 0; |
| 63 | else if (cap) |
| 64 | cnt_cap_i <= cnt_cur_i; |
| 65 | |
| 66 | assign cnt_cur = cnt_cur_i; |
| 67 | assign cnt_cap = cnt_cap_i; |
| 68 | |
| 69 | `endif |
| 70 | |
| 71 | endmodule // capcnt |