Sylvain Munaut | c75f71e | 2020-10-03 20:01:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * picorv32_ice40_regs.v |
| 3 | * |
| 4 | * vim: ts=4 sw=4 |
| 5 | * |
| 6 | * Implementation of register file for the PicoRV32 on iCE40 |
| 7 | * |
| 8 | * Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com> |
| 9 | * SPDX-License-Identifier: CERN-OHL-P-2.0 |
| 10 | */ |
| 11 | |
| 12 | `default_nettype none |
| 13 | |
| 14 | module picorv32_ice40_regs ( |
| 15 | input wire clk, |
| 16 | input wire wen, |
| 17 | input wire [5:0] waddr, |
| 18 | input wire [5:0] raddr1, |
| 19 | input wire [5:0] raddr2, |
| 20 | input wire [31:0] wdata, |
| 21 | output wire [31:0] rdata1, |
| 22 | output wire [31:0] rdata2 |
| 23 | ); |
| 24 | |
| 25 | ice40_ebr #( |
| 26 | .READ_MODE(0), |
| 27 | .WRITE_MODE(0), |
| 28 | .MASK_WORKAROUND(0), |
| 29 | .NEG_WR_CLK(0), |
| 30 | .NEG_RD_CLK(1) |
| 31 | ) regs[3:0] ( |
| 32 | .wr_addr ({ 4{2'b00, waddr} }), |
| 33 | .wr_data ({ 2{wdata} }), |
| 34 | .wr_mask (64'h0000000000000000), |
| 35 | .wr_ena (wen), |
| 36 | .wr_clk (clk), |
| 37 | .rd_addr ({2'b00, raddr2, 2'b00, raddr2, 2'b00, raddr1, 2'b00, raddr1}), |
| 38 | .rd_data ({rdata2, rdata1}), |
| 39 | .rd_ena (1'b1), |
| 40 | .rd_clk (clk) |
| 41 | ); |
| 42 | |
| 43 | endmodule // picorv32_ice40_regs |