Harald Welte | da02f55 | 2012-01-14 18:18:31 +0100 | [diff] [blame] | 1 | #include <stdint.h> |
| 2 | |
| 3 | #include "idt82v2081.h" |
| 4 | #include "idt82v2081_regs.h" |
| 5 | |
Harald Welte | 605e3e4 | 2012-03-06 23:15:42 +0100 | [diff] [blame] | 6 | /*! \brief Set or clear some (masked) bits inside a register |
| 7 | * \param[in] e4k reference to the tuner |
| 8 | * \param[in] reg number of the register |
| 9 | * \param[in] mask bit-mask of the value |
| 10 | * \param[in] val data value to be written to register |
| 11 | * \returns 0 on success, negative in case of error |
| 12 | */ |
| 13 | static int idt82_reg_set_bit_mask(struct idt82 *idt, uint8_t reg, |
| 14 | uint8_t mask, uint8_t val) |
| 15 | { |
| 16 | uint8_t tmp = idt82_reg_read(idt, reg); |
| 17 | |
| 18 | if ((tmp & mask) == val) |
| 19 | return 0; |
| 20 | |
| 21 | return idt82_reg_write(idt, reg, (tmp & ~mask) | (val & mask)); |
| 22 | } |
| 23 | |
Harald Welte | da02f55 | 2012-01-14 18:18:31 +0100 | [diff] [blame] | 24 | int idt82_termination(struct idt82 *idt, enum idt82_term term) |
| 25 | { |
| 26 | idt82_reg_set_bit_mask(IDT_REG_TERM, term | (term << IDT_TERM_T_SHIFT), |
| 27 | IDT_TERM_T_MASK | IDT_TERM_R_MASK); |
| 28 | |
| 29 | switch (idt->mode) { |
| 30 | case IDT_MODE_E1: |
| 31 | if (term == IDT_TERM_INT_75) |
| 32 | puls = 0; |
| 33 | else |
| 34 | puls = 1; |
| 35 | scal = 0x21; |
| 36 | break; |
| 37 | case IDT_MODE_T1: |
| 38 | /* FIXME: different length! */ |
| 39 | puls = 2; |
| 40 | scal = 0x36; |
| 41 | break; |
| 42 | case IDT_MODE_J1: |
| 43 | puls = 7; |
| 44 | scal = 0x36; |
| 45 | break; |
| 46 | } |
| 47 | |
| 48 | idt82_reg_set_bit_mask(IDT_REG_TCF1, puls, IDT_TCF1_PULS_MASK); |
| 49 | idt82_reg_set_bit_mask(IDT_REG_TCF2, scal, IDT_TCF1_SCAL_MASK); |
| 50 | |
| 51 | idt->term = term; |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | int idt82_mode(struct idt82 *idt, enum idt82_mode mode) |
| 57 | { |
| 58 | switch (mode) { |
| 59 | case IDT_MODE_E1: |
| 60 | idt82_reg_set_bit_mask(idt, IDT_REG_GCF, IDT_GCF_T1E1_E1, |
| 61 | IDT_GCF_T1E1_MASK); |
| 62 | break; |
| 63 | case IDT_MODE_T1: |
| 64 | idt82_reg_set_bit_mask(idt, IDT_REG_GCF, IDT_GCF_T1E1_T1, |
| 65 | IDT_GCF_T1E1_MASK); |
| 66 | break; |
| 67 | } |
| 68 | idt->mode = mode; |
| 69 | } |
| 70 | |
| 71 | int idt82_get_errcount(struct idt82 *idt) |
| 72 | { |
| 73 | uint16_t ret; |
| 74 | int rc; |
| 75 | |
| 76 | rc = idt82_reg_read(idt, IDT_REG_CNT0) |
| 77 | if (rc < 0) |
| 78 | return ret; |
| 79 | |
| 80 | ret = rc; |
| 81 | |
| 82 | rc = idt82_reg_read(idt, IDT_REG_CNT1) |
| 83 | if (rc < 0) |
| 84 | return ret; |
| 85 | |
| 86 | ret |= (rc << 8); |
| 87 | |
| 88 | return ret; |
| 89 | |
| 90 | } |
| 91 | |
| 92 | /* return in dB, range is return value ... (value + 2) */ |
| 93 | int idt82_get_line_att(struct idt82 *idt) |
| 94 | { |
| 95 | int rc; |
| 96 | |
| 97 | rc = idt82_reg_read(idt, IDT_REG_STAT1); |
| 98 | if (rc < 0) |
| 99 | return rc; |
| 100 | |
| 101 | return (rc & IDT_STAT1_ATT_MASK)*2; |
| 102 | } |
| 103 | |
| 104 | int idt82_init(struct idt82 *idt) |
| 105 | { |
| 106 | idt82_reg_write(idt, IDT_REG_GCF, 0); |
| 107 | idt82_reg_write(idt, IDT_REG_JA, 0); |
| 108 | idt82_reg_write(idt, IDT_REG_TCF0, 0); |
| 109 | idt82_reg_write(idt, IDT_REG_TCF5, 0); |
| 110 | idt82_reg_write(idt, IDT_REG_RCF1, 0); /* short haul */ |
| 111 | |
| 112 | idt82_mode(idt, IDT_MODE_E1); |
| 113 | idt82_term(idt, IDT_TERM_INT_120); |
| 114 | |
| 115 | return 0; |
| 116 | } |
| 117 | |