gateware/firmware: Match rx/tx tick order in register with doc

The documentation always had the rRX tick in the LSB which
is consistent with having the RX units before TX.

They can be read as 16 bit value anyway so there isn't any
performance impact.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
diff --git a/firmware/ice40-riscv/e1-tracer/misc.c b/firmware/ice40-riscv/e1-tracer/misc.c
index 6b100bd..f3c68e3 100644
--- a/firmware/ice40-riscv/e1-tracer/misc.c
+++ b/firmware/ice40-riscv/e1-tracer/misc.c
@@ -16,8 +16,8 @@
 	uint32_t warmboot;
 	uint32_t _rsvd0[3];;
 	struct {
-		uint16_t tx;
 		uint16_t rx;
+		uint16_t tx;
 	} e1_tick[2];
 	uint32_t _rsvd1;
 	uint32_t time;
diff --git a/firmware/ice40-riscv/icE1usb/misc.c b/firmware/ice40-riscv/icE1usb/misc.c
index 9ceb8c6..6f40fd4 100644
--- a/firmware/ice40-riscv/icE1usb/misc.c
+++ b/firmware/ice40-riscv/icE1usb/misc.c
@@ -18,8 +18,8 @@
 	uint32_t e1_led;
 	uint32_t _rsvd;
 	struct {
-		uint16_t tx;
 		uint16_t rx;
+		uint16_t tx;
 	} e1_tick[2];
 	uint32_t gps;
 	uint32_t time;
diff --git a/gateware/e1-tracer/rtl/misc.v b/gateware/e1-tracer/rtl/misc.v
index 99ae0b8..c64ad8b 100644
--- a/gateware/e1-tracer/rtl/misc.v
+++ b/gateware/e1-tracer/rtl/misc.v
@@ -76,8 +76,8 @@
 			wb_rdata <= 32'h00000000;
 		else
 			case (wb_addr[3:0])
-				4'h4:    wb_rdata <= { cap_e1_rx[0], 16'h0000 };
-				4'h5:    wb_rdata <= { cap_e1_rx[1], 16'h0000 };
+				4'h4:    wb_rdata <= { 16'h000, cap_e1_rx[0] };
+				4'h5:    wb_rdata <= { 16'h000, cap_e1_rx[1] };
 				4'h7:    wb_rdata <= cnt_time;
 				default: wb_rdata <= 32'hxxxxxxxx;
 			endcase
diff --git a/gateware/icE1usb-proto/rtl/misc.v b/gateware/icE1usb-proto/rtl/misc.v
index e7a2854..63c315d 100644
--- a/gateware/icE1usb-proto/rtl/misc.v
+++ b/gateware/icE1usb-proto/rtl/misc.v
@@ -102,7 +102,7 @@
 			wb_rdata <= 32'h00000000;
 		else
 			case (wb_addr[3:0])
-				4'h4:    wb_rdata <= { cap_e1_rx, cap_e1_tx };
+				4'h4:    wb_rdata <= { cap_e1_tx, cap_e1_rx };
 				4'h7:    wb_rdata <= cnt_time;
 				4'h8:    wb_rdata <= { pdm_clk[0][12], 19'h00000, pdm_clk[0][11:0] };
 				4'h9:    wb_rdata <= { pdm_clk[1][12], 19'h00000, pdm_clk[1][11:0] };