gateware/icE1usb{,-proto}: Make PDM registers write-only
Really we never need to read them and it takes logic to implement
the read-mux for nothing ...
diff --git a/gateware/icE1usb-proto/doc/mem-map.md b/gateware/icE1usb-proto/doc/mem-map.md
index 87407a6..d8f9cba 100644
--- a/gateware/icE1usb-proto/doc/mem-map.md
+++ b/gateware/icE1usb-proto/doc/mem-map.md
@@ -188,7 +188,7 @@
32 bit counter incremented at the system clock rate ( 30.72 MHz )
-#### PDM (Read/Write, addr `0x08-0x0f`)
+#### PDM (Write Only, addr `0x08-0x0f`)
This exposes configurable voltages ( DACs ). Some channels are 12 bits, some are 8 bits.
diff --git a/gateware/icE1usb-proto/rtl/misc.v b/gateware/icE1usb-proto/rtl/misc.v
index 934ba05..8ff14d9 100644
--- a/gateware/icE1usb-proto/rtl/misc.v
+++ b/gateware/icE1usb-proto/rtl/misc.v
@@ -11,6 +11,8 @@
`default_nettype none
+// `define WITH_PDM_READBACK
+
module misc (
// PDM outputs
output wire e1_vref_ct_pdm,
@@ -102,11 +104,13 @@
case (wb_addr[3:0])
4'h4: wb_rdata <= { cap_e1_tx, cap_e1_rx };
4'h7: wb_rdata <= cnt_time;
+`ifdef WITH_PDM_READBACK
4'h8: wb_rdata <= { pdm_clk[0][12], 19'h00000, pdm_clk[0][11:0] };
4'h9: wb_rdata <= { pdm_clk[1][12], 19'h00000, pdm_clk[1][11:0] };
4'ha: wb_rdata <= { pdm_e1[0][8], 23'h000000, pdm_e1[0][ 7:0] };
4'hb: wb_rdata <= { pdm_e1[1][8], 23'h000000, pdm_e1[1][ 7:0] };
4'hc: wb_rdata <= { pdm_e1[2][8], 23'h000000, pdm_e1[2][ 7:0] };
+`endif
default: wb_rdata <= 32'hxxxxxxxx;
endcase
diff --git a/gateware/icE1usb/doc/mem-map.md b/gateware/icE1usb/doc/mem-map.md
index 4c6cdaf..b237000 100644
--- a/gateware/icE1usb/doc/mem-map.md
+++ b/gateware/icE1usb/doc/mem-map.md
@@ -251,7 +251,7 @@
32 bit counter incremented at the system clock rate ( 30.72 MHz )
-#### PDM (Read/Write, addr `0x08-0x0f`)
+#### PDM (Write Only, addr `0x08-0x0f`)
This exposes configurable voltages ( DACs ). Some channels are 12 bits, some are 8 bits.
diff --git a/gateware/icE1usb/rtl/misc.v b/gateware/icE1usb/rtl/misc.v
index 634ed5d..1efa442 100644
--- a/gateware/icE1usb/rtl/misc.v
+++ b/gateware/icE1usb/rtl/misc.v
@@ -11,6 +11,8 @@
`default_nettype none
+// `define WITH_PDM_READBACK
+
module misc (
// PDM outputs
output wire [1:0] e1_rx_bias,
@@ -136,10 +138,12 @@
4'h5: wb_rdata <= { cap_e1_tx[1], cap_e1_rx[1] };
4'h6: wb_rdata <= cap_gps;
4'h7: wb_rdata <= cnt_time;
+`ifdef WITH_PDM_READBACK
4'h8: wb_rdata <= { pdm_clk[0][12], 19'h00000, pdm_clk[0][11:0] };
4'h9: wb_rdata <= { pdm_clk[1][12], 19'h00000, pdm_clk[1][11:0] };
4'ha: wb_rdata <= { pdm_e1[0][8], 23'h000000, pdm_e1[0][ 7:0] };
4'hb: wb_rdata <= { pdm_e1[1][8], 23'h000000, pdm_e1[1][ 7:0] };
+`endif
default: wb_rdata <= 32'hxxxxxxxx;
endcase