| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief HAL cache functionality implementation. |
| 5 | * |
| 6 | * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | /* |
| 34 | * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a> |
| 35 | */ |
| 36 | |
| 37 | #ifndef HAL_CACHE_H_ |
| 38 | #define HAL_CACHE_H_ |
| 39 | |
| 40 | #include <hpl_cmcc.h> |
| 41 | |
| 42 | #ifdef __cplusplus |
| 43 | extern "C" { |
| 44 | #endif |
| 45 | |
| 46 | /** |
| 47 | * \brief Enable cache module |
| 48 | * |
| 49 | * \param[in] pointer pointing to the starting address of cache module |
| 50 | * |
| 51 | * \return status of operation |
| 52 | */ |
| 53 | int32_t cache_enable(const void *hw); |
| 54 | |
| 55 | /** |
| 56 | * \brief Disable cache module |
| 57 | * |
| 58 | * \param[in] pointer pointing to the starting address of cache module |
| 59 | * |
| 60 | * \return status of operation |
| 61 | */ |
| 62 | int32_t cache_disable(const void *hw); |
| 63 | |
| 64 | /** |
| 65 | * \brief Initialize cache module |
| 66 | * |
| 67 | * This function initialize cache module configuration. |
| 68 | * |
| 69 | * \return status of operation |
| 70 | */ |
| 71 | int32_t cache_init(void); |
| 72 | |
| 73 | /** |
| 74 | * \brief Configure cache module |
| 75 | * |
| 76 | * \param[in] pointer pointing to the starting address of cache module |
| 77 | * \param[in] cache configuration structure pointer |
| 78 | * |
| 79 | * \return status of operation |
| 80 | */ |
| 81 | int32_t cache_configure(const void *hw, struct _cache_cfg *cache); |
| 82 | |
| 83 | /** |
| 84 | * \brief Invalidate entire cache entries |
| 85 | * |
| 86 | * \param[in] pointer pointing to the starting address of cache module |
| 87 | * |
| 88 | * \return status of operation |
| 89 | */ |
| 90 | int32_t cache_invalidate_all(const void *hw); |
| 91 | |
| 92 | #ifdef __cplusplus |
| 93 | } |
| 94 | #endif |
| 95 | |
| 96 | #endif /* HAL_CACHE_H_ */ |