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gerrit.osmocom.org / osmo-ccid-firmware / refs/heads/hoernchen/kevin / . / sysmoOCTSIM / include / same54n19a.h
blob: 6812e730fa8e3eca04b8874b0f5e70766bba16cb [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief Header file for SAME54N19A
5 *
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]6 * Copyright (c) 2019 Microchip Technology Inc.
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54N19A_
31#define _SAME54N19A_
32
33/**
34 * \ingroup SAME54_definitions
35 * \addtogroup SAME54N19A_definitions SAME54N19A definitions
36 * This file defines all structures and symbols for SAME54N19A:
37 * - registers and bitfields
38 * - peripheral base address
39 * - peripheral ID
40 * - PIO definitions
41*/
42/*@{*/
43
44#ifdef __cplusplus
45 extern "C" {
46#endif
47
48#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49#include <stdint.h>
50#ifndef __cplusplus
51typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
52typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
53typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
54#else
55typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
56typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
57typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
58#endif
59typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
60typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
61typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
62typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
63typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
64typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
65#endif
66
67#if !defined(SKIP_INTEGER_LITERALS)
68#if defined(_U_) || defined(_L_) || defined(_UL_)
69 #error "Integer Literals macros already defined elsewhere"
70#endif
71
72#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
73/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
74#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
75#define _L_(x) x ## L /**< C code: Long integer literal constant value */
76#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
77#else /* Assembler */
78#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
79#define _L_(x) x /**< Assembler: Long integer literal constant value */
80#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
81#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
82#endif /* SKIP_INTEGER_LITERALS */
83
84/* ************************************************************************** */
85/** CMSIS DEFINITIONS FOR SAME54N19A */
86/* ************************************************************************** */
87/** \defgroup SAME54N19A_cmsis CMSIS Definitions */
88/*@{*/
89
90/** Interrupt Number Definition */
91typedef enum IRQn
92{
93 /****** Cortex-M4 Processor Exceptions Numbers *******************/
94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
95 HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
96 MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */
97 BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */
98 UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */
99 SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
100 DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */
101 PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
102 SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
103 /****** SAME54N19A-specific Interrupt Numbers *********************/
104 PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */
105 MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]106 OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL) IRQ 0 */
107 OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL) IRQ 1 */
108 OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL) IRQ 2 */
109 OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL) IRQ 3 */
110 OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL) IRQ 4 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]111 OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]112 SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC) IRQ 0 */
113 SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC) IRQ 1 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]114 WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */
115 RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]116 EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC) IRQ 0 */
117 EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC) IRQ 1 */
118 EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC) IRQ 2 */
119 EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC) IRQ 3 */
120 EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC) IRQ 4 */
121 EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC) IRQ 5 */
122 EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC) IRQ 6 */
123 EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC) IRQ 7 */
124 EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC) IRQ 8 */
125 EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC) IRQ 9 */
126 EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC) IRQ 10 */
127 EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC) IRQ 11 */
128 EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC) IRQ 12 */
129 EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC) IRQ 13 */
130 EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC) IRQ 14 */
131 EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC) IRQ 15 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]132 FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]133 NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
134 NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
135 DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 0 */
136 DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 1 */
137 DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 2 */
138 DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 3 */
139 DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 4 */
140 EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS) IRQ 0 */
141 EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS) IRQ 1 */
142 EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS) IRQ 2 */
143 EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS) IRQ 3 */
144 EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS) IRQ 4 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]145 PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */
146 RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]147 SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
148 SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
149 SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
150 SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
151 SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
152 SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
153 SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
154 SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
155 SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
156 SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
157 SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
158 SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
159 SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
160 SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
161 SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
162 SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
163 SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
164 SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
165 SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
166 SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
167 SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
168 SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
169 SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
170 SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
171 SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
172 SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
173 SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
174 SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
175 SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
176 SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
177 SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
178 SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]179 CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */
180 CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]181 USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB) IRQ 0 */
182 USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB) IRQ 1 */
183 USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB) IRQ 2 */
184 USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB) IRQ 3 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]185 GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]186 TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 0 */
187 TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 1 */
188 TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 2 */
189 TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 3 */
190 TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 4 */
191 TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 5 */
192 TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 6 */
193 TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 0 */
194 TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 1 */
195 TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 2 */
196 TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 3 */
197 TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 4 */
198 TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 0 */
199 TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 1 */
200 TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 2 */
201 TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 3 */
202 TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 0 */
203 TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 1 */
204 TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 2 */
205 TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 0 */
206 TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 1 */
207 TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 2 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]208 TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */
209 TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */
210 TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */
211 TC3_IRQn = 110, /**< 110 SAME54N19A Basic Timer Counter 3 (TC3) */
212 TC4_IRQn = 111, /**< 111 SAME54N19A Basic Timer Counter 4 (TC4) */
213 TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */
214 TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */
215 TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]216 PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC) IRQ 0 */
217 PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC) IRQ 1 */
218 PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC) IRQ 2 */
219 ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 0 */
220 ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 1 */
221 ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 0 */
222 ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 1 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]223 AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */
Harald Welte9bb8bfe2019-05-17 16:10:00 +0200[diff] [blame]224 DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 0 */
225 DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 1 */
226 DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 2 */
227 DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 3 */
228 DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 4 */
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]229 I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */
230 PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */
231 AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */
232 TRNG_IRQn = 131, /**< 131 SAME54N19A True Random Generator (TRNG) */
233 ICM_IRQn = 132, /**< 132 SAME54N19A Integrity Check Monitor (ICM) */
234 PUKCC_IRQn = 133, /**< 133 SAME54N19A PUblic-Key Cryptography Controller (PUKCC) */
235 QSPI_IRQn = 134, /**< 134 SAME54N19A Quad SPI interface (QSPI) */
236 SDHC0_IRQn = 135, /**< 135 SAME54N19A SD/MMC Host Controller 0 (SDHC0) */
237 SDHC1_IRQn = 136, /**< 136 SAME54N19A SD/MMC Host Controller 1 (SDHC1) */
238
239 PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */
240} IRQn_Type;
241
242typedef struct _DeviceVectors
243{
244 /* Stack pointer */
245 void* pvStack;
246
247 /* Cortex-M handlers */
248 void* pfnReset_Handler;
249 void* pfnNonMaskableInt_Handler;
250 void* pfnHardFault_Handler;
251 void* pfnMemManagement_Handler;
252 void* pfnBusFault_Handler;
253 void* pfnUsageFault_Handler;
254 void* pvReservedM9;
255 void* pvReservedM8;
256 void* pvReservedM7;
257 void* pvReservedM6;
258 void* pfnSVCall_Handler;
259 void* pfnDebugMonitor_Handler;
260 void* pvReservedM3;
261 void* pfnPendSV_Handler;
262 void* pfnSysTick_Handler;
263
264 /* Peripheral handlers */
265 void* pfnPM_Handler; /* 0 Power Manager */
266 void* pfnMCLK_Handler; /* 1 Main Clock */
267 void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
268 void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
269 void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
270 void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
271 void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
272 void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
273 void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
274 void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
275 void* pfnWDT_Handler; /* 10 Watchdog Timer */
276 void* pfnRTC_Handler; /* 11 Real-Time Counter */
277 void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
278 void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
279 void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
280 void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
281 void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
282 void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
283 void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
284 void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
285 void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
286 void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
287 void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
288 void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
289 void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
290 void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
291 void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
292 void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
293 void* pfnFREQM_Handler; /* 28 Frequency Meter */
294 void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
295 void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
296 void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
297 void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
298 void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
299 void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
300 void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
301 void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
302 void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
303 void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
304 void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
305 void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
306 void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
307 void* pvReserved42;
308 void* pvReserved43;
309 void* pvReserved44;
310 void* pfnRAMECC_Handler; /* 45 RAM ECC */
311 void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
312 void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
313 void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
314 void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
315 void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
316 void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
317 void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
318 void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
319 void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
320 void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
321 void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
322 void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
323 void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
324 void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
325 void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
326 void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
327 void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
328 void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
329 void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
330 void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
331 void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
332 void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
333 void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
334 void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
335 void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
336 void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
337 void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
338 void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
339 void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
340 void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
341 void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
342 void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
343 void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
344 void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
345 void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
346 void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
347 void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
348 void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
349 void* pfnGMAC_Handler; /* 84 Ethernet MAC */
350 void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
351 void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
352 void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
353 void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
354 void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
355 void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
356 void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
357 void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
358 void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
359 void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
360 void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
361 void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
362 void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
363 void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
364 void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
365 void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
366 void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
367 void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
368 void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
369 void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
370 void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
371 void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
372 void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
373 void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
374 void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
375 void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
376 void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
377 void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
378 void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
379 void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
380 void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
381 void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
382 void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
383 void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
384 void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
385 void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
386 void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
387 void* pfnAC_Handler; /* 122 Analog Comparators */
388 void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
389 void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
390 void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
391 void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
392 void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
393 void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
394 void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
395 void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
396 void* pfnTRNG_Handler; /* 131 True Random Generator */
397 void* pfnICM_Handler; /* 132 Integrity Check Monitor */
398 void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
399 void* pfnQSPI_Handler; /* 134 Quad SPI interface */
400 void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
401 void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
402} DeviceVectors;
403
404/* Cortex-M4 processor handlers */
405void Reset_Handler ( void );
406void NonMaskableInt_Handler ( void );
407void HardFault_Handler ( void );
408void MemManagement_Handler ( void );
409void BusFault_Handler ( void );
410void UsageFault_Handler ( void );
411void SVCall_Handler ( void );
412void DebugMonitor_Handler ( void );
413void PendSV_Handler ( void );
414void SysTick_Handler ( void );
415
416/* Peripherals handlers */
417void PM_Handler ( void );
418void MCLK_Handler ( void );
419void OSCCTRL_0_Handler ( void );
420void OSCCTRL_1_Handler ( void );
421void OSCCTRL_2_Handler ( void );
422void OSCCTRL_3_Handler ( void );
423void OSCCTRL_4_Handler ( void );
424void OSC32KCTRL_Handler ( void );
425void SUPC_0_Handler ( void );
426void SUPC_1_Handler ( void );
427void WDT_Handler ( void );
428void RTC_Handler ( void );
429void EIC_0_Handler ( void );
430void EIC_1_Handler ( void );
431void EIC_2_Handler ( void );
432void EIC_3_Handler ( void );
433void EIC_4_Handler ( void );
434void EIC_5_Handler ( void );
435void EIC_6_Handler ( void );
436void EIC_7_Handler ( void );
437void EIC_8_Handler ( void );
438void EIC_9_Handler ( void );
439void EIC_10_Handler ( void );
440void EIC_11_Handler ( void );
441void EIC_12_Handler ( void );
442void EIC_13_Handler ( void );
443void EIC_14_Handler ( void );
444void EIC_15_Handler ( void );
445void FREQM_Handler ( void );
446void NVMCTRL_0_Handler ( void );
447void NVMCTRL_1_Handler ( void );
448void DMAC_0_Handler ( void );
449void DMAC_1_Handler ( void );
450void DMAC_2_Handler ( void );
451void DMAC_3_Handler ( void );
452void DMAC_4_Handler ( void );
453void EVSYS_0_Handler ( void );
454void EVSYS_1_Handler ( void );
455void EVSYS_2_Handler ( void );
456void EVSYS_3_Handler ( void );
457void EVSYS_4_Handler ( void );
458void PAC_Handler ( void );
459void RAMECC_Handler ( void );
460void SERCOM0_0_Handler ( void );
461void SERCOM0_1_Handler ( void );
462void SERCOM0_2_Handler ( void );
463void SERCOM0_3_Handler ( void );
464void SERCOM1_0_Handler ( void );
465void SERCOM1_1_Handler ( void );
466void SERCOM1_2_Handler ( void );
467void SERCOM1_3_Handler ( void );
468void SERCOM2_0_Handler ( void );
469void SERCOM2_1_Handler ( void );
470void SERCOM2_2_Handler ( void );
471void SERCOM2_3_Handler ( void );
472void SERCOM3_0_Handler ( void );
473void SERCOM3_1_Handler ( void );
474void SERCOM3_2_Handler ( void );
475void SERCOM3_3_Handler ( void );
476void SERCOM4_0_Handler ( void );
477void SERCOM4_1_Handler ( void );
478void SERCOM4_2_Handler ( void );
479void SERCOM4_3_Handler ( void );
480void SERCOM5_0_Handler ( void );
481void SERCOM5_1_Handler ( void );
482void SERCOM5_2_Handler ( void );
483void SERCOM5_3_Handler ( void );
484void SERCOM6_0_Handler ( void );
485void SERCOM6_1_Handler ( void );
486void SERCOM6_2_Handler ( void );
487void SERCOM6_3_Handler ( void );
488void SERCOM7_0_Handler ( void );
489void SERCOM7_1_Handler ( void );
490void SERCOM7_2_Handler ( void );
491void SERCOM7_3_Handler ( void );
492void CAN0_Handler ( void );
493void CAN1_Handler ( void );
494void USB_0_Handler ( void );
495void USB_1_Handler ( void );
496void USB_2_Handler ( void );
497void USB_3_Handler ( void );
498void GMAC_Handler ( void );
499void TCC0_0_Handler ( void );
500void TCC0_1_Handler ( void );
501void TCC0_2_Handler ( void );
502void TCC0_3_Handler ( void );
503void TCC0_4_Handler ( void );
504void TCC0_5_Handler ( void );
505void TCC0_6_Handler ( void );
506void TCC1_0_Handler ( void );
507void TCC1_1_Handler ( void );
508void TCC1_2_Handler ( void );
509void TCC1_3_Handler ( void );
510void TCC1_4_Handler ( void );
511void TCC2_0_Handler ( void );
512void TCC2_1_Handler ( void );
513void TCC2_2_Handler ( void );
514void TCC2_3_Handler ( void );
515void TCC3_0_Handler ( void );
516void TCC3_1_Handler ( void );
517void TCC3_2_Handler ( void );
518void TCC4_0_Handler ( void );
519void TCC4_1_Handler ( void );
520void TCC4_2_Handler ( void );
521void TC0_Handler ( void );
522void TC1_Handler ( void );
523void TC2_Handler ( void );
524void TC3_Handler ( void );
525void TC4_Handler ( void );
526void TC5_Handler ( void );
527void TC6_Handler ( void );
528void TC7_Handler ( void );
529void PDEC_0_Handler ( void );
530void PDEC_1_Handler ( void );
531void PDEC_2_Handler ( void );
532void ADC0_0_Handler ( void );
533void ADC0_1_Handler ( void );
534void ADC1_0_Handler ( void );
535void ADC1_1_Handler ( void );
536void AC_Handler ( void );
537void DAC_0_Handler ( void );
538void DAC_1_Handler ( void );
539void DAC_2_Handler ( void );
540void DAC_3_Handler ( void );
541void DAC_4_Handler ( void );
542void I2S_Handler ( void );
543void PCC_Handler ( void );
544void AES_Handler ( void );
545void TRNG_Handler ( void );
546void ICM_Handler ( void );
547void PUKCC_Handler ( void );
548void QSPI_Handler ( void );
549void SDHC0_Handler ( void );
550void SDHC1_Handler ( void );
551
552/*
553 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
554 */
555
556#define __CM4_REV 1 /*!< Core revision r0p1 */
557#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */
558#define __FPU_PRESENT 1 /*!< FPU present or not */
559#define __MPU_PRESENT 1 /*!< MPU present or not */
560#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */
561#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */
562#define __VTOR_PRESENT 1 /*!< VTOR present or not */
563#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
564
565/**
566 * \brief CMSIS includes
567 */
568
569#include <core_cm4.h>
570#if !defined DONT_USE_CMSIS_INIT
571#include "system_same54.h"
572#endif /* DONT_USE_CMSIS_INIT */
573
574/*@}*/
575
576/* ************************************************************************** */
577/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */
578/* ************************************************************************** */
579/** \defgroup SAME54N19A_api Peripheral Software API */
580/*@{*/
581
582#include "component/ac.h"
583#include "component/adc.h"
584#include "component/aes.h"
585#include "component/can.h"
586#include "component/ccl.h"
587#include "component/cmcc.h"
588#include "component/dac.h"
589#include "component/dmac.h"
590#include "component/dsu.h"
591#include "component/eic.h"
592#include "component/evsys.h"
593#include "component/freqm.h"
594#include "component/gclk.h"
595#include "component/gmac.h"
596#include "component/hmatrixb.h"
597#include "component/icm.h"
598#include "component/i2s.h"
599#include "component/mclk.h"
600#include "component/nvmctrl.h"
601#include "component/oscctrl.h"
602#include "component/osc32kctrl.h"
603#include "component/pac.h"
604#include "component/pcc.h"
605#include "component/pdec.h"
606#include "component/pm.h"
607#include "component/port.h"
608#include "component/qspi.h"
609#include "component/ramecc.h"
610#include "component/rstc.h"
611#include "component/rtc.h"
612#include "component/sdhc.h"
613#include "component/sercom.h"
614#include "component/supc.h"
615#include "component/tc.h"
616#include "component/tcc.h"
617#include "component/trng.h"
618#include "component/usb.h"
619#include "component/wdt.h"
620/*@}*/
621
622/* ************************************************************************** */
623/** REGISTERS ACCESS DEFINITIONS FOR SAME54N19A */
624/* ************************************************************************** */
625/** \defgroup SAME54N19A_reg Registers Access Definitions */
626/*@{*/
627
628#include "instance/ac.h"
629#include "instance/adc0.h"
630#include "instance/adc1.h"
631#include "instance/aes.h"
632#include "instance/can0.h"
633#include "instance/can1.h"
634#include "instance/ccl.h"
635#include "instance/cmcc.h"
636#include "instance/dac.h"
637#include "instance/dmac.h"
638#include "instance/dsu.h"
639#include "instance/eic.h"
640#include "instance/evsys.h"
641#include "instance/freqm.h"
642#include "instance/gclk.h"
643#include "instance/gmac.h"
644#include "instance/hmatrix.h"
645#include "instance/icm.h"
646#include "instance/i2s.h"
647#include "instance/mclk.h"
648#include "instance/nvmctrl.h"
649#include "instance/oscctrl.h"
650#include "instance/osc32kctrl.h"
651#include "instance/pac.h"
652#include "instance/pcc.h"
653#include "instance/pdec.h"
654#include "instance/pm.h"
655#include "instance/port.h"
656#include "instance/pukcc.h"
657#include "instance/qspi.h"
658#include "instance/ramecc.h"
659#include "instance/rstc.h"
660#include "instance/rtc.h"
661#include "instance/sdhc0.h"
662#include "instance/sdhc1.h"
663#include "instance/sercom0.h"
664#include "instance/sercom1.h"
665#include "instance/sercom2.h"
666#include "instance/sercom3.h"
667#include "instance/sercom4.h"
668#include "instance/sercom5.h"
669#include "instance/sercom6.h"
670#include "instance/sercom7.h"
671#include "instance/supc.h"
672#include "instance/tc0.h"
673#include "instance/tc1.h"
674#include "instance/tc2.h"
675#include "instance/tc3.h"
676#include "instance/tc4.h"
677#include "instance/tc5.h"
678#include "instance/tc6.h"
679#include "instance/tc7.h"
680#include "instance/tcc0.h"
681#include "instance/tcc1.h"
682#include "instance/tcc2.h"
683#include "instance/tcc3.h"
684#include "instance/tcc4.h"
685#include "instance/trng.h"
686#include "instance/usb.h"
687#include "instance/wdt.h"
688/*@}*/
689
690/* ************************************************************************** */
691/** PERIPHERAL ID DEFINITIONS FOR SAME54N19A */
692/* ************************************************************************** */
693/** \defgroup SAME54N19A_id Peripheral Ids Definitions */
694/*@{*/
695
696// Peripheral instances on HPB0 bridge
697#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
698#define ID_PM 1 /**< \brief Power Manager (PM) */
699#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
700#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
701#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
702#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
703#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
704#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
705#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
706#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
707#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
708#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
709#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
710#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
711#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */
712#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */
713
714// Peripheral instances on HPB1 bridge
715#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */
716#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
717#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
718#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */
719#define ID_PORT 36 /**< \brief Port Module (PORT) */
720#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */
721#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */
722#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */
723#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
724#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
725#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */
726#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */
727#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */
728#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */
729#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */
730
731// Peripheral instances on HPB2 bridge
732#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */
733#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */
734#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */
735#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */
736#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */
737#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */
738#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */
739#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */
740#define ID_AC 72 /**< \brief Analog Comparators (AC) */
741#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */
742#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */
743#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */
744#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
745#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */
746#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */
747
748// Peripheral instances on HPB3 bridge
749#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
750#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
751#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
752#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
753#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */
754#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */
755#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */
756#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */
757#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */
758#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */
759#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */
760#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */
761
762// Peripheral instances on AHB (as if on bridge 4)
763#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */
764#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */
765
766#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
767/*@}*/
768
769/* ************************************************************************** */
770/** BASE ADDRESS DEFINITIONS FOR SAME54N19A */
771/* ************************************************************************** */
772/** \defgroup SAME54N19A_base Peripheral Base Address Definitions */
773/*@{*/
774
775#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
776#define AC (0x42002000) /**< \brief (AC) APB Base Address */
777#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */
778#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */
779#define AES (0x42002400) /**< \brief (AES) APB Base Address */
780#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */
781#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */
782#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */
783#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */
784#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */
785#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */
786#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */
787#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
788#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
789#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */
790#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
791#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
792#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */
793#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
794#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */
795#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */
796#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
797#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
798#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
799#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
800#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
801#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
802#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
803#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
804#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */
805#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */
806#define PM (0x40000400) /**< \brief (PM) APB Base Address */
807#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */
808#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */
809#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */
810#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */
811#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */
812#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */
813#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
814#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
815#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */
816#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */
817#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */
818#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */
819#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */
820#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */
821#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */
822#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */
823#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */
824#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
825#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
826#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */
827#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */
828#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */
829#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */
830#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */
831#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */
832#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */
833#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */
834#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */
835#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */
836#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */
837#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */
838#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */
839#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */
840#define USB (0x41000000) /**< \brief (USB) APB Base Address */
841#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
842#else
843#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */
844#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
845#define AC_INSTS { AC } /**< \brief (AC) Instances List */
846
847#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
848#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
849#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
850#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
851
852#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */
853#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */
854#define AES_INSTS { AES } /**< \brief (AES) Instances List */
855
856#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */
857#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */
858#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
859#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
860
861#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */
862#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
863#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
864
865#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
866#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
867#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */
868#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */
869
870#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */
871#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
872#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
873
874#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
875#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
876#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
877
878#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
879#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
880#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
881
882#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
883#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
884#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
885
886#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
887#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
888#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
889
890#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
891#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
892#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
893
894#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
895#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
896#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
897
898#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
899#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */
900#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */
901
902#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
903#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
904#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */
905
906#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
907#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */
908#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */
909
910#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */
911#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
912#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
913
914#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
915#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
916#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
917
918#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
919#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
920#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
921#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
922#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
923#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
924
925#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
926#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
927#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
928
929#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
930#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
931#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
932
933#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
934#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
935#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
936
937#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
938#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */
939#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */
940
941#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
942#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */
943#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */
944
945#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
946#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
947#define PM_INSTS { PM } /**< \brief (PM) Instances List */
948
949#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */
950#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
951#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
952
953#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
954#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
955#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */
956#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */
957
958#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
959#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
960#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */
961#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */
962
963#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
964#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */
965#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */
966
967#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
968#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
969#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
970
971#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
972#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
973#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
974
975#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
976#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
977#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */
978#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */
979
980#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
981#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
982#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
983#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
984#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
985#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
986#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
987#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
988#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */
989#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
990
991#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
992#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
993#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
994
995#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */
996#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
997#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
998#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
999#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */
1000#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */
1001#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */
1002#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */
1003#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */
1004#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
1005
1006#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
1007#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
1008#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
1009#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
1010#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
1011#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */
1012#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
1013
1014#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
1015#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */
1016#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */
1017
1018#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */
1019#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
1020#define USB_INSTS { USB } /**< \brief (USB) Instances List */
1021
1022#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
1023#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
1024#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
1025
1026#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1027/*@}*/
1028
1029/* ************************************************************************** */
1030/** PORT DEFINITIONS FOR SAME54N19A */
1031/* ************************************************************************** */
1032/** \defgroup SAME54N19A_port PORT Definitions */
1033/*@{*/
1034
1035#include "pio/same54n19a.h"
1036/*@}*/
1037
1038/* ************************************************************************** */
1039/** MEMORY MAPPING DEFINITIONS FOR SAME54N19A */
1040/* ************************************************************************** */
1041
1042#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */
1043#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */
1044#define FLASH_PAGE_SIZE 512
1045#define FLASH_NB_OF_PAGES 1024
1046#define FLASH_USER_PAGE_SIZE 512
1047#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
1048#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
1049
1050#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
1051#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */
1052#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */
1053#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */
1054#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */
1055#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
1056#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */
1057#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
1058#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */
1059#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */
1060#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */
1061#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */
1062#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
1063#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
1064#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
1065#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */
1066#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */
1067#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */
1068#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
1069
1070#define DSU_DID_RESETVALUE _UL_(0x61840303)
1071#define ADC0_TOUCH_LINES_NUM 32
1072#define PORT_GROUPS 3
1073
1074/* ************************************************************************** */
1075/** ELECTRICAL DEFINITIONS FOR SAME54N19A */
1076/* ************************************************************************** */
1077
1078
1079#ifdef __cplusplus
1080}
1081#endif
1082
1083/*@}*/
1084
1085#endif /* SAME54N19A_H */