| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for TCC1
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_TCC1_INSTANCE_
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| 31 | #define _SAME54_TCC1_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for TCC1 peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_TCC1_CTRLA (0x41018000) /**< \brief (TCC1) Control A */
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| 36 | #define REG_TCC1_CTRLBCLR (0x41018004) /**< \brief (TCC1) Control B Clear */
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| 37 | #define REG_TCC1_CTRLBSET (0x41018005) /**< \brief (TCC1) Control B Set */
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| 38 | #define REG_TCC1_SYNCBUSY (0x41018008) /**< \brief (TCC1) Synchronization Busy */
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| 39 | #define REG_TCC1_FCTRLA (0x4101800C) /**< \brief (TCC1) Recoverable Fault A Configuration */
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| 40 | #define REG_TCC1_FCTRLB (0x41018010) /**< \brief (TCC1) Recoverable Fault B Configuration */
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| 41 | #define REG_TCC1_WEXCTRL (0x41018014) /**< \brief (TCC1) Waveform Extension Configuration */
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| 42 | #define REG_TCC1_DRVCTRL (0x41018018) /**< \brief (TCC1) Driver Control */
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| 43 | #define REG_TCC1_DBGCTRL (0x4101801E) /**< \brief (TCC1) Debug Control */
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| 44 | #define REG_TCC1_EVCTRL (0x41018020) /**< \brief (TCC1) Event Control */
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| 45 | #define REG_TCC1_INTENCLR (0x41018024) /**< \brief (TCC1) Interrupt Enable Clear */
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| 46 | #define REG_TCC1_INTENSET (0x41018028) /**< \brief (TCC1) Interrupt Enable Set */
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| 47 | #define REG_TCC1_INTFLAG (0x4101802C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
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| 48 | #define REG_TCC1_STATUS (0x41018030) /**< \brief (TCC1) Status */
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| 49 | #define REG_TCC1_COUNT (0x41018034) /**< \brief (TCC1) Count */
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| 50 | #define REG_TCC1_PATT (0x41018038) /**< \brief (TCC1) Pattern */
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| 51 | #define REG_TCC1_WAVE (0x4101803C) /**< \brief (TCC1) Waveform Control */
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| 52 | #define REG_TCC1_PER (0x41018040) /**< \brief (TCC1) Period */
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| 53 | #define REG_TCC1_CC0 (0x41018044) /**< \brief (TCC1) Compare and Capture 0 */
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| 54 | #define REG_TCC1_CC1 (0x41018048) /**< \brief (TCC1) Compare and Capture 1 */
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| 55 | #define REG_TCC1_CC2 (0x4101804C) /**< \brief (TCC1) Compare and Capture 2 */
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| 56 | #define REG_TCC1_CC3 (0x41018050) /**< \brief (TCC1) Compare and Capture 3 */
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| 57 | #define REG_TCC1_PATTBUF (0x41018064) /**< \brief (TCC1) Pattern Buffer */
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| 58 | #define REG_TCC1_PERBUF (0x4101806C) /**< \brief (TCC1) Period Buffer */
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| 59 | #define REG_TCC1_CCBUF0 (0x41018070) /**< \brief (TCC1) Compare and Capture Buffer 0 */
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| 60 | #define REG_TCC1_CCBUF1 (0x41018074) /**< \brief (TCC1) Compare and Capture Buffer 1 */
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| 61 | #define REG_TCC1_CCBUF2 (0x41018078) /**< \brief (TCC1) Compare and Capture Buffer 2 */
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| 62 | #define REG_TCC1_CCBUF3 (0x4101807C) /**< \brief (TCC1) Compare and Capture Buffer 3 */
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| 63 | #else
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| 64 | #define REG_TCC1_CTRLA (*(RwReg *)0x41018000UL) /**< \brief (TCC1) Control A */
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| 65 | #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL) /**< \brief (TCC1) Control B Clear */
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| 66 | #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL) /**< \brief (TCC1) Control B Set */
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| 67 | #define REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL) /**< \brief (TCC1) Synchronization Busy */
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| 68 | #define REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
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| 69 | #define REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
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| 70 | #define REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL) /**< \brief (TCC1) Waveform Extension Configuration */
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| 71 | #define REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL) /**< \brief (TCC1) Driver Control */
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| 72 | #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL) /**< \brief (TCC1) Debug Control */
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| 73 | #define REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL) /**< \brief (TCC1) Event Control */
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| 74 | #define REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL) /**< \brief (TCC1) Interrupt Enable Clear */
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| 75 | #define REG_TCC1_INTENSET (*(RwReg *)0x41018028UL) /**< \brief (TCC1) Interrupt Enable Set */
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| 76 | #define REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
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| 77 | #define REG_TCC1_STATUS (*(RwReg *)0x41018030UL) /**< \brief (TCC1) Status */
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| 78 | #define REG_TCC1_COUNT (*(RwReg *)0x41018034UL) /**< \brief (TCC1) Count */
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| 79 | #define REG_TCC1_PATT (*(RwReg16*)0x41018038UL) /**< \brief (TCC1) Pattern */
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| 80 | #define REG_TCC1_WAVE (*(RwReg *)0x4101803CUL) /**< \brief (TCC1) Waveform Control */
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| 81 | #define REG_TCC1_PER (*(RwReg *)0x41018040UL) /**< \brief (TCC1) Period */
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| 82 | #define REG_TCC1_CC0 (*(RwReg *)0x41018044UL) /**< \brief (TCC1) Compare and Capture 0 */
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| 83 | #define REG_TCC1_CC1 (*(RwReg *)0x41018048UL) /**< \brief (TCC1) Compare and Capture 1 */
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| 84 | #define REG_TCC1_CC2 (*(RwReg *)0x4101804CUL) /**< \brief (TCC1) Compare and Capture 2 */
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| 85 | #define REG_TCC1_CC3 (*(RwReg *)0x41018050UL) /**< \brief (TCC1) Compare and Capture 3 */
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| 86 | #define REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL) /**< \brief (TCC1) Pattern Buffer */
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| 87 | #define REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL) /**< \brief (TCC1) Period Buffer */
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| 88 | #define REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
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| 89 | #define REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
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| 90 | #define REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL) /**< \brief (TCC1) Compare and Capture Buffer 2 */
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| 91 | #define REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL) /**< \brief (TCC1) Compare and Capture Buffer 3 */
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| 92 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 93 |
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| 94 | /* ========== Instance parameters for TCC1 peripheral ========== */
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| 95 | #define TCC1_CC_NUM 4 // Number of Compare/Capture units
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| 96 | #define TCC1_DITHERING 1 // Dithering feature implemented
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| 97 | #define TCC1_DMAC_ID_MC_0 30
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| 98 | #define TCC1_DMAC_ID_MC_1 31
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| 99 | #define TCC1_DMAC_ID_MC_2 32
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| 100 | #define TCC1_DMAC_ID_MC_3 33
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| 101 | #define TCC1_DMAC_ID_MC_LSB 30
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| 102 | #define TCC1_DMAC_ID_MC_MSB 33
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| 103 | #define TCC1_DMAC_ID_MC_SIZE 4
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| 104 | #define TCC1_DMAC_ID_OVF 29 // DMA overflow/underflow/retrigger trigger
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| 105 | #define TCC1_DTI 1 // Dead-Time-Insertion feature implemented
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| 106 | #define TCC1_EXT 31 // Coding of implemented extended features
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| 107 | #define TCC1_GCLK_ID 25 // Index of Generic Clock
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| 108 | #define TCC1_MASTER_SLAVE_MODE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
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| 109 | #define TCC1_OTMX 1 // Output Matrix feature implemented
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| 110 | #define TCC1_OW_NUM 8 // Number of Output Waveforms
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| 111 | #define TCC1_PG 1 // Pattern Generation feature implemented
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| 112 | #define TCC1_SIZE 24
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| 113 | #define TCC1_SWAP 1 // DTI outputs swap feature implemented
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| 114 |
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| 115 | #endif /* _SAME54_TCC1_INSTANCE_ */
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