| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
|
| 2 | * \file
|
| 3 | *
|
| 4 | * \brief Instance description for TC2
|
| 5 | *
|
| 6 | * Copyright (c) 2019 Microchip Technology Inc.
|
| 7 | *
|
| 8 | * \asf_license_start
|
| 9 | *
|
| 10 | * \page License
|
| 11 | *
|
| 12 | * SPDX-License-Identifier: Apache-2.0
|
| 13 | *
|
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
|
| 15 | * not use this file except in compliance with the License.
|
| 16 | * You may obtain a copy of the Licence at
|
| 17 | *
|
| 18 | * http://www.apache.org/licenses/LICENSE-2.0
|
| 19 | *
|
| 20 | * Unless required by applicable law or agreed to in writing, software
|
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
| 23 | * See the License for the specific language governing permissions and
|
| 24 | * limitations under the License.
|
| 25 | *
|
| 26 | * \asf_license_stop
|
| 27 | *
|
| 28 | */
|
| 29 |
|
| 30 | #ifndef _SAME54_TC2_INSTANCE_
|
| 31 | #define _SAME54_TC2_INSTANCE_
|
| 32 |
|
| 33 | /* ========== Register definition for TC2 peripheral ========== */
|
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 35 | #define REG_TC2_CTRLA (0x4101A000) /**< \brief (TC2) Control A */
|
| 36 | #define REG_TC2_CTRLBCLR (0x4101A004) /**< \brief (TC2) Control B Clear */
|
| 37 | #define REG_TC2_CTRLBSET (0x4101A005) /**< \brief (TC2) Control B Set */
|
| 38 | #define REG_TC2_EVCTRL (0x4101A006) /**< \brief (TC2) Event Control */
|
| 39 | #define REG_TC2_INTENCLR (0x4101A008) /**< \brief (TC2) Interrupt Enable Clear */
|
| 40 | #define REG_TC2_INTENSET (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */
|
| 41 | #define REG_TC2_INTFLAG (0x4101A00A) /**< \brief (TC2) Interrupt Flag Status and Clear */
|
| 42 | #define REG_TC2_STATUS (0x4101A00B) /**< \brief (TC2) Status */
|
| 43 | #define REG_TC2_WAVE (0x4101A00C) /**< \brief (TC2) Waveform Generation Control */
|
| 44 | #define REG_TC2_DRVCTRL (0x4101A00D) /**< \brief (TC2) Control C */
|
| 45 | #define REG_TC2_DBGCTRL (0x4101A00F) /**< \brief (TC2) Debug Control */
|
| 46 | #define REG_TC2_SYNCBUSY (0x4101A010) /**< \brief (TC2) Synchronization Status */
|
| 47 | #define REG_TC2_COUNT16_COUNT (0x4101A014) /**< \brief (TC2) COUNT16 Count */
|
| 48 | #define REG_TC2_COUNT16_CC0 (0x4101A01C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
|
| 49 | #define REG_TC2_COUNT16_CC1 (0x4101A01E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
|
| 50 | #define REG_TC2_COUNT16_CCBUF0 (0x4101A030) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
|
| 51 | #define REG_TC2_COUNT16_CCBUF1 (0x4101A032) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
|
| 52 | #define REG_TC2_COUNT32_COUNT (0x4101A014) /**< \brief (TC2) COUNT32 Count */
|
| 53 | #define REG_TC2_COUNT32_CC0 (0x4101A01C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
|
| 54 | #define REG_TC2_COUNT32_CC1 (0x4101A020) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
|
| 55 | #define REG_TC2_COUNT32_CCBUF0 (0x4101A030) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
|
| 56 | #define REG_TC2_COUNT32_CCBUF1 (0x4101A034) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
|
| 57 | #define REG_TC2_COUNT8_COUNT (0x4101A014) /**< \brief (TC2) COUNT8 Count */
|
| 58 | #define REG_TC2_COUNT8_PER (0x4101A01B) /**< \brief (TC2) COUNT8 Period */
|
| 59 | #define REG_TC2_COUNT8_CC0 (0x4101A01C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
|
| 60 | #define REG_TC2_COUNT8_CC1 (0x4101A01D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
|
| 61 | #define REG_TC2_COUNT8_PERBUF (0x4101A02F) /**< \brief (TC2) COUNT8 Period Buffer */
|
| 62 | #define REG_TC2_COUNT8_CCBUF0 (0x4101A030) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
|
| 63 | #define REG_TC2_COUNT8_CCBUF1 (0x4101A031) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
|
| 64 | #else
|
| 65 | #define REG_TC2_CTRLA (*(RwReg *)0x4101A000UL) /**< \brief (TC2) Control A */
|
| 66 | #define REG_TC2_CTRLBCLR (*(RwReg8 *)0x4101A004UL) /**< \brief (TC2) Control B Clear */
|
| 67 | #define REG_TC2_CTRLBSET (*(RwReg8 *)0x4101A005UL) /**< \brief (TC2) Control B Set */
|
| 68 | #define REG_TC2_EVCTRL (*(RwReg16*)0x4101A006UL) /**< \brief (TC2) Event Control */
|
| 69 | #define REG_TC2_INTENCLR (*(RwReg8 *)0x4101A008UL) /**< \brief (TC2) Interrupt Enable Clear */
|
| 70 | #define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set */
|
| 71 | #define REG_TC2_INTFLAG (*(RwReg8 *)0x4101A00AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
|
| 72 | #define REG_TC2_STATUS (*(RwReg8 *)0x4101A00BUL) /**< \brief (TC2) Status */
|
| 73 | #define REG_TC2_WAVE (*(RwReg8 *)0x4101A00CUL) /**< \brief (TC2) Waveform Generation Control */
|
| 74 | #define REG_TC2_DRVCTRL (*(RwReg8 *)0x4101A00DUL) /**< \brief (TC2) Control C */
|
| 75 | #define REG_TC2_DBGCTRL (*(RwReg8 *)0x4101A00FUL) /**< \brief (TC2) Debug Control */
|
| 76 | #define REG_TC2_SYNCBUSY (*(RoReg *)0x4101A010UL) /**< \brief (TC2) Synchronization Status */
|
| 77 | #define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x4101A014UL) /**< \brief (TC2) COUNT16 Count */
|
| 78 | #define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4101A01CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
|
| 79 | #define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4101A01EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
|
| 80 | #define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x4101A030UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
|
| 81 | #define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x4101A032UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
|
| 82 | #define REG_TC2_COUNT32_COUNT (*(RwReg *)0x4101A014UL) /**< \brief (TC2) COUNT32 Count */
|
| 83 | #define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4101A01CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
|
| 84 | #define REG_TC2_COUNT32_CC1 (*(RwReg *)0x4101A020UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
|
| 85 | #define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x4101A030UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
|
| 86 | #define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x4101A034UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
|
| 87 | #define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x4101A014UL) /**< \brief (TC2) COUNT8 Count */
|
| 88 | #define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4101A01BUL) /**< \brief (TC2) COUNT8 Period */
|
| 89 | #define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4101A01CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
|
| 90 | #define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4101A01DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
|
| 91 | #define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4101A02FUL) /**< \brief (TC2) COUNT8 Period Buffer */
|
| 92 | #define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x4101A030UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
|
| 93 | #define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x4101A031UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
|
| 94 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 95 |
|
| 96 | /* ========== Instance parameters for TC2 peripheral ========== */
|
| 97 | #define TC2_CC_NUM 2
|
| 98 | #define TC2_DMAC_ID_MC_0 51
|
| 99 | #define TC2_DMAC_ID_MC_1 52
|
| 100 | #define TC2_DMAC_ID_MC_LSB 51
|
| 101 | #define TC2_DMAC_ID_MC_MSB 52
|
| 102 | #define TC2_DMAC_ID_MC_SIZE 2
|
| 103 | #define TC2_DMAC_ID_OVF 50 // Indexes of DMA Overflow trigger
|
| 104 | #define TC2_EXT 0 // Coding of implemented extended features (keep 0 value)
|
| 105 | #define TC2_GCLK_ID 26 // Index of Generic Clock
|
| 106 | #define TC2_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
|
| 107 | #define TC2_OW_NUM 2 // Number of Output Waveforms
|
| 108 |
|
| 109 | #endif /* _SAME54_TC2_INSTANCE_ */
|