| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for TC0
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_TC0_INSTANCE_
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| 31 | #define _SAME54_TC0_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for TC0 peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_TC0_CTRLA (0x40003800) /**< \brief (TC0) Control A */
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| 36 | #define REG_TC0_CTRLBCLR (0x40003804) /**< \brief (TC0) Control B Clear */
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| 37 | #define REG_TC0_CTRLBSET (0x40003805) /**< \brief (TC0) Control B Set */
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| 38 | #define REG_TC0_EVCTRL (0x40003806) /**< \brief (TC0) Event Control */
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| 39 | #define REG_TC0_INTENCLR (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */
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| 40 | #define REG_TC0_INTENSET (0x40003809) /**< \brief (TC0) Interrupt Enable Set */
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| 41 | #define REG_TC0_INTFLAG (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */
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| 42 | #define REG_TC0_STATUS (0x4000380B) /**< \brief (TC0) Status */
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| 43 | #define REG_TC0_WAVE (0x4000380C) /**< \brief (TC0) Waveform Generation Control */
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| 44 | #define REG_TC0_DRVCTRL (0x4000380D) /**< \brief (TC0) Control C */
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| 45 | #define REG_TC0_DBGCTRL (0x4000380F) /**< \brief (TC0) Debug Control */
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| 46 | #define REG_TC0_SYNCBUSY (0x40003810) /**< \brief (TC0) Synchronization Status */
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| 47 | #define REG_TC0_COUNT16_COUNT (0x40003814) /**< \brief (TC0) COUNT16 Count */
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| 48 | #define REG_TC0_COUNT16_CC0 (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
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| 49 | #define REG_TC0_COUNT16_CC1 (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
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| 50 | #define REG_TC0_COUNT16_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
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| 51 | #define REG_TC0_COUNT16_CCBUF1 (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
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| 52 | #define REG_TC0_COUNT32_COUNT (0x40003814) /**< \brief (TC0) COUNT32 Count */
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| 53 | #define REG_TC0_COUNT32_CC0 (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
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| 54 | #define REG_TC0_COUNT32_CC1 (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
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| 55 | #define REG_TC0_COUNT32_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
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| 56 | #define REG_TC0_COUNT32_CCBUF1 (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
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| 57 | #define REG_TC0_COUNT8_COUNT (0x40003814) /**< \brief (TC0) COUNT8 Count */
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| 58 | #define REG_TC0_COUNT8_PER (0x4000381B) /**< \brief (TC0) COUNT8 Period */
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| 59 | #define REG_TC0_COUNT8_CC0 (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
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| 60 | #define REG_TC0_COUNT8_CC1 (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
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| 61 | #define REG_TC0_COUNT8_PERBUF (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */
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| 62 | #define REG_TC0_COUNT8_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
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| 63 | #define REG_TC0_COUNT8_CCBUF1 (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
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| 64 | #else
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| 65 | #define REG_TC0_CTRLA (*(RwReg *)0x40003800UL) /**< \brief (TC0) Control A */
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| 66 | #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */
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| 67 | #define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */
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| 68 | #define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */
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| 69 | #define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */
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| 70 | #define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */
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| 71 | #define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
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| 72 | #define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */
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| 73 | #define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */
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| 74 | #define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */
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| 75 | #define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */
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| 76 | #define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL) /**< \brief (TC0) Synchronization Status */
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| 77 | #define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */
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| 78 | #define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
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| 79 | #define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
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| 80 | #define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
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| 81 | #define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
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| 82 | #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */
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| 83 | #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
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| 84 | #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
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| 85 | #define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
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| 86 | #define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
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| 87 | #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */
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| 88 | #define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */
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| 89 | #define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
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| 90 | #define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
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| 91 | #define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */
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| 92 | #define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
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| 93 | #define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
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| 94 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 95 |
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| 96 | /* ========== Instance parameters for TC0 peripheral ========== */
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| 97 | #define TC0_CC_NUM 2
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| 98 | #define TC0_DMAC_ID_MC_0 45
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| 99 | #define TC0_DMAC_ID_MC_1 46
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| 100 | #define TC0_DMAC_ID_MC_LSB 45
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| 101 | #define TC0_DMAC_ID_MC_MSB 46
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| 102 | #define TC0_DMAC_ID_MC_SIZE 2
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| 103 | #define TC0_DMAC_ID_OVF 44 // Indexes of DMA Overflow trigger
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| 104 | #define TC0_EXT 0 // Coding of implemented extended features (keep 0 value)
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| 105 | #define TC0_GCLK_ID 9 // Index of Generic Clock
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| 106 | #define TC0_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
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| 107 | #define TC0_OW_NUM 2 // Number of Output Waveforms
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| 108 |
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| 109 | #endif /* _SAME54_TC0_INSTANCE_ */
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