| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for RTC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_RTC_INSTANCE_
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| 31 | #define _SAME54_RTC_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for RTC peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */
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| 36 | #define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */
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| 37 | #define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */
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| 38 | #define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */
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| 39 | #define REG_RTC_GP2 (0x40002448) /**< \brief (RTC) General Purpose 2 */
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| 40 | #define REG_RTC_GP3 (0x4000244C) /**< \brief (RTC) General Purpose 3 */
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| 41 | #define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */
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| 42 | #define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */
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| 43 | #define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */
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| 44 | #define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */
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| 45 | #define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */
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| 46 | #define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */
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| 47 | #define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */
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| 48 | #define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */
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| 49 | #define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */
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| 50 | #define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */
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| 51 | #define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */
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| 52 | #define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */
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| 53 | #define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */
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| 54 | #define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
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| 55 | #define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
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| 56 | #define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
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| 57 | #define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
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| 58 | #define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
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| 59 | #define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
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| 60 | #define REG_RTC_MODE0_COMP1 (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */
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| 61 | #define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */
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| 62 | #define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */
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| 63 | #define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */
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| 64 | #define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */
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| 65 | #define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
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| 66 | #define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
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| 67 | #define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
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| 68 | #define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
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| 69 | #define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
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| 70 | #define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
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| 71 | #define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
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| 72 | #define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
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| 73 | #define REG_RTC_MODE1_COMP2 (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */
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| 74 | #define REG_RTC_MODE1_COMP3 (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */
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| 75 | #define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */
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| 76 | #define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */
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| 77 | #define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */
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| 78 | #define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */
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| 79 | #define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
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| 80 | #define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
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| 81 | #define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
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| 82 | #define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
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| 83 | #define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
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| 84 | #define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */
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| 85 | #define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
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| 86 | #define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
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| 87 | #define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
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| 88 | #define REG_RTC_MODE2_ALARM_MASK1 (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
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| 89 | #else
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| 90 | #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
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| 91 | #define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
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| 92 | #define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */
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| 93 | #define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */
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| 94 | #define REG_RTC_GP2 (*(RwReg *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */
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| 95 | #define REG_RTC_GP3 (*(RwReg *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */
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| 96 | #define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */
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| 97 | #define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */
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| 98 | #define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */
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| 99 | #define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */
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| 100 | #define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */
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| 101 | #define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */
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| 102 | #define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */
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| 103 | #define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */
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| 104 | #define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */
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| 105 | #define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */
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| 106 | #define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
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| 107 | #define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */
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| 108 | #define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
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| 109 | #define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
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| 110 | #define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
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| 111 | #define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
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| 112 | #define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
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| 113 | #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
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| 114 | #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
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| 115 | #define REG_RTC_MODE0_COMP1 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */
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| 116 | #define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */
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| 117 | #define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
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| 118 | #define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */
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| 119 | #define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
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| 120 | #define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
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| 121 | #define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
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| 122 | #define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
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| 123 | #define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
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| 124 | #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
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| 125 | #define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
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| 126 | #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
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| 127 | #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
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| 128 | #define REG_RTC_MODE1_COMP2 (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */
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| 129 | #define REG_RTC_MODE1_COMP3 (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */
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| 130 | #define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */
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| 131 | #define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
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| 132 | #define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */
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| 133 | #define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
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| 134 | #define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
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| 135 | #define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
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| 136 | #define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
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| 137 | #define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
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| 138 | #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
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| 139 | #define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */
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| 140 | #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
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| 141 | #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
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| 142 | #define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
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| 143 | #define REG_RTC_MODE2_ALARM_MASK1 (*(RwReg8 *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
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| 144 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 145 |
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| 146 | /* ========== Instance parameters for RTC peripheral ========== */
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| 147 | #define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger
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| 148 | #define RTC_GPR_NUM 4 // Number of General-Purpose Registers
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| 149 | #define RTC_NUM_OF_ALARMS 2 // Number of Alarms
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| 150 | #define RTC_NUM_OF_BKREGS 8 // Number of Backup Registers
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| 151 | #define RTC_NUM_OF_COMP16 4 // Number of 16-bit Comparators
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| 152 | #define RTC_NUM_OF_COMP32 2 // Number of 32-bit Comparators
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| 153 | #define RTC_NUM_OF_TAMPERS 5 // Number of Tamper Inputs
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| 154 | #define RTC_PER_NUM 8 // Number of Periodic Intervals
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| 155 |
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| 156 | #endif /* _SAME54_RTC_INSTANCE_ */
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