| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for EIC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_EIC_INSTANCE_
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| 31 | #define _SAME54_EIC_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for EIC peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control A */
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| 36 | #define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */
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| 37 | #define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
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| 38 | #define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Synchronization Busy */
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| 39 | #define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */
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| 40 | #define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
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| 41 | #define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
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| 42 | #define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
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| 43 | #define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */
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| 44 | #define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
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| 45 | #define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
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| 46 | #define REG_EIC_DEBOUNCEN (0x40002830) /**< \brief (EIC) Debouncer Enable */
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| 47 | #define REG_EIC_DPRESCALER (0x40002834) /**< \brief (EIC) Debouncer Prescaler */
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| 48 | #define REG_EIC_PINSTATE (0x40002838) /**< \brief (EIC) Pin State */
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| 49 | #else
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| 50 | #define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */
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| 51 | #define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
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| 52 | #define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
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| 53 | #define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */
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| 54 | #define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */
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| 55 | #define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
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| 56 | #define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
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| 57 | #define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
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| 58 | #define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */
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| 59 | #define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
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| 60 | #define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
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| 61 | #define REG_EIC_DEBOUNCEN (*(RwReg *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */
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| 62 | #define REG_EIC_DPRESCALER (*(RwReg *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */
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| 63 | #define REG_EIC_PINSTATE (*(RoReg *)0x40002838UL) /**< \brief (EIC) Pin State */
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| 64 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 65 |
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| 66 | /* ========== Instance parameters for EIC peripheral ========== */
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| 67 | #define EIC_EXTINT_NUM 16 // Number of external interrupts
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| 68 | #define EIC_GCLK_ID 4 // Generic Clock index
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| 69 | #define EIC_NUMBER_OF_CONFIG_REGS 2 // Number of CONFIG registers
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| 70 | #define EIC_NUMBER_OF_DPRESCALER_REGS 2 // Number of DPRESCALER pin groups
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| 71 | #define EIC_NUMBER_OF_INTERRUPTS 16 // Number of external interrupts (obsolete)
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| 72 |
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| 73 | #endif /* _SAME54_EIC_INSTANCE_ */
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