| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for DMAC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_DMAC_INSTANCE_
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| 31 | #define _SAME54_DMAC_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for DMAC peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_DMAC_CTRL (0x4100A000) /**< \brief (DMAC) Control */
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| 36 | #define REG_DMAC_CRCCTRL (0x4100A002) /**< \brief (DMAC) CRC Control */
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| 37 | #define REG_DMAC_CRCDATAIN (0x4100A004) /**< \brief (DMAC) CRC Data Input */
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| 38 | #define REG_DMAC_CRCCHKSUM (0x4100A008) /**< \brief (DMAC) CRC Checksum */
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| 39 | #define REG_DMAC_CRCSTATUS (0x4100A00C) /**< \brief (DMAC) CRC Status */
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| 40 | #define REG_DMAC_DBGCTRL (0x4100A00D) /**< \brief (DMAC) Debug Control */
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| 41 | #define REG_DMAC_SWTRIGCTRL (0x4100A010) /**< \brief (DMAC) Software Trigger Control */
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| 42 | #define REG_DMAC_PRICTRL0 (0x4100A014) /**< \brief (DMAC) Priority Control 0 */
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| 43 | #define REG_DMAC_INTPEND (0x4100A020) /**< \brief (DMAC) Interrupt Pending */
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| 44 | #define REG_DMAC_INTSTATUS (0x4100A024) /**< \brief (DMAC) Interrupt Status */
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| 45 | #define REG_DMAC_BUSYCH (0x4100A028) /**< \brief (DMAC) Busy Channels */
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| 46 | #define REG_DMAC_PENDCH (0x4100A02C) /**< \brief (DMAC) Pending Channels */
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| 47 | #define REG_DMAC_ACTIVE (0x4100A030) /**< \brief (DMAC) Active Channel and Levels */
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| 48 | #define REG_DMAC_BASEADDR (0x4100A034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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| 49 | #define REG_DMAC_WRBADDR (0x4100A038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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| 50 | #define REG_DMAC_CHCTRLA0 (0x4100A040) /**< \brief (DMAC) Channel 0 Control A */
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| 51 | #define REG_DMAC_CHCTRLB0 (0x4100A044) /**< \brief (DMAC) Channel 0 Control B */
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| 52 | #define REG_DMAC_CHPRILVL0 (0x4100A045) /**< \brief (DMAC) Channel 0 Priority Level */
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| 53 | #define REG_DMAC_CHEVCTRL0 (0x4100A046) /**< \brief (DMAC) Channel 0 Event Control */
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| 54 | #define REG_DMAC_CHINTENCLR0 (0x4100A04C) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
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| 55 | #define REG_DMAC_CHINTENSET0 (0x4100A04D) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
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| 56 | #define REG_DMAC_CHINTFLAG0 (0x4100A04E) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
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| 57 | #define REG_DMAC_CHSTATUS0 (0x4100A04F) /**< \brief (DMAC) Channel 0 Status */
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| 58 | #define REG_DMAC_CHCTRLA1 (0x4100A050) /**< \brief (DMAC) Channel 1 Control A */
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| 59 | #define REG_DMAC_CHCTRLB1 (0x4100A054) /**< \brief (DMAC) Channel 1 Control B */
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| 60 | #define REG_DMAC_CHPRILVL1 (0x4100A055) /**< \brief (DMAC) Channel 1 Priority Level */
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| 61 | #define REG_DMAC_CHEVCTRL1 (0x4100A056) /**< \brief (DMAC) Channel 1 Event Control */
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| 62 | #define REG_DMAC_CHINTENCLR1 (0x4100A05C) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
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| 63 | #define REG_DMAC_CHINTENSET1 (0x4100A05D) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
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| 64 | #define REG_DMAC_CHINTFLAG1 (0x4100A05E) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
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| 65 | #define REG_DMAC_CHSTATUS1 (0x4100A05F) /**< \brief (DMAC) Channel 1 Status */
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| 66 | #define REG_DMAC_CHCTRLA2 (0x4100A060) /**< \brief (DMAC) Channel 2 Control A */
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| 67 | #define REG_DMAC_CHCTRLB2 (0x4100A064) /**< \brief (DMAC) Channel 2 Control B */
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| 68 | #define REG_DMAC_CHPRILVL2 (0x4100A065) /**< \brief (DMAC) Channel 2 Priority Level */
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| 69 | #define REG_DMAC_CHEVCTRL2 (0x4100A066) /**< \brief (DMAC) Channel 2 Event Control */
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| 70 | #define REG_DMAC_CHINTENCLR2 (0x4100A06C) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
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| 71 | #define REG_DMAC_CHINTENSET2 (0x4100A06D) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
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| 72 | #define REG_DMAC_CHINTFLAG2 (0x4100A06E) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
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| 73 | #define REG_DMAC_CHSTATUS2 (0x4100A06F) /**< \brief (DMAC) Channel 2 Status */
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| 74 | #define REG_DMAC_CHCTRLA3 (0x4100A070) /**< \brief (DMAC) Channel 3 Control A */
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| 75 | #define REG_DMAC_CHCTRLB3 (0x4100A074) /**< \brief (DMAC) Channel 3 Control B */
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| 76 | #define REG_DMAC_CHPRILVL3 (0x4100A075) /**< \brief (DMAC) Channel 3 Priority Level */
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| 77 | #define REG_DMAC_CHEVCTRL3 (0x4100A076) /**< \brief (DMAC) Channel 3 Event Control */
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| 78 | #define REG_DMAC_CHINTENCLR3 (0x4100A07C) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
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| 79 | #define REG_DMAC_CHINTENSET3 (0x4100A07D) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
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| 80 | #define REG_DMAC_CHINTFLAG3 (0x4100A07E) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
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| 81 | #define REG_DMAC_CHSTATUS3 (0x4100A07F) /**< \brief (DMAC) Channel 3 Status */
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| 82 | #define REG_DMAC_CHCTRLA4 (0x4100A080) /**< \brief (DMAC) Channel 4 Control A */
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| 83 | #define REG_DMAC_CHCTRLB4 (0x4100A084) /**< \brief (DMAC) Channel 4 Control B */
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| 84 | #define REG_DMAC_CHPRILVL4 (0x4100A085) /**< \brief (DMAC) Channel 4 Priority Level */
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| 85 | #define REG_DMAC_CHEVCTRL4 (0x4100A086) /**< \brief (DMAC) Channel 4 Event Control */
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| 86 | #define REG_DMAC_CHINTENCLR4 (0x4100A08C) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
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| 87 | #define REG_DMAC_CHINTENSET4 (0x4100A08D) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
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| 88 | #define REG_DMAC_CHINTFLAG4 (0x4100A08E) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
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| 89 | #define REG_DMAC_CHSTATUS4 (0x4100A08F) /**< \brief (DMAC) Channel 4 Status */
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| 90 | #define REG_DMAC_CHCTRLA5 (0x4100A090) /**< \brief (DMAC) Channel 5 Control A */
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| 91 | #define REG_DMAC_CHCTRLB5 (0x4100A094) /**< \brief (DMAC) Channel 5 Control B */
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| 92 | #define REG_DMAC_CHPRILVL5 (0x4100A095) /**< \brief (DMAC) Channel 5 Priority Level */
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| 93 | #define REG_DMAC_CHEVCTRL5 (0x4100A096) /**< \brief (DMAC) Channel 5 Event Control */
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| 94 | #define REG_DMAC_CHINTENCLR5 (0x4100A09C) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
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| 95 | #define REG_DMAC_CHINTENSET5 (0x4100A09D) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
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| 96 | #define REG_DMAC_CHINTFLAG5 (0x4100A09E) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
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| 97 | #define REG_DMAC_CHSTATUS5 (0x4100A09F) /**< \brief (DMAC) Channel 5 Status */
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| 98 | #define REG_DMAC_CHCTRLA6 (0x4100A0A0) /**< \brief (DMAC) Channel 6 Control A */
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| 99 | #define REG_DMAC_CHCTRLB6 (0x4100A0A4) /**< \brief (DMAC) Channel 6 Control B */
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| 100 | #define REG_DMAC_CHPRILVL6 (0x4100A0A5) /**< \brief (DMAC) Channel 6 Priority Level */
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| 101 | #define REG_DMAC_CHEVCTRL6 (0x4100A0A6) /**< \brief (DMAC) Channel 6 Event Control */
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| 102 | #define REG_DMAC_CHINTENCLR6 (0x4100A0AC) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
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| 103 | #define REG_DMAC_CHINTENSET6 (0x4100A0AD) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
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| 104 | #define REG_DMAC_CHINTFLAG6 (0x4100A0AE) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
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| 105 | #define REG_DMAC_CHSTATUS6 (0x4100A0AF) /**< \brief (DMAC) Channel 6 Status */
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| 106 | #define REG_DMAC_CHCTRLA7 (0x4100A0B0) /**< \brief (DMAC) Channel 7 Control A */
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| 107 | #define REG_DMAC_CHCTRLB7 (0x4100A0B4) /**< \brief (DMAC) Channel 7 Control B */
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| 108 | #define REG_DMAC_CHPRILVL7 (0x4100A0B5) /**< \brief (DMAC) Channel 7 Priority Level */
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| 109 | #define REG_DMAC_CHEVCTRL7 (0x4100A0B6) /**< \brief (DMAC) Channel 7 Event Control */
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| 110 | #define REG_DMAC_CHINTENCLR7 (0x4100A0BC) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
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| 111 | #define REG_DMAC_CHINTENSET7 (0x4100A0BD) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
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| 112 | #define REG_DMAC_CHINTFLAG7 (0x4100A0BE) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
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| 113 | #define REG_DMAC_CHSTATUS7 (0x4100A0BF) /**< \brief (DMAC) Channel 7 Status */
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| 114 | #define REG_DMAC_CHCTRLA8 (0x4100A0C0) /**< \brief (DMAC) Channel 8 Control A */
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| 115 | #define REG_DMAC_CHCTRLB8 (0x4100A0C4) /**< \brief (DMAC) Channel 8 Control B */
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| 116 | #define REG_DMAC_CHPRILVL8 (0x4100A0C5) /**< \brief (DMAC) Channel 8 Priority Level */
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| 117 | #define REG_DMAC_CHEVCTRL8 (0x4100A0C6) /**< \brief (DMAC) Channel 8 Event Control */
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| 118 | #define REG_DMAC_CHINTENCLR8 (0x4100A0CC) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
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| 119 | #define REG_DMAC_CHINTENSET8 (0x4100A0CD) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
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| 120 | #define REG_DMAC_CHINTFLAG8 (0x4100A0CE) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
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| 121 | #define REG_DMAC_CHSTATUS8 (0x4100A0CF) /**< \brief (DMAC) Channel 8 Status */
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| 122 | #define REG_DMAC_CHCTRLA9 (0x4100A0D0) /**< \brief (DMAC) Channel 9 Control A */
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| 123 | #define REG_DMAC_CHCTRLB9 (0x4100A0D4) /**< \brief (DMAC) Channel 9 Control B */
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| 124 | #define REG_DMAC_CHPRILVL9 (0x4100A0D5) /**< \brief (DMAC) Channel 9 Priority Level */
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| 125 | #define REG_DMAC_CHEVCTRL9 (0x4100A0D6) /**< \brief (DMAC) Channel 9 Event Control */
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| 126 | #define REG_DMAC_CHINTENCLR9 (0x4100A0DC) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
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| 127 | #define REG_DMAC_CHINTENSET9 (0x4100A0DD) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
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| 128 | #define REG_DMAC_CHINTFLAG9 (0x4100A0DE) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
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| 129 | #define REG_DMAC_CHSTATUS9 (0x4100A0DF) /**< \brief (DMAC) Channel 9 Status */
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| 130 | #define REG_DMAC_CHCTRLA10 (0x4100A0E0) /**< \brief (DMAC) Channel 10 Control A */
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| 131 | #define REG_DMAC_CHCTRLB10 (0x4100A0E4) /**< \brief (DMAC) Channel 10 Control B */
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| 132 | #define REG_DMAC_CHPRILVL10 (0x4100A0E5) /**< \brief (DMAC) Channel 10 Priority Level */
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| 133 | #define REG_DMAC_CHEVCTRL10 (0x4100A0E6) /**< \brief (DMAC) Channel 10 Event Control */
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| 134 | #define REG_DMAC_CHINTENCLR10 (0x4100A0EC) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
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| 135 | #define REG_DMAC_CHINTENSET10 (0x4100A0ED) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
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| 136 | #define REG_DMAC_CHINTFLAG10 (0x4100A0EE) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
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| 137 | #define REG_DMAC_CHSTATUS10 (0x4100A0EF) /**< \brief (DMAC) Channel 10 Status */
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| 138 | #define REG_DMAC_CHCTRLA11 (0x4100A0F0) /**< \brief (DMAC) Channel 11 Control A */
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| 139 | #define REG_DMAC_CHCTRLB11 (0x4100A0F4) /**< \brief (DMAC) Channel 11 Control B */
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| 140 | #define REG_DMAC_CHPRILVL11 (0x4100A0F5) /**< \brief (DMAC) Channel 11 Priority Level */
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| 141 | #define REG_DMAC_CHEVCTRL11 (0x4100A0F6) /**< \brief (DMAC) Channel 11 Event Control */
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| 142 | #define REG_DMAC_CHINTENCLR11 (0x4100A0FC) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
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| 143 | #define REG_DMAC_CHINTENSET11 (0x4100A0FD) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
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| 144 | #define REG_DMAC_CHINTFLAG11 (0x4100A0FE) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
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| 145 | #define REG_DMAC_CHSTATUS11 (0x4100A0FF) /**< \brief (DMAC) Channel 11 Status */
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| 146 | #define REG_DMAC_CHCTRLA12 (0x4100A100) /**< \brief (DMAC) Channel 12 Control A */
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| 147 | #define REG_DMAC_CHCTRLB12 (0x4100A104) /**< \brief (DMAC) Channel 12 Control B */
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| 148 | #define REG_DMAC_CHPRILVL12 (0x4100A105) /**< \brief (DMAC) Channel 12 Priority Level */
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| 149 | #define REG_DMAC_CHEVCTRL12 (0x4100A106) /**< \brief (DMAC) Channel 12 Event Control */
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| 150 | #define REG_DMAC_CHINTENCLR12 (0x4100A10C) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
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| 151 | #define REG_DMAC_CHINTENSET12 (0x4100A10D) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
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| 152 | #define REG_DMAC_CHINTFLAG12 (0x4100A10E) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
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| 153 | #define REG_DMAC_CHSTATUS12 (0x4100A10F) /**< \brief (DMAC) Channel 12 Status */
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| 154 | #define REG_DMAC_CHCTRLA13 (0x4100A110) /**< \brief (DMAC) Channel 13 Control A */
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| 155 | #define REG_DMAC_CHCTRLB13 (0x4100A114) /**< \brief (DMAC) Channel 13 Control B */
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| 156 | #define REG_DMAC_CHPRILVL13 (0x4100A115) /**< \brief (DMAC) Channel 13 Priority Level */
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| 157 | #define REG_DMAC_CHEVCTRL13 (0x4100A116) /**< \brief (DMAC) Channel 13 Event Control */
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| 158 | #define REG_DMAC_CHINTENCLR13 (0x4100A11C) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
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| 159 | #define REG_DMAC_CHINTENSET13 (0x4100A11D) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
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| 160 | #define REG_DMAC_CHINTFLAG13 (0x4100A11E) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
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| 161 | #define REG_DMAC_CHSTATUS13 (0x4100A11F) /**< \brief (DMAC) Channel 13 Status */
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| 162 | #define REG_DMAC_CHCTRLA14 (0x4100A120) /**< \brief (DMAC) Channel 14 Control A */
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| 163 | #define REG_DMAC_CHCTRLB14 (0x4100A124) /**< \brief (DMAC) Channel 14 Control B */
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| 164 | #define REG_DMAC_CHPRILVL14 (0x4100A125) /**< \brief (DMAC) Channel 14 Priority Level */
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| 165 | #define REG_DMAC_CHEVCTRL14 (0x4100A126) /**< \brief (DMAC) Channel 14 Event Control */
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| 166 | #define REG_DMAC_CHINTENCLR14 (0x4100A12C) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
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| 167 | #define REG_DMAC_CHINTENSET14 (0x4100A12D) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
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| 168 | #define REG_DMAC_CHINTFLAG14 (0x4100A12E) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
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| 169 | #define REG_DMAC_CHSTATUS14 (0x4100A12F) /**< \brief (DMAC) Channel 14 Status */
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| 170 | #define REG_DMAC_CHCTRLA15 (0x4100A130) /**< \brief (DMAC) Channel 15 Control A */
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| 171 | #define REG_DMAC_CHCTRLB15 (0x4100A134) /**< \brief (DMAC) Channel 15 Control B */
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| 172 | #define REG_DMAC_CHPRILVL15 (0x4100A135) /**< \brief (DMAC) Channel 15 Priority Level */
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| 173 | #define REG_DMAC_CHEVCTRL15 (0x4100A136) /**< \brief (DMAC) Channel 15 Event Control */
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| 174 | #define REG_DMAC_CHINTENCLR15 (0x4100A13C) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
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| 175 | #define REG_DMAC_CHINTENSET15 (0x4100A13D) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
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| 176 | #define REG_DMAC_CHINTFLAG15 (0x4100A13E) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
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| 177 | #define REG_DMAC_CHSTATUS15 (0x4100A13F) /**< \brief (DMAC) Channel 15 Status */
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| 178 | #define REG_DMAC_CHCTRLA16 (0x4100A140) /**< \brief (DMAC) Channel 16 Control A */
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| 179 | #define REG_DMAC_CHCTRLB16 (0x4100A144) /**< \brief (DMAC) Channel 16 Control B */
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| 180 | #define REG_DMAC_CHPRILVL16 (0x4100A145) /**< \brief (DMAC) Channel 16 Priority Level */
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| 181 | #define REG_DMAC_CHEVCTRL16 (0x4100A146) /**< \brief (DMAC) Channel 16 Event Control */
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| 182 | #define REG_DMAC_CHINTENCLR16 (0x4100A14C) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
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| 183 | #define REG_DMAC_CHINTENSET16 (0x4100A14D) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
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| 184 | #define REG_DMAC_CHINTFLAG16 (0x4100A14E) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
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| 185 | #define REG_DMAC_CHSTATUS16 (0x4100A14F) /**< \brief (DMAC) Channel 16 Status */
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| 186 | #define REG_DMAC_CHCTRLA17 (0x4100A150) /**< \brief (DMAC) Channel 17 Control A */
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| 187 | #define REG_DMAC_CHCTRLB17 (0x4100A154) /**< \brief (DMAC) Channel 17 Control B */
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| 188 | #define REG_DMAC_CHPRILVL17 (0x4100A155) /**< \brief (DMAC) Channel 17 Priority Level */
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| 189 | #define REG_DMAC_CHEVCTRL17 (0x4100A156) /**< \brief (DMAC) Channel 17 Event Control */
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| 190 | #define REG_DMAC_CHINTENCLR17 (0x4100A15C) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
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| 191 | #define REG_DMAC_CHINTENSET17 (0x4100A15D) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
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| 192 | #define REG_DMAC_CHINTFLAG17 (0x4100A15E) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
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| 193 | #define REG_DMAC_CHSTATUS17 (0x4100A15F) /**< \brief (DMAC) Channel 17 Status */
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| 194 | #define REG_DMAC_CHCTRLA18 (0x4100A160) /**< \brief (DMAC) Channel 18 Control A */
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| 195 | #define REG_DMAC_CHCTRLB18 (0x4100A164) /**< \brief (DMAC) Channel 18 Control B */
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| 196 | #define REG_DMAC_CHPRILVL18 (0x4100A165) /**< \brief (DMAC) Channel 18 Priority Level */
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| 197 | #define REG_DMAC_CHEVCTRL18 (0x4100A166) /**< \brief (DMAC) Channel 18 Event Control */
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| 198 | #define REG_DMAC_CHINTENCLR18 (0x4100A16C) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
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| 199 | #define REG_DMAC_CHINTENSET18 (0x4100A16D) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
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| 200 | #define REG_DMAC_CHINTFLAG18 (0x4100A16E) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
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| 201 | #define REG_DMAC_CHSTATUS18 (0x4100A16F) /**< \brief (DMAC) Channel 18 Status */
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| 202 | #define REG_DMAC_CHCTRLA19 (0x4100A170) /**< \brief (DMAC) Channel 19 Control A */
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| 203 | #define REG_DMAC_CHCTRLB19 (0x4100A174) /**< \brief (DMAC) Channel 19 Control B */
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| 204 | #define REG_DMAC_CHPRILVL19 (0x4100A175) /**< \brief (DMAC) Channel 19 Priority Level */
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| 205 | #define REG_DMAC_CHEVCTRL19 (0x4100A176) /**< \brief (DMAC) Channel 19 Event Control */
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| 206 | #define REG_DMAC_CHINTENCLR19 (0x4100A17C) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
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| 207 | #define REG_DMAC_CHINTENSET19 (0x4100A17D) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
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| 208 | #define REG_DMAC_CHINTFLAG19 (0x4100A17E) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
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| 209 | #define REG_DMAC_CHSTATUS19 (0x4100A17F) /**< \brief (DMAC) Channel 19 Status */
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| 210 | #define REG_DMAC_CHCTRLA20 (0x4100A180) /**< \brief (DMAC) Channel 20 Control A */
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| 211 | #define REG_DMAC_CHCTRLB20 (0x4100A184) /**< \brief (DMAC) Channel 20 Control B */
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| 212 | #define REG_DMAC_CHPRILVL20 (0x4100A185) /**< \brief (DMAC) Channel 20 Priority Level */
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| 213 | #define REG_DMAC_CHEVCTRL20 (0x4100A186) /**< \brief (DMAC) Channel 20 Event Control */
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| 214 | #define REG_DMAC_CHINTENCLR20 (0x4100A18C) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
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| 215 | #define REG_DMAC_CHINTENSET20 (0x4100A18D) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
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| 216 | #define REG_DMAC_CHINTFLAG20 (0x4100A18E) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
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| 217 | #define REG_DMAC_CHSTATUS20 (0x4100A18F) /**< \brief (DMAC) Channel 20 Status */
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| 218 | #define REG_DMAC_CHCTRLA21 (0x4100A190) /**< \brief (DMAC) Channel 21 Control A */
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| 219 | #define REG_DMAC_CHCTRLB21 (0x4100A194) /**< \brief (DMAC) Channel 21 Control B */
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| 220 | #define REG_DMAC_CHPRILVL21 (0x4100A195) /**< \brief (DMAC) Channel 21 Priority Level */
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| 221 | #define REG_DMAC_CHEVCTRL21 (0x4100A196) /**< \brief (DMAC) Channel 21 Event Control */
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| 222 | #define REG_DMAC_CHINTENCLR21 (0x4100A19C) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
|
| 223 | #define REG_DMAC_CHINTENSET21 (0x4100A19D) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
|
| 224 | #define REG_DMAC_CHINTFLAG21 (0x4100A19E) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
|
| 225 | #define REG_DMAC_CHSTATUS21 (0x4100A19F) /**< \brief (DMAC) Channel 21 Status */
|
| 226 | #define REG_DMAC_CHCTRLA22 (0x4100A1A0) /**< \brief (DMAC) Channel 22 Control A */
|
| 227 | #define REG_DMAC_CHCTRLB22 (0x4100A1A4) /**< \brief (DMAC) Channel 22 Control B */
|
| 228 | #define REG_DMAC_CHPRILVL22 (0x4100A1A5) /**< \brief (DMAC) Channel 22 Priority Level */
|
| 229 | #define REG_DMAC_CHEVCTRL22 (0x4100A1A6) /**< \brief (DMAC) Channel 22 Event Control */
|
| 230 | #define REG_DMAC_CHINTENCLR22 (0x4100A1AC) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
|
| 231 | #define REG_DMAC_CHINTENSET22 (0x4100A1AD) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
|
| 232 | #define REG_DMAC_CHINTFLAG22 (0x4100A1AE) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
|
| 233 | #define REG_DMAC_CHSTATUS22 (0x4100A1AF) /**< \brief (DMAC) Channel 22 Status */
|
| 234 | #define REG_DMAC_CHCTRLA23 (0x4100A1B0) /**< \brief (DMAC) Channel 23 Control A */
|
| 235 | #define REG_DMAC_CHCTRLB23 (0x4100A1B4) /**< \brief (DMAC) Channel 23 Control B */
|
| 236 | #define REG_DMAC_CHPRILVL23 (0x4100A1B5) /**< \brief (DMAC) Channel 23 Priority Level */
|
| 237 | #define REG_DMAC_CHEVCTRL23 (0x4100A1B6) /**< \brief (DMAC) Channel 23 Event Control */
|
| 238 | #define REG_DMAC_CHINTENCLR23 (0x4100A1BC) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
|
| 239 | #define REG_DMAC_CHINTENSET23 (0x4100A1BD) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
|
| 240 | #define REG_DMAC_CHINTFLAG23 (0x4100A1BE) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
|
| 241 | #define REG_DMAC_CHSTATUS23 (0x4100A1BF) /**< \brief (DMAC) Channel 23 Status */
|
| 242 | #define REG_DMAC_CHCTRLA24 (0x4100A1C0) /**< \brief (DMAC) Channel 24 Control A */
|
| 243 | #define REG_DMAC_CHCTRLB24 (0x4100A1C4) /**< \brief (DMAC) Channel 24 Control B */
|
| 244 | #define REG_DMAC_CHPRILVL24 (0x4100A1C5) /**< \brief (DMAC) Channel 24 Priority Level */
|
| 245 | #define REG_DMAC_CHEVCTRL24 (0x4100A1C6) /**< \brief (DMAC) Channel 24 Event Control */
|
| 246 | #define REG_DMAC_CHINTENCLR24 (0x4100A1CC) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
|
| 247 | #define REG_DMAC_CHINTENSET24 (0x4100A1CD) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
|
| 248 | #define REG_DMAC_CHINTFLAG24 (0x4100A1CE) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
|
| 249 | #define REG_DMAC_CHSTATUS24 (0x4100A1CF) /**< \brief (DMAC) Channel 24 Status */
|
| 250 | #define REG_DMAC_CHCTRLA25 (0x4100A1D0) /**< \brief (DMAC) Channel 25 Control A */
|
| 251 | #define REG_DMAC_CHCTRLB25 (0x4100A1D4) /**< \brief (DMAC) Channel 25 Control B */
|
| 252 | #define REG_DMAC_CHPRILVL25 (0x4100A1D5) /**< \brief (DMAC) Channel 25 Priority Level */
|
| 253 | #define REG_DMAC_CHEVCTRL25 (0x4100A1D6) /**< \brief (DMAC) Channel 25 Event Control */
|
| 254 | #define REG_DMAC_CHINTENCLR25 (0x4100A1DC) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
|
| 255 | #define REG_DMAC_CHINTENSET25 (0x4100A1DD) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
|
| 256 | #define REG_DMAC_CHINTFLAG25 (0x4100A1DE) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
|
| 257 | #define REG_DMAC_CHSTATUS25 (0x4100A1DF) /**< \brief (DMAC) Channel 25 Status */
|
| 258 | #define REG_DMAC_CHCTRLA26 (0x4100A1E0) /**< \brief (DMAC) Channel 26 Control A */
|
| 259 | #define REG_DMAC_CHCTRLB26 (0x4100A1E4) /**< \brief (DMAC) Channel 26 Control B */
|
| 260 | #define REG_DMAC_CHPRILVL26 (0x4100A1E5) /**< \brief (DMAC) Channel 26 Priority Level */
|
| 261 | #define REG_DMAC_CHEVCTRL26 (0x4100A1E6) /**< \brief (DMAC) Channel 26 Event Control */
|
| 262 | #define REG_DMAC_CHINTENCLR26 (0x4100A1EC) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
|
| 263 | #define REG_DMAC_CHINTENSET26 (0x4100A1ED) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
|
| 264 | #define REG_DMAC_CHINTFLAG26 (0x4100A1EE) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
|
| 265 | #define REG_DMAC_CHSTATUS26 (0x4100A1EF) /**< \brief (DMAC) Channel 26 Status */
|
| 266 | #define REG_DMAC_CHCTRLA27 (0x4100A1F0) /**< \brief (DMAC) Channel 27 Control A */
|
| 267 | #define REG_DMAC_CHCTRLB27 (0x4100A1F4) /**< \brief (DMAC) Channel 27 Control B */
|
| 268 | #define REG_DMAC_CHPRILVL27 (0x4100A1F5) /**< \brief (DMAC) Channel 27 Priority Level */
|
| 269 | #define REG_DMAC_CHEVCTRL27 (0x4100A1F6) /**< \brief (DMAC) Channel 27 Event Control */
|
| 270 | #define REG_DMAC_CHINTENCLR27 (0x4100A1FC) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
|
| 271 | #define REG_DMAC_CHINTENSET27 (0x4100A1FD) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
|
| 272 | #define REG_DMAC_CHINTFLAG27 (0x4100A1FE) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
|
| 273 | #define REG_DMAC_CHSTATUS27 (0x4100A1FF) /**< \brief (DMAC) Channel 27 Status */
|
| 274 | #define REG_DMAC_CHCTRLA28 (0x4100A200) /**< \brief (DMAC) Channel 28 Control A */
|
| 275 | #define REG_DMAC_CHCTRLB28 (0x4100A204) /**< \brief (DMAC) Channel 28 Control B */
|
| 276 | #define REG_DMAC_CHPRILVL28 (0x4100A205) /**< \brief (DMAC) Channel 28 Priority Level */
|
| 277 | #define REG_DMAC_CHEVCTRL28 (0x4100A206) /**< \brief (DMAC) Channel 28 Event Control */
|
| 278 | #define REG_DMAC_CHINTENCLR28 (0x4100A20C) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
|
| 279 | #define REG_DMAC_CHINTENSET28 (0x4100A20D) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
|
| 280 | #define REG_DMAC_CHINTFLAG28 (0x4100A20E) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
|
| 281 | #define REG_DMAC_CHSTATUS28 (0x4100A20F) /**< \brief (DMAC) Channel 28 Status */
|
| 282 | #define REG_DMAC_CHCTRLA29 (0x4100A210) /**< \brief (DMAC) Channel 29 Control A */
|
| 283 | #define REG_DMAC_CHCTRLB29 (0x4100A214) /**< \brief (DMAC) Channel 29 Control B */
|
| 284 | #define REG_DMAC_CHPRILVL29 (0x4100A215) /**< \brief (DMAC) Channel 29 Priority Level */
|
| 285 | #define REG_DMAC_CHEVCTRL29 (0x4100A216) /**< \brief (DMAC) Channel 29 Event Control */
|
| 286 | #define REG_DMAC_CHINTENCLR29 (0x4100A21C) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
|
| 287 | #define REG_DMAC_CHINTENSET29 (0x4100A21D) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
|
| 288 | #define REG_DMAC_CHINTFLAG29 (0x4100A21E) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
|
| 289 | #define REG_DMAC_CHSTATUS29 (0x4100A21F) /**< \brief (DMAC) Channel 29 Status */
|
| 290 | #define REG_DMAC_CHCTRLA30 (0x4100A220) /**< \brief (DMAC) Channel 30 Control A */
|
| 291 | #define REG_DMAC_CHCTRLB30 (0x4100A224) /**< \brief (DMAC) Channel 30 Control B */
|
| 292 | #define REG_DMAC_CHPRILVL30 (0x4100A225) /**< \brief (DMAC) Channel 30 Priority Level */
|
| 293 | #define REG_DMAC_CHEVCTRL30 (0x4100A226) /**< \brief (DMAC) Channel 30 Event Control */
|
| 294 | #define REG_DMAC_CHINTENCLR30 (0x4100A22C) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
|
| 295 | #define REG_DMAC_CHINTENSET30 (0x4100A22D) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
|
| 296 | #define REG_DMAC_CHINTFLAG30 (0x4100A22E) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
|
| 297 | #define REG_DMAC_CHSTATUS30 (0x4100A22F) /**< \brief (DMAC) Channel 30 Status */
|
| 298 | #define REG_DMAC_CHCTRLA31 (0x4100A230) /**< \brief (DMAC) Channel 31 Control A */
|
| 299 | #define REG_DMAC_CHCTRLB31 (0x4100A234) /**< \brief (DMAC) Channel 31 Control B */
|
| 300 | #define REG_DMAC_CHPRILVL31 (0x4100A235) /**< \brief (DMAC) Channel 31 Priority Level */
|
| 301 | #define REG_DMAC_CHEVCTRL31 (0x4100A236) /**< \brief (DMAC) Channel 31 Event Control */
|
| 302 | #define REG_DMAC_CHINTENCLR31 (0x4100A23C) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
|
| 303 | #define REG_DMAC_CHINTENSET31 (0x4100A23D) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
|
| 304 | #define REG_DMAC_CHINTFLAG31 (0x4100A23E) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
|
| 305 | #define REG_DMAC_CHSTATUS31 (0x4100A23F) /**< \brief (DMAC) Channel 31 Status */
|
| 306 | #else
|
| 307 | #define REG_DMAC_CTRL (*(RwReg16*)0x4100A000UL) /**< \brief (DMAC) Control */
|
| 308 | #define REG_DMAC_CRCCTRL (*(RwReg16*)0x4100A002UL) /**< \brief (DMAC) CRC Control */
|
| 309 | #define REG_DMAC_CRCDATAIN (*(RwReg *)0x4100A004UL) /**< \brief (DMAC) CRC Data Input */
|
| 310 | #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x4100A008UL) /**< \brief (DMAC) CRC Checksum */
|
| 311 | #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100A00CUL) /**< \brief (DMAC) CRC Status */
|
| 312 | #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100A00DUL) /**< \brief (DMAC) Debug Control */
|
| 313 | #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x4100A010UL) /**< \brief (DMAC) Software Trigger Control */
|
| 314 | #define REG_DMAC_PRICTRL0 (*(RwReg *)0x4100A014UL) /**< \brief (DMAC) Priority Control 0 */
|
| 315 | #define REG_DMAC_INTPEND (*(RwReg16*)0x4100A020UL) /**< \brief (DMAC) Interrupt Pending */
|
| 316 | #define REG_DMAC_INTSTATUS (*(RoReg *)0x4100A024UL) /**< \brief (DMAC) Interrupt Status */
|
| 317 | #define REG_DMAC_BUSYCH (*(RoReg *)0x4100A028UL) /**< \brief (DMAC) Busy Channels */
|
| 318 | #define REG_DMAC_PENDCH (*(RoReg *)0x4100A02CUL) /**< \brief (DMAC) Pending Channels */
|
| 319 | #define REG_DMAC_ACTIVE (*(RoReg *)0x4100A030UL) /**< \brief (DMAC) Active Channel and Levels */
|
| 320 | #define REG_DMAC_BASEADDR (*(RwReg *)0x4100A034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
|
| 321 | #define REG_DMAC_WRBADDR (*(RwReg *)0x4100A038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
|
| 322 | #define REG_DMAC_CHCTRLA0 (*(RwReg *)0x4100A040UL) /**< \brief (DMAC) Channel 0 Control A */
|
| 323 | #define REG_DMAC_CHCTRLB0 (*(RwReg8 *)0x4100A044UL) /**< \brief (DMAC) Channel 0 Control B */
|
| 324 | #define REG_DMAC_CHPRILVL0 (*(RwReg8 *)0x4100A045UL) /**< \brief (DMAC) Channel 0 Priority Level */
|
| 325 | #define REG_DMAC_CHEVCTRL0 (*(RwReg8 *)0x4100A046UL) /**< \brief (DMAC) Channel 0 Event Control */
|
| 326 | #define REG_DMAC_CHINTENCLR0 (*(RwReg8 *)0x4100A04CUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
|
| 327 | #define REG_DMAC_CHINTENSET0 (*(RwReg8 *)0x4100A04DUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
|
| 328 | #define REG_DMAC_CHINTFLAG0 (*(RwReg8 *)0x4100A04EUL) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
|
| 329 | #define REG_DMAC_CHSTATUS0 (*(RwReg8 *)0x4100A04FUL) /**< \brief (DMAC) Channel 0 Status */
|
| 330 | #define REG_DMAC_CHCTRLA1 (*(RwReg *)0x4100A050UL) /**< \brief (DMAC) Channel 1 Control A */
|
| 331 | #define REG_DMAC_CHCTRLB1 (*(RwReg8 *)0x4100A054UL) /**< \brief (DMAC) Channel 1 Control B */
|
| 332 | #define REG_DMAC_CHPRILVL1 (*(RwReg8 *)0x4100A055UL) /**< \brief (DMAC) Channel 1 Priority Level */
|
| 333 | #define REG_DMAC_CHEVCTRL1 (*(RwReg8 *)0x4100A056UL) /**< \brief (DMAC) Channel 1 Event Control */
|
| 334 | #define REG_DMAC_CHINTENCLR1 (*(RwReg8 *)0x4100A05CUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
|
| 335 | #define REG_DMAC_CHINTENSET1 (*(RwReg8 *)0x4100A05DUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
|
| 336 | #define REG_DMAC_CHINTFLAG1 (*(RwReg8 *)0x4100A05EUL) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
|
| 337 | #define REG_DMAC_CHSTATUS1 (*(RwReg8 *)0x4100A05FUL) /**< \brief (DMAC) Channel 1 Status */
|
| 338 | #define REG_DMAC_CHCTRLA2 (*(RwReg *)0x4100A060UL) /**< \brief (DMAC) Channel 2 Control A */
|
| 339 | #define REG_DMAC_CHCTRLB2 (*(RwReg8 *)0x4100A064UL) /**< \brief (DMAC) Channel 2 Control B */
|
| 340 | #define REG_DMAC_CHPRILVL2 (*(RwReg8 *)0x4100A065UL) /**< \brief (DMAC) Channel 2 Priority Level */
|
| 341 | #define REG_DMAC_CHEVCTRL2 (*(RwReg8 *)0x4100A066UL) /**< \brief (DMAC) Channel 2 Event Control */
|
| 342 | #define REG_DMAC_CHINTENCLR2 (*(RwReg8 *)0x4100A06CUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
|
| 343 | #define REG_DMAC_CHINTENSET2 (*(RwReg8 *)0x4100A06DUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
|
| 344 | #define REG_DMAC_CHINTFLAG2 (*(RwReg8 *)0x4100A06EUL) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
|
| 345 | #define REG_DMAC_CHSTATUS2 (*(RwReg8 *)0x4100A06FUL) /**< \brief (DMAC) Channel 2 Status */
|
| 346 | #define REG_DMAC_CHCTRLA3 (*(RwReg *)0x4100A070UL) /**< \brief (DMAC) Channel 3 Control A */
|
| 347 | #define REG_DMAC_CHCTRLB3 (*(RwReg8 *)0x4100A074UL) /**< \brief (DMAC) Channel 3 Control B */
|
| 348 | #define REG_DMAC_CHPRILVL3 (*(RwReg8 *)0x4100A075UL) /**< \brief (DMAC) Channel 3 Priority Level */
|
| 349 | #define REG_DMAC_CHEVCTRL3 (*(RwReg8 *)0x4100A076UL) /**< \brief (DMAC) Channel 3 Event Control */
|
| 350 | #define REG_DMAC_CHINTENCLR3 (*(RwReg8 *)0x4100A07CUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
|
| 351 | #define REG_DMAC_CHINTENSET3 (*(RwReg8 *)0x4100A07DUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
|
| 352 | #define REG_DMAC_CHINTFLAG3 (*(RwReg8 *)0x4100A07EUL) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
|
| 353 | #define REG_DMAC_CHSTATUS3 (*(RwReg8 *)0x4100A07FUL) /**< \brief (DMAC) Channel 3 Status */
|
| 354 | #define REG_DMAC_CHCTRLA4 (*(RwReg *)0x4100A080UL) /**< \brief (DMAC) Channel 4 Control A */
|
| 355 | #define REG_DMAC_CHCTRLB4 (*(RwReg8 *)0x4100A084UL) /**< \brief (DMAC) Channel 4 Control B */
|
| 356 | #define REG_DMAC_CHPRILVL4 (*(RwReg8 *)0x4100A085UL) /**< \brief (DMAC) Channel 4 Priority Level */
|
| 357 | #define REG_DMAC_CHEVCTRL4 (*(RwReg8 *)0x4100A086UL) /**< \brief (DMAC) Channel 4 Event Control */
|
| 358 | #define REG_DMAC_CHINTENCLR4 (*(RwReg8 *)0x4100A08CUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
|
| 359 | #define REG_DMAC_CHINTENSET4 (*(RwReg8 *)0x4100A08DUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
|
| 360 | #define REG_DMAC_CHINTFLAG4 (*(RwReg8 *)0x4100A08EUL) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
|
| 361 | #define REG_DMAC_CHSTATUS4 (*(RwReg8 *)0x4100A08FUL) /**< \brief (DMAC) Channel 4 Status */
|
| 362 | #define REG_DMAC_CHCTRLA5 (*(RwReg *)0x4100A090UL) /**< \brief (DMAC) Channel 5 Control A */
|
| 363 | #define REG_DMAC_CHCTRLB5 (*(RwReg8 *)0x4100A094UL) /**< \brief (DMAC) Channel 5 Control B */
|
| 364 | #define REG_DMAC_CHPRILVL5 (*(RwReg8 *)0x4100A095UL) /**< \brief (DMAC) Channel 5 Priority Level */
|
| 365 | #define REG_DMAC_CHEVCTRL5 (*(RwReg8 *)0x4100A096UL) /**< \brief (DMAC) Channel 5 Event Control */
|
| 366 | #define REG_DMAC_CHINTENCLR5 (*(RwReg8 *)0x4100A09CUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
|
| 367 | #define REG_DMAC_CHINTENSET5 (*(RwReg8 *)0x4100A09DUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
|
| 368 | #define REG_DMAC_CHINTFLAG5 (*(RwReg8 *)0x4100A09EUL) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
|
| 369 | #define REG_DMAC_CHSTATUS5 (*(RwReg8 *)0x4100A09FUL) /**< \brief (DMAC) Channel 5 Status */
|
| 370 | #define REG_DMAC_CHCTRLA6 (*(RwReg *)0x4100A0A0UL) /**< \brief (DMAC) Channel 6 Control A */
|
| 371 | #define REG_DMAC_CHCTRLB6 (*(RwReg8 *)0x4100A0A4UL) /**< \brief (DMAC) Channel 6 Control B */
|
| 372 | #define REG_DMAC_CHPRILVL6 (*(RwReg8 *)0x4100A0A5UL) /**< \brief (DMAC) Channel 6 Priority Level */
|
| 373 | #define REG_DMAC_CHEVCTRL6 (*(RwReg8 *)0x4100A0A6UL) /**< \brief (DMAC) Channel 6 Event Control */
|
| 374 | #define REG_DMAC_CHINTENCLR6 (*(RwReg8 *)0x4100A0ACUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
|
| 375 | #define REG_DMAC_CHINTENSET6 (*(RwReg8 *)0x4100A0ADUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
|
| 376 | #define REG_DMAC_CHINTFLAG6 (*(RwReg8 *)0x4100A0AEUL) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
|
| 377 | #define REG_DMAC_CHSTATUS6 (*(RwReg8 *)0x4100A0AFUL) /**< \brief (DMAC) Channel 6 Status */
|
| 378 | #define REG_DMAC_CHCTRLA7 (*(RwReg *)0x4100A0B0UL) /**< \brief (DMAC) Channel 7 Control A */
|
| 379 | #define REG_DMAC_CHCTRLB7 (*(RwReg8 *)0x4100A0B4UL) /**< \brief (DMAC) Channel 7 Control B */
|
| 380 | #define REG_DMAC_CHPRILVL7 (*(RwReg8 *)0x4100A0B5UL) /**< \brief (DMAC) Channel 7 Priority Level */
|
| 381 | #define REG_DMAC_CHEVCTRL7 (*(RwReg8 *)0x4100A0B6UL) /**< \brief (DMAC) Channel 7 Event Control */
|
| 382 | #define REG_DMAC_CHINTENCLR7 (*(RwReg8 *)0x4100A0BCUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
|
| 383 | #define REG_DMAC_CHINTENSET7 (*(RwReg8 *)0x4100A0BDUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
|
| 384 | #define REG_DMAC_CHINTFLAG7 (*(RwReg8 *)0x4100A0BEUL) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
|
| 385 | #define REG_DMAC_CHSTATUS7 (*(RwReg8 *)0x4100A0BFUL) /**< \brief (DMAC) Channel 7 Status */
|
| 386 | #define REG_DMAC_CHCTRLA8 (*(RwReg *)0x4100A0C0UL) /**< \brief (DMAC) Channel 8 Control A */
|
| 387 | #define REG_DMAC_CHCTRLB8 (*(RwReg8 *)0x4100A0C4UL) /**< \brief (DMAC) Channel 8 Control B */
|
| 388 | #define REG_DMAC_CHPRILVL8 (*(RwReg8 *)0x4100A0C5UL) /**< \brief (DMAC) Channel 8 Priority Level */
|
| 389 | #define REG_DMAC_CHEVCTRL8 (*(RwReg8 *)0x4100A0C6UL) /**< \brief (DMAC) Channel 8 Event Control */
|
| 390 | #define REG_DMAC_CHINTENCLR8 (*(RwReg8 *)0x4100A0CCUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
|
| 391 | #define REG_DMAC_CHINTENSET8 (*(RwReg8 *)0x4100A0CDUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
|
| 392 | #define REG_DMAC_CHINTFLAG8 (*(RwReg8 *)0x4100A0CEUL) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
|
| 393 | #define REG_DMAC_CHSTATUS8 (*(RwReg8 *)0x4100A0CFUL) /**< \brief (DMAC) Channel 8 Status */
|
| 394 | #define REG_DMAC_CHCTRLA9 (*(RwReg *)0x4100A0D0UL) /**< \brief (DMAC) Channel 9 Control A */
|
| 395 | #define REG_DMAC_CHCTRLB9 (*(RwReg8 *)0x4100A0D4UL) /**< \brief (DMAC) Channel 9 Control B */
|
| 396 | #define REG_DMAC_CHPRILVL9 (*(RwReg8 *)0x4100A0D5UL) /**< \brief (DMAC) Channel 9 Priority Level */
|
| 397 | #define REG_DMAC_CHEVCTRL9 (*(RwReg8 *)0x4100A0D6UL) /**< \brief (DMAC) Channel 9 Event Control */
|
| 398 | #define REG_DMAC_CHINTENCLR9 (*(RwReg8 *)0x4100A0DCUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
|
| 399 | #define REG_DMAC_CHINTENSET9 (*(RwReg8 *)0x4100A0DDUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
|
| 400 | #define REG_DMAC_CHINTFLAG9 (*(RwReg8 *)0x4100A0DEUL) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
|
| 401 | #define REG_DMAC_CHSTATUS9 (*(RwReg8 *)0x4100A0DFUL) /**< \brief (DMAC) Channel 9 Status */
|
| 402 | #define REG_DMAC_CHCTRLA10 (*(RwReg *)0x4100A0E0UL) /**< \brief (DMAC) Channel 10 Control A */
|
| 403 | #define REG_DMAC_CHCTRLB10 (*(RwReg8 *)0x4100A0E4UL) /**< \brief (DMAC) Channel 10 Control B */
|
| 404 | #define REG_DMAC_CHPRILVL10 (*(RwReg8 *)0x4100A0E5UL) /**< \brief (DMAC) Channel 10 Priority Level */
|
| 405 | #define REG_DMAC_CHEVCTRL10 (*(RwReg8 *)0x4100A0E6UL) /**< \brief (DMAC) Channel 10 Event Control */
|
| 406 | #define REG_DMAC_CHINTENCLR10 (*(RwReg8 *)0x4100A0ECUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
|
| 407 | #define REG_DMAC_CHINTENSET10 (*(RwReg8 *)0x4100A0EDUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
|
| 408 | #define REG_DMAC_CHINTFLAG10 (*(RwReg8 *)0x4100A0EEUL) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
|
| 409 | #define REG_DMAC_CHSTATUS10 (*(RwReg8 *)0x4100A0EFUL) /**< \brief (DMAC) Channel 10 Status */
|
| 410 | #define REG_DMAC_CHCTRLA11 (*(RwReg *)0x4100A0F0UL) /**< \brief (DMAC) Channel 11 Control A */
|
| 411 | #define REG_DMAC_CHCTRLB11 (*(RwReg8 *)0x4100A0F4UL) /**< \brief (DMAC) Channel 11 Control B */
|
| 412 | #define REG_DMAC_CHPRILVL11 (*(RwReg8 *)0x4100A0F5UL) /**< \brief (DMAC) Channel 11 Priority Level */
|
| 413 | #define REG_DMAC_CHEVCTRL11 (*(RwReg8 *)0x4100A0F6UL) /**< \brief (DMAC) Channel 11 Event Control */
|
| 414 | #define REG_DMAC_CHINTENCLR11 (*(RwReg8 *)0x4100A0FCUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
|
| 415 | #define REG_DMAC_CHINTENSET11 (*(RwReg8 *)0x4100A0FDUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
|
| 416 | #define REG_DMAC_CHINTFLAG11 (*(RwReg8 *)0x4100A0FEUL) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
|
| 417 | #define REG_DMAC_CHSTATUS11 (*(RwReg8 *)0x4100A0FFUL) /**< \brief (DMAC) Channel 11 Status */
|
| 418 | #define REG_DMAC_CHCTRLA12 (*(RwReg *)0x4100A100UL) /**< \brief (DMAC) Channel 12 Control A */
|
| 419 | #define REG_DMAC_CHCTRLB12 (*(RwReg8 *)0x4100A104UL) /**< \brief (DMAC) Channel 12 Control B */
|
| 420 | #define REG_DMAC_CHPRILVL12 (*(RwReg8 *)0x4100A105UL) /**< \brief (DMAC) Channel 12 Priority Level */
|
| 421 | #define REG_DMAC_CHEVCTRL12 (*(RwReg8 *)0x4100A106UL) /**< \brief (DMAC) Channel 12 Event Control */
|
| 422 | #define REG_DMAC_CHINTENCLR12 (*(RwReg8 *)0x4100A10CUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
|
| 423 | #define REG_DMAC_CHINTENSET12 (*(RwReg8 *)0x4100A10DUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
|
| 424 | #define REG_DMAC_CHINTFLAG12 (*(RwReg8 *)0x4100A10EUL) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
|
| 425 | #define REG_DMAC_CHSTATUS12 (*(RwReg8 *)0x4100A10FUL) /**< \brief (DMAC) Channel 12 Status */
|
| 426 | #define REG_DMAC_CHCTRLA13 (*(RwReg *)0x4100A110UL) /**< \brief (DMAC) Channel 13 Control A */
|
| 427 | #define REG_DMAC_CHCTRLB13 (*(RwReg8 *)0x4100A114UL) /**< \brief (DMAC) Channel 13 Control B */
|
| 428 | #define REG_DMAC_CHPRILVL13 (*(RwReg8 *)0x4100A115UL) /**< \brief (DMAC) Channel 13 Priority Level */
|
| 429 | #define REG_DMAC_CHEVCTRL13 (*(RwReg8 *)0x4100A116UL) /**< \brief (DMAC) Channel 13 Event Control */
|
| 430 | #define REG_DMAC_CHINTENCLR13 (*(RwReg8 *)0x4100A11CUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
|
| 431 | #define REG_DMAC_CHINTENSET13 (*(RwReg8 *)0x4100A11DUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
|
| 432 | #define REG_DMAC_CHINTFLAG13 (*(RwReg8 *)0x4100A11EUL) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
|
| 433 | #define REG_DMAC_CHSTATUS13 (*(RwReg8 *)0x4100A11FUL) /**< \brief (DMAC) Channel 13 Status */
|
| 434 | #define REG_DMAC_CHCTRLA14 (*(RwReg *)0x4100A120UL) /**< \brief (DMAC) Channel 14 Control A */
|
| 435 | #define REG_DMAC_CHCTRLB14 (*(RwReg8 *)0x4100A124UL) /**< \brief (DMAC) Channel 14 Control B */
|
| 436 | #define REG_DMAC_CHPRILVL14 (*(RwReg8 *)0x4100A125UL) /**< \brief (DMAC) Channel 14 Priority Level */
|
| 437 | #define REG_DMAC_CHEVCTRL14 (*(RwReg8 *)0x4100A126UL) /**< \brief (DMAC) Channel 14 Event Control */
|
| 438 | #define REG_DMAC_CHINTENCLR14 (*(RwReg8 *)0x4100A12CUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
|
| 439 | #define REG_DMAC_CHINTENSET14 (*(RwReg8 *)0x4100A12DUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
|
| 440 | #define REG_DMAC_CHINTFLAG14 (*(RwReg8 *)0x4100A12EUL) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
|
| 441 | #define REG_DMAC_CHSTATUS14 (*(RwReg8 *)0x4100A12FUL) /**< \brief (DMAC) Channel 14 Status */
|
| 442 | #define REG_DMAC_CHCTRLA15 (*(RwReg *)0x4100A130UL) /**< \brief (DMAC) Channel 15 Control A */
|
| 443 | #define REG_DMAC_CHCTRLB15 (*(RwReg8 *)0x4100A134UL) /**< \brief (DMAC) Channel 15 Control B */
|
| 444 | #define REG_DMAC_CHPRILVL15 (*(RwReg8 *)0x4100A135UL) /**< \brief (DMAC) Channel 15 Priority Level */
|
| 445 | #define REG_DMAC_CHEVCTRL15 (*(RwReg8 *)0x4100A136UL) /**< \brief (DMAC) Channel 15 Event Control */
|
| 446 | #define REG_DMAC_CHINTENCLR15 (*(RwReg8 *)0x4100A13CUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
|
| 447 | #define REG_DMAC_CHINTENSET15 (*(RwReg8 *)0x4100A13DUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
|
| 448 | #define REG_DMAC_CHINTFLAG15 (*(RwReg8 *)0x4100A13EUL) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
|
| 449 | #define REG_DMAC_CHSTATUS15 (*(RwReg8 *)0x4100A13FUL) /**< \brief (DMAC) Channel 15 Status */
|
| 450 | #define REG_DMAC_CHCTRLA16 (*(RwReg *)0x4100A140UL) /**< \brief (DMAC) Channel 16 Control A */
|
| 451 | #define REG_DMAC_CHCTRLB16 (*(RwReg8 *)0x4100A144UL) /**< \brief (DMAC) Channel 16 Control B */
|
| 452 | #define REG_DMAC_CHPRILVL16 (*(RwReg8 *)0x4100A145UL) /**< \brief (DMAC) Channel 16 Priority Level */
|
| 453 | #define REG_DMAC_CHEVCTRL16 (*(RwReg8 *)0x4100A146UL) /**< \brief (DMAC) Channel 16 Event Control */
|
| 454 | #define REG_DMAC_CHINTENCLR16 (*(RwReg8 *)0x4100A14CUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
|
| 455 | #define REG_DMAC_CHINTENSET16 (*(RwReg8 *)0x4100A14DUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
|
| 456 | #define REG_DMAC_CHINTFLAG16 (*(RwReg8 *)0x4100A14EUL) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
|
| 457 | #define REG_DMAC_CHSTATUS16 (*(RwReg8 *)0x4100A14FUL) /**< \brief (DMAC) Channel 16 Status */
|
| 458 | #define REG_DMAC_CHCTRLA17 (*(RwReg *)0x4100A150UL) /**< \brief (DMAC) Channel 17 Control A */
|
| 459 | #define REG_DMAC_CHCTRLB17 (*(RwReg8 *)0x4100A154UL) /**< \brief (DMAC) Channel 17 Control B */
|
| 460 | #define REG_DMAC_CHPRILVL17 (*(RwReg8 *)0x4100A155UL) /**< \brief (DMAC) Channel 17 Priority Level */
|
| 461 | #define REG_DMAC_CHEVCTRL17 (*(RwReg8 *)0x4100A156UL) /**< \brief (DMAC) Channel 17 Event Control */
|
| 462 | #define REG_DMAC_CHINTENCLR17 (*(RwReg8 *)0x4100A15CUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
|
| 463 | #define REG_DMAC_CHINTENSET17 (*(RwReg8 *)0x4100A15DUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
|
| 464 | #define REG_DMAC_CHINTFLAG17 (*(RwReg8 *)0x4100A15EUL) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
|
| 465 | #define REG_DMAC_CHSTATUS17 (*(RwReg8 *)0x4100A15FUL) /**< \brief (DMAC) Channel 17 Status */
|
| 466 | #define REG_DMAC_CHCTRLA18 (*(RwReg *)0x4100A160UL) /**< \brief (DMAC) Channel 18 Control A */
|
| 467 | #define REG_DMAC_CHCTRLB18 (*(RwReg8 *)0x4100A164UL) /**< \brief (DMAC) Channel 18 Control B */
|
| 468 | #define REG_DMAC_CHPRILVL18 (*(RwReg8 *)0x4100A165UL) /**< \brief (DMAC) Channel 18 Priority Level */
|
| 469 | #define REG_DMAC_CHEVCTRL18 (*(RwReg8 *)0x4100A166UL) /**< \brief (DMAC) Channel 18 Event Control */
|
| 470 | #define REG_DMAC_CHINTENCLR18 (*(RwReg8 *)0x4100A16CUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
|
| 471 | #define REG_DMAC_CHINTENSET18 (*(RwReg8 *)0x4100A16DUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
|
| 472 | #define REG_DMAC_CHINTFLAG18 (*(RwReg8 *)0x4100A16EUL) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
|
| 473 | #define REG_DMAC_CHSTATUS18 (*(RwReg8 *)0x4100A16FUL) /**< \brief (DMAC) Channel 18 Status */
|
| 474 | #define REG_DMAC_CHCTRLA19 (*(RwReg *)0x4100A170UL) /**< \brief (DMAC) Channel 19 Control A */
|
| 475 | #define REG_DMAC_CHCTRLB19 (*(RwReg8 *)0x4100A174UL) /**< \brief (DMAC) Channel 19 Control B */
|
| 476 | #define REG_DMAC_CHPRILVL19 (*(RwReg8 *)0x4100A175UL) /**< \brief (DMAC) Channel 19 Priority Level */
|
| 477 | #define REG_DMAC_CHEVCTRL19 (*(RwReg8 *)0x4100A176UL) /**< \brief (DMAC) Channel 19 Event Control */
|
| 478 | #define REG_DMAC_CHINTENCLR19 (*(RwReg8 *)0x4100A17CUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
|
| 479 | #define REG_DMAC_CHINTENSET19 (*(RwReg8 *)0x4100A17DUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
|
| 480 | #define REG_DMAC_CHINTFLAG19 (*(RwReg8 *)0x4100A17EUL) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
|
| 481 | #define REG_DMAC_CHSTATUS19 (*(RwReg8 *)0x4100A17FUL) /**< \brief (DMAC) Channel 19 Status */
|
| 482 | #define REG_DMAC_CHCTRLA20 (*(RwReg *)0x4100A180UL) /**< \brief (DMAC) Channel 20 Control A */
|
| 483 | #define REG_DMAC_CHCTRLB20 (*(RwReg8 *)0x4100A184UL) /**< \brief (DMAC) Channel 20 Control B */
|
| 484 | #define REG_DMAC_CHPRILVL20 (*(RwReg8 *)0x4100A185UL) /**< \brief (DMAC) Channel 20 Priority Level */
|
| 485 | #define REG_DMAC_CHEVCTRL20 (*(RwReg8 *)0x4100A186UL) /**< \brief (DMAC) Channel 20 Event Control */
|
| 486 | #define REG_DMAC_CHINTENCLR20 (*(RwReg8 *)0x4100A18CUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
|
| 487 | #define REG_DMAC_CHINTENSET20 (*(RwReg8 *)0x4100A18DUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
|
| 488 | #define REG_DMAC_CHINTFLAG20 (*(RwReg8 *)0x4100A18EUL) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
|
| 489 | #define REG_DMAC_CHSTATUS20 (*(RwReg8 *)0x4100A18FUL) /**< \brief (DMAC) Channel 20 Status */
|
| 490 | #define REG_DMAC_CHCTRLA21 (*(RwReg *)0x4100A190UL) /**< \brief (DMAC) Channel 21 Control A */
|
| 491 | #define REG_DMAC_CHCTRLB21 (*(RwReg8 *)0x4100A194UL) /**< \brief (DMAC) Channel 21 Control B */
|
| 492 | #define REG_DMAC_CHPRILVL21 (*(RwReg8 *)0x4100A195UL) /**< \brief (DMAC) Channel 21 Priority Level */
|
| 493 | #define REG_DMAC_CHEVCTRL21 (*(RwReg8 *)0x4100A196UL) /**< \brief (DMAC) Channel 21 Event Control */
|
| 494 | #define REG_DMAC_CHINTENCLR21 (*(RwReg8 *)0x4100A19CUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
|
| 495 | #define REG_DMAC_CHINTENSET21 (*(RwReg8 *)0x4100A19DUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
|
| 496 | #define REG_DMAC_CHINTFLAG21 (*(RwReg8 *)0x4100A19EUL) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
|
| 497 | #define REG_DMAC_CHSTATUS21 (*(RwReg8 *)0x4100A19FUL) /**< \brief (DMAC) Channel 21 Status */
|
| 498 | #define REG_DMAC_CHCTRLA22 (*(RwReg *)0x4100A1A0UL) /**< \brief (DMAC) Channel 22 Control A */
|
| 499 | #define REG_DMAC_CHCTRLB22 (*(RwReg8 *)0x4100A1A4UL) /**< \brief (DMAC) Channel 22 Control B */
|
| 500 | #define REG_DMAC_CHPRILVL22 (*(RwReg8 *)0x4100A1A5UL) /**< \brief (DMAC) Channel 22 Priority Level */
|
| 501 | #define REG_DMAC_CHEVCTRL22 (*(RwReg8 *)0x4100A1A6UL) /**< \brief (DMAC) Channel 22 Event Control */
|
| 502 | #define REG_DMAC_CHINTENCLR22 (*(RwReg8 *)0x4100A1ACUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
|
| 503 | #define REG_DMAC_CHINTENSET22 (*(RwReg8 *)0x4100A1ADUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
|
| 504 | #define REG_DMAC_CHINTFLAG22 (*(RwReg8 *)0x4100A1AEUL) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
|
| 505 | #define REG_DMAC_CHSTATUS22 (*(RwReg8 *)0x4100A1AFUL) /**< \brief (DMAC) Channel 22 Status */
|
| 506 | #define REG_DMAC_CHCTRLA23 (*(RwReg *)0x4100A1B0UL) /**< \brief (DMAC) Channel 23 Control A */
|
| 507 | #define REG_DMAC_CHCTRLB23 (*(RwReg8 *)0x4100A1B4UL) /**< \brief (DMAC) Channel 23 Control B */
|
| 508 | #define REG_DMAC_CHPRILVL23 (*(RwReg8 *)0x4100A1B5UL) /**< \brief (DMAC) Channel 23 Priority Level */
|
| 509 | #define REG_DMAC_CHEVCTRL23 (*(RwReg8 *)0x4100A1B6UL) /**< \brief (DMAC) Channel 23 Event Control */
|
| 510 | #define REG_DMAC_CHINTENCLR23 (*(RwReg8 *)0x4100A1BCUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
|
| 511 | #define REG_DMAC_CHINTENSET23 (*(RwReg8 *)0x4100A1BDUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
|
| 512 | #define REG_DMAC_CHINTFLAG23 (*(RwReg8 *)0x4100A1BEUL) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
|
| 513 | #define REG_DMAC_CHSTATUS23 (*(RwReg8 *)0x4100A1BFUL) /**< \brief (DMAC) Channel 23 Status */
|
| 514 | #define REG_DMAC_CHCTRLA24 (*(RwReg *)0x4100A1C0UL) /**< \brief (DMAC) Channel 24 Control A */
|
| 515 | #define REG_DMAC_CHCTRLB24 (*(RwReg8 *)0x4100A1C4UL) /**< \brief (DMAC) Channel 24 Control B */
|
| 516 | #define REG_DMAC_CHPRILVL24 (*(RwReg8 *)0x4100A1C5UL) /**< \brief (DMAC) Channel 24 Priority Level */
|
| 517 | #define REG_DMAC_CHEVCTRL24 (*(RwReg8 *)0x4100A1C6UL) /**< \brief (DMAC) Channel 24 Event Control */
|
| 518 | #define REG_DMAC_CHINTENCLR24 (*(RwReg8 *)0x4100A1CCUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
|
| 519 | #define REG_DMAC_CHINTENSET24 (*(RwReg8 *)0x4100A1CDUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
|
| 520 | #define REG_DMAC_CHINTFLAG24 (*(RwReg8 *)0x4100A1CEUL) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
|
| 521 | #define REG_DMAC_CHSTATUS24 (*(RwReg8 *)0x4100A1CFUL) /**< \brief (DMAC) Channel 24 Status */
|
| 522 | #define REG_DMAC_CHCTRLA25 (*(RwReg *)0x4100A1D0UL) /**< \brief (DMAC) Channel 25 Control A */
|
| 523 | #define REG_DMAC_CHCTRLB25 (*(RwReg8 *)0x4100A1D4UL) /**< \brief (DMAC) Channel 25 Control B */
|
| 524 | #define REG_DMAC_CHPRILVL25 (*(RwReg8 *)0x4100A1D5UL) /**< \brief (DMAC) Channel 25 Priority Level */
|
| 525 | #define REG_DMAC_CHEVCTRL25 (*(RwReg8 *)0x4100A1D6UL) /**< \brief (DMAC) Channel 25 Event Control */
|
| 526 | #define REG_DMAC_CHINTENCLR25 (*(RwReg8 *)0x4100A1DCUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
|
| 527 | #define REG_DMAC_CHINTENSET25 (*(RwReg8 *)0x4100A1DDUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
|
| 528 | #define REG_DMAC_CHINTFLAG25 (*(RwReg8 *)0x4100A1DEUL) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
|
| 529 | #define REG_DMAC_CHSTATUS25 (*(RwReg8 *)0x4100A1DFUL) /**< \brief (DMAC) Channel 25 Status */
|
| 530 | #define REG_DMAC_CHCTRLA26 (*(RwReg *)0x4100A1E0UL) /**< \brief (DMAC) Channel 26 Control A */
|
| 531 | #define REG_DMAC_CHCTRLB26 (*(RwReg8 *)0x4100A1E4UL) /**< \brief (DMAC) Channel 26 Control B */
|
| 532 | #define REG_DMAC_CHPRILVL26 (*(RwReg8 *)0x4100A1E5UL) /**< \brief (DMAC) Channel 26 Priority Level */
|
| 533 | #define REG_DMAC_CHEVCTRL26 (*(RwReg8 *)0x4100A1E6UL) /**< \brief (DMAC) Channel 26 Event Control */
|
| 534 | #define REG_DMAC_CHINTENCLR26 (*(RwReg8 *)0x4100A1ECUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
|
| 535 | #define REG_DMAC_CHINTENSET26 (*(RwReg8 *)0x4100A1EDUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
|
| 536 | #define REG_DMAC_CHINTFLAG26 (*(RwReg8 *)0x4100A1EEUL) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
|
| 537 | #define REG_DMAC_CHSTATUS26 (*(RwReg8 *)0x4100A1EFUL) /**< \brief (DMAC) Channel 26 Status */
|
| 538 | #define REG_DMAC_CHCTRLA27 (*(RwReg *)0x4100A1F0UL) /**< \brief (DMAC) Channel 27 Control A */
|
| 539 | #define REG_DMAC_CHCTRLB27 (*(RwReg8 *)0x4100A1F4UL) /**< \brief (DMAC) Channel 27 Control B */
|
| 540 | #define REG_DMAC_CHPRILVL27 (*(RwReg8 *)0x4100A1F5UL) /**< \brief (DMAC) Channel 27 Priority Level */
|
| 541 | #define REG_DMAC_CHEVCTRL27 (*(RwReg8 *)0x4100A1F6UL) /**< \brief (DMAC) Channel 27 Event Control */
|
| 542 | #define REG_DMAC_CHINTENCLR27 (*(RwReg8 *)0x4100A1FCUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
|
| 543 | #define REG_DMAC_CHINTENSET27 (*(RwReg8 *)0x4100A1FDUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
|
| 544 | #define REG_DMAC_CHINTFLAG27 (*(RwReg8 *)0x4100A1FEUL) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
|
| 545 | #define REG_DMAC_CHSTATUS27 (*(RwReg8 *)0x4100A1FFUL) /**< \brief (DMAC) Channel 27 Status */
|
| 546 | #define REG_DMAC_CHCTRLA28 (*(RwReg *)0x4100A200UL) /**< \brief (DMAC) Channel 28 Control A */
|
| 547 | #define REG_DMAC_CHCTRLB28 (*(RwReg8 *)0x4100A204UL) /**< \brief (DMAC) Channel 28 Control B */
|
| 548 | #define REG_DMAC_CHPRILVL28 (*(RwReg8 *)0x4100A205UL) /**< \brief (DMAC) Channel 28 Priority Level */
|
| 549 | #define REG_DMAC_CHEVCTRL28 (*(RwReg8 *)0x4100A206UL) /**< \brief (DMAC) Channel 28 Event Control */
|
| 550 | #define REG_DMAC_CHINTENCLR28 (*(RwReg8 *)0x4100A20CUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
|
| 551 | #define REG_DMAC_CHINTENSET28 (*(RwReg8 *)0x4100A20DUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
|
| 552 | #define REG_DMAC_CHINTFLAG28 (*(RwReg8 *)0x4100A20EUL) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
|
| 553 | #define REG_DMAC_CHSTATUS28 (*(RwReg8 *)0x4100A20FUL) /**< \brief (DMAC) Channel 28 Status */
|
| 554 | #define REG_DMAC_CHCTRLA29 (*(RwReg *)0x4100A210UL) /**< \brief (DMAC) Channel 29 Control A */
|
| 555 | #define REG_DMAC_CHCTRLB29 (*(RwReg8 *)0x4100A214UL) /**< \brief (DMAC) Channel 29 Control B */
|
| 556 | #define REG_DMAC_CHPRILVL29 (*(RwReg8 *)0x4100A215UL) /**< \brief (DMAC) Channel 29 Priority Level */
|
| 557 | #define REG_DMAC_CHEVCTRL29 (*(RwReg8 *)0x4100A216UL) /**< \brief (DMAC) Channel 29 Event Control */
|
| 558 | #define REG_DMAC_CHINTENCLR29 (*(RwReg8 *)0x4100A21CUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
|
| 559 | #define REG_DMAC_CHINTENSET29 (*(RwReg8 *)0x4100A21DUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
|
| 560 | #define REG_DMAC_CHINTFLAG29 (*(RwReg8 *)0x4100A21EUL) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
|
| 561 | #define REG_DMAC_CHSTATUS29 (*(RwReg8 *)0x4100A21FUL) /**< \brief (DMAC) Channel 29 Status */
|
| 562 | #define REG_DMAC_CHCTRLA30 (*(RwReg *)0x4100A220UL) /**< \brief (DMAC) Channel 30 Control A */
|
| 563 | #define REG_DMAC_CHCTRLB30 (*(RwReg8 *)0x4100A224UL) /**< \brief (DMAC) Channel 30 Control B */
|
| 564 | #define REG_DMAC_CHPRILVL30 (*(RwReg8 *)0x4100A225UL) /**< \brief (DMAC) Channel 30 Priority Level */
|
| 565 | #define REG_DMAC_CHEVCTRL30 (*(RwReg8 *)0x4100A226UL) /**< \brief (DMAC) Channel 30 Event Control */
|
| 566 | #define REG_DMAC_CHINTENCLR30 (*(RwReg8 *)0x4100A22CUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
|
| 567 | #define REG_DMAC_CHINTENSET30 (*(RwReg8 *)0x4100A22DUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
|
| 568 | #define REG_DMAC_CHINTFLAG30 (*(RwReg8 *)0x4100A22EUL) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
|
| 569 | #define REG_DMAC_CHSTATUS30 (*(RwReg8 *)0x4100A22FUL) /**< \brief (DMAC) Channel 30 Status */
|
| 570 | #define REG_DMAC_CHCTRLA31 (*(RwReg *)0x4100A230UL) /**< \brief (DMAC) Channel 31 Control A */
|
| 571 | #define REG_DMAC_CHCTRLB31 (*(RwReg8 *)0x4100A234UL) /**< \brief (DMAC) Channel 31 Control B */
|
| 572 | #define REG_DMAC_CHPRILVL31 (*(RwReg8 *)0x4100A235UL) /**< \brief (DMAC) Channel 31 Priority Level */
|
| 573 | #define REG_DMAC_CHEVCTRL31 (*(RwReg8 *)0x4100A236UL) /**< \brief (DMAC) Channel 31 Event Control */
|
| 574 | #define REG_DMAC_CHINTENCLR31 (*(RwReg8 *)0x4100A23CUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
|
| 575 | #define REG_DMAC_CHINTENSET31 (*(RwReg8 *)0x4100A23DUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
|
| 576 | #define REG_DMAC_CHINTFLAG31 (*(RwReg8 *)0x4100A23EUL) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
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| 577 | #define REG_DMAC_CHSTATUS31 (*(RwReg8 *)0x4100A23FUL) /**< \brief (DMAC) Channel 31 Status */
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| 578 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 579 |
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| 580 | /* ========== Instance parameters for DMAC peripheral ========== */
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| 581 | #define DMAC_BURST 1 // 0: no burst support; 1: burst support
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| 582 | #define DMAC_CH_BITS 5 // Number of bits to select channel
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| 583 | #define DMAC_CH_NUM 32 // Number of channels
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| 584 | #define DMAC_CLK_AHB_ID 9 // AHB clock index
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| 585 | #define DMAC_EVIN_NUM 8 // Number of input events
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| 586 | #define DMAC_EVOUT_NUM 4 // Number of output events
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| 587 | #define DMAC_FIFO_SIZE 16 // FIFO size for burst mode.
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| 588 | #define DMAC_LVL_BITS 2 // Number of bits to select level priority
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| 589 | #define DMAC_LVL_NUM 4 // Enable priority level number
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| 590 | #define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
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| 591 | #define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
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| 592 | #define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
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| 593 | #define DMAC_TRIG_BITS 7 // Number of bits to select trigger source
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| 594 | #define DMAC_TRIG_NUM 85 // Number of peripheral triggers
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| 595 |
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| 596 | #endif /* _SAME54_DMAC_INSTANCE_ */
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