| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
|
| 2 | * \file
|
| 3 | *
|
| 4 | * \brief Instance description for CCL
|
| 5 | *
|
| 6 | * Copyright (c) 2019 Microchip Technology Inc.
|
| 7 | *
|
| 8 | * \asf_license_start
|
| 9 | *
|
| 10 | * \page License
|
| 11 | *
|
| 12 | * SPDX-License-Identifier: Apache-2.0
|
| 13 | *
|
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
|
| 15 | * not use this file except in compliance with the License.
|
| 16 | * You may obtain a copy of the Licence at
|
| 17 | *
|
| 18 | * http://www.apache.org/licenses/LICENSE-2.0
|
| 19 | *
|
| 20 | * Unless required by applicable law or agreed to in writing, software
|
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
| 23 | * See the License for the specific language governing permissions and
|
| 24 | * limitations under the License.
|
| 25 | *
|
| 26 | * \asf_license_stop
|
| 27 | *
|
| 28 | */
|
| 29 |
|
| 30 | #ifndef _SAME54_CCL_INSTANCE_
|
| 31 | #define _SAME54_CCL_INSTANCE_
|
| 32 |
|
| 33 | /* ========== Register definition for CCL peripheral ========== */
|
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 35 | #define REG_CCL_CTRL (0x42003800) /**< \brief (CCL) Control */
|
| 36 | #define REG_CCL_SEQCTRL0 (0x42003804) /**< \brief (CCL) SEQ Control x 0 */
|
| 37 | #define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */
|
| 38 | #define REG_CCL_LUTCTRL0 (0x42003808) /**< \brief (CCL) LUT Control x 0 */
|
| 39 | #define REG_CCL_LUTCTRL1 (0x4200380C) /**< \brief (CCL) LUT Control x 1 */
|
| 40 | #define REG_CCL_LUTCTRL2 (0x42003810) /**< \brief (CCL) LUT Control x 2 */
|
| 41 | #define REG_CCL_LUTCTRL3 (0x42003814) /**< \brief (CCL) LUT Control x 3 */
|
| 42 | #else
|
| 43 | #define REG_CCL_CTRL (*(RwReg8 *)0x42003800UL) /**< \brief (CCL) Control */
|
| 44 | #define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42003804UL) /**< \brief (CCL) SEQ Control x 0 */
|
| 45 | #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */
|
| 46 | #define REG_CCL_LUTCTRL0 (*(RwReg *)0x42003808UL) /**< \brief (CCL) LUT Control x 0 */
|
| 47 | #define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200380CUL) /**< \brief (CCL) LUT Control x 1 */
|
| 48 | #define REG_CCL_LUTCTRL2 (*(RwReg *)0x42003810UL) /**< \brief (CCL) LUT Control x 2 */
|
| 49 | #define REG_CCL_LUTCTRL3 (*(RwReg *)0x42003814UL) /**< \brief (CCL) LUT Control x 3 */
|
| 50 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 51 |
|
| 52 | /* ========== Instance parameters for CCL peripheral ========== */
|
| 53 | #define CCL_GCLK_ID 33 // GCLK index for CCL
|
| 54 | #define CCL_LUT_NUM 4 // Number of LUT in a CCL
|
| 55 | #define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
|
| 56 |
|
| 57 | #endif /* _SAME54_CCL_INSTANCE_ */
|