| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for ADC1
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_ADC1_INSTANCE_
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| 31 | #define _SAME54_ADC1_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for ADC1 peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_ADC1_CTRLA (0x43002000) /**< \brief (ADC1) Control A */
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| 36 | #define REG_ADC1_EVCTRL (0x43002002) /**< \brief (ADC1) Event Control */
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| 37 | #define REG_ADC1_DBGCTRL (0x43002003) /**< \brief (ADC1) Debug Control */
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| 38 | #define REG_ADC1_INPUTCTRL (0x43002004) /**< \brief (ADC1) Input Control */
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| 39 | #define REG_ADC1_CTRLB (0x43002006) /**< \brief (ADC1) Control B */
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| 40 | #define REG_ADC1_REFCTRL (0x43002008) /**< \brief (ADC1) Reference Control */
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| 41 | #define REG_ADC1_AVGCTRL (0x4300200A) /**< \brief (ADC1) Average Control */
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| 42 | #define REG_ADC1_SAMPCTRL (0x4300200B) /**< \brief (ADC1) Sample Time Control */
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| 43 | #define REG_ADC1_WINLT (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */
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| 44 | #define REG_ADC1_WINUT (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */
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| 45 | #define REG_ADC1_GAINCORR (0x43002010) /**< \brief (ADC1) Gain Correction */
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| 46 | #define REG_ADC1_OFFSETCORR (0x43002012) /**< \brief (ADC1) Offset Correction */
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| 47 | #define REG_ADC1_SWTRIG (0x43002014) /**< \brief (ADC1) Software Trigger */
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| 48 | #define REG_ADC1_INTENCLR (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */
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| 49 | #define REG_ADC1_INTENSET (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */
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| 50 | #define REG_ADC1_INTFLAG (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */
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| 51 | #define REG_ADC1_STATUS (0x4300202F) /**< \brief (ADC1) Status */
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| 52 | #define REG_ADC1_SYNCBUSY (0x43002030) /**< \brief (ADC1) Synchronization Busy */
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| 53 | #define REG_ADC1_DSEQDATA (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */
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| 54 | #define REG_ADC1_DSEQCTRL (0x43002038) /**< \brief (ADC1) DMA Sequential Control */
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| 55 | #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */
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| 56 | #define REG_ADC1_RESULT (0x43002040) /**< \brief (ADC1) Result Conversion Value */
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| 57 | #define REG_ADC1_RESS (0x43002044) /**< \brief (ADC1) Last Sample Result */
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| 58 | #define REG_ADC1_CALIB (0x43002048) /**< \brief (ADC1) Calibration */
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| 59 | #else
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| 60 | #define REG_ADC1_CTRLA (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */
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| 61 | #define REG_ADC1_EVCTRL (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */
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| 62 | #define REG_ADC1_DBGCTRL (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */
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| 63 | #define REG_ADC1_INPUTCTRL (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */
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| 64 | #define REG_ADC1_CTRLB (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */
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| 65 | #define REG_ADC1_REFCTRL (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */
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| 66 | #define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */
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| 67 | #define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */
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| 68 | #define REG_ADC1_WINLT (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
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| 69 | #define REG_ADC1_WINUT (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */
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| 70 | #define REG_ADC1_GAINCORR (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */
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| 71 | #define REG_ADC1_OFFSETCORR (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */
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| 72 | #define REG_ADC1_SWTRIG (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */
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| 73 | #define REG_ADC1_INTENCLR (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */
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| 74 | #define REG_ADC1_INTENSET (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */
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| 75 | #define REG_ADC1_INTFLAG (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
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| 76 | #define REG_ADC1_STATUS (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */
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| 77 | #define REG_ADC1_SYNCBUSY (*(RoReg *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */
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| 78 | #define REG_ADC1_DSEQDATA (*(WoReg *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */
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| 79 | #define REG_ADC1_DSEQCTRL (*(RwReg *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */
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| 80 | #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */
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| 81 | #define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */
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| 82 | #define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */
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| 83 | #define REG_ADC1_CALIB (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */
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| 84 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 85 |
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| 86 | /* ========== Instance parameters for ADC1 peripheral ========== */
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| 87 | #define ADC1_BANDGAP 27 // MUXPOS value to select BANDGAP
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| 88 | #define ADC1_CTAT 29 // MUXPOS value to select CTAT
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| 89 | #define ADC1_DMAC_ID_RESRDY 70 // Index of DMA RESRDY trigger
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| 90 | #define ADC1_DMAC_ID_SEQ 71 // Index of DMA SEQ trigger
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| 91 | #define ADC1_EXTCHANNEL_MSB 15 // Number of external channels
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| 92 | #define ADC1_GCLK_ID 41 // Index of Generic Clock
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| 93 | #define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode
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| 94 | #define ADC1_OPAMP2 0 // MUXPOS value to select OPAMP2
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| 95 | #define ADC1_OPAMP01 0 // MUXPOS value to select OPAMP01
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| 96 | #define ADC1_PTAT 28 // MUXPOS value to select PTAT
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| 97 | #define ADC1_TOUCH_IMPLEMENTED 0 // TOUCH implemented or not
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| 98 | #define ADC1_TOUCH_LINES_NUM 1 // Number of touch lines
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| 99 |
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| 100 | #endif /* _SAME54_ADC1_INSTANCE_ */
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