| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for RTC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_RTC_COMPONENT_
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| 31 | #define _SAME54_RTC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR RTC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_RTC Real-Time Counter */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define RTC_U2250
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| 40 | #define REV_RTC 0x210
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| 41 |
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| 42 | /* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
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| 49 | uint16_t :3; /*!< bit: 4.. 6 Reserved */
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| 50 | uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
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| 51 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
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| 52 | uint16_t :1; /*!< bit: 12 Reserved */
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| 53 | uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
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| 54 | uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
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| 55 | uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
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| 56 | } bit; /*!< Structure used for bit access */
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| 57 | uint16_t reg; /*!< Type used for register access */
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| 58 | } RTC_MODE0_CTRLA_Type;
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| 59 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 60 |
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| 61 | #define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */
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| 62 | #define RTC_MODE0_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */
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| 63 |
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| 64 | #define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */
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| 65 | #define RTC_MODE0_CTRLA_SWRST (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)
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| 66 | #define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */
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| 67 | #define RTC_MODE0_CTRLA_ENABLE (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)
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| 68 | #define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */
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| 69 | #define RTC_MODE0_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)
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| 70 | #define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
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| 71 | #define RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */
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| 72 | #define RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */
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| 73 | #define RTC_MODE0_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */
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| 74 | #define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)
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| 75 | #define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)
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| 76 | #define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)
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| 77 | #define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */
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| 78 | #define RTC_MODE0_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)
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| 79 | #define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */
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| 80 | #define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 81 | #define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
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| 82 | #define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
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| 83 | #define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
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| 84 | #define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
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| 85 | #define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
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| 86 | #define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
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| 87 | #define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
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| 88 | #define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
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| 89 | #define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
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| 90 | #define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
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| 91 | #define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
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| 92 | #define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
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| 93 | #define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
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| 94 | #define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 95 | #define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 96 | #define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 97 | #define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 98 | #define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 99 | #define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 100 | #define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 101 | #define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 102 | #define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 103 | #define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 104 | #define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 105 | #define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
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| 106 | #define RTC_MODE0_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable */
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| 107 | #define RTC_MODE0_CTRLA_BKTRST (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)
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| 108 | #define RTC_MODE0_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable */
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| 109 | #define RTC_MODE0_CTRLA_GPTRST (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)
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| 110 | #define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */
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| 111 | #define RTC_MODE0_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
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| 112 | #define RTC_MODE0_CTRLA_MASK _U_(0xEF8F) /**< \brief (RTC_MODE0_CTRLA) MASK Register */
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| 113 |
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| 114 | /* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */
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| 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 116 | typedef union {
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| 117 | struct {
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| 118 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 119 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 120 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
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| 121 | uint16_t :4; /*!< bit: 4.. 7 Reserved */
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| 122 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
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| 123 | uint16_t :1; /*!< bit: 12 Reserved */
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| 124 | uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
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| 125 | uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
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| 126 | uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
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| 127 | } bit; /*!< Structure used for bit access */
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| 128 | uint16_t reg; /*!< Type used for register access */
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| 129 | } RTC_MODE1_CTRLA_Type;
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| 130 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 131 |
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| 132 | #define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */
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| 133 | #define RTC_MODE1_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */
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| 134 |
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| 135 | #define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */
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| 136 | #define RTC_MODE1_CTRLA_SWRST (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)
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| 137 | #define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */
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| 138 | #define RTC_MODE1_CTRLA_ENABLE (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)
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| 139 | #define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */
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| 140 | #define RTC_MODE1_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)
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| 141 | #define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
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| 142 | #define RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */
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| 143 | #define RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */
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| 144 | #define RTC_MODE1_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */
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| 145 | #define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)
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| 146 | #define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)
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| 147 | #define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)
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| 148 | #define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */
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| 149 | #define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 150 | #define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
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| 151 | #define RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
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| 152 | #define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
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| 153 | #define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
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| 154 | #define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
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| 155 | #define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
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| 156 | #define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
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| 157 | #define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
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| 158 | #define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
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| 159 | #define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
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| 160 | #define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
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| 161 | #define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
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| 162 | #define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
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| 163 | #define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 164 | #define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 165 | #define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 166 | #define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 167 | #define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 168 | #define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 169 | #define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 170 | #define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 171 | #define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 172 | #define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 173 | #define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 174 | #define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
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| 175 | #define RTC_MODE1_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable */
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| 176 | #define RTC_MODE1_CTRLA_BKTRST (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)
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| 177 | #define RTC_MODE1_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable */
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| 178 | #define RTC_MODE1_CTRLA_GPTRST (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)
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| 179 | #define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */
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| 180 | #define RTC_MODE1_CTRLA_COUNTSYNC (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)
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| 181 | #define RTC_MODE1_CTRLA_MASK _U_(0xEF0F) /**< \brief (RTC_MODE1_CTRLA) MASK Register */
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| 182 |
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| 183 | /* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */
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| 184 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 185 | typedef union {
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| 186 | struct {
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| 187 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 188 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 189 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
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| 190 | uint16_t :2; /*!< bit: 4.. 5 Reserved */
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| 191 | uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
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| 192 | uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
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| 193 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
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| 194 | uint16_t :1; /*!< bit: 12 Reserved */
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| 195 | uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
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| 196 | uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
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| 197 | uint16_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable */
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| 198 | } bit; /*!< Structure used for bit access */
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| 199 | uint16_t reg; /*!< Type used for register access */
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| 200 | } RTC_MODE2_CTRLA_Type;
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| 201 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 202 |
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| 203 | #define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */
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| 204 | #define RTC_MODE2_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */
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| 205 |
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| 206 | #define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */
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| 207 | #define RTC_MODE2_CTRLA_SWRST (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)
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| 208 | #define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */
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| 209 | #define RTC_MODE2_CTRLA_ENABLE (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)
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| 210 | #define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */
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| 211 | #define RTC_MODE2_CTRLA_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)
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| 212 | #define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
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| 213 | #define RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */
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| 214 | #define RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */
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| 215 | #define RTC_MODE2_CTRLA_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */
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| 216 | #define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)
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| 217 | #define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)
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| 218 | #define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)
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| 219 | #define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */
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| 220 | #define RTC_MODE2_CTRLA_CLKREP (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)
|
| 221 | #define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */
|
| 222 | #define RTC_MODE2_CTRLA_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)
|
| 223 | #define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */
|
| 224 | #define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 225 | #define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
|
| 226 | #define RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
|
| 227 | #define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
|
| 228 | #define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
|
| 229 | #define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
|
| 230 | #define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
|
| 231 | #define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
|
| 232 | #define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
|
| 233 | #define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
|
| 234 | #define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
|
| 235 | #define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
|
| 236 | #define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
|
| 237 | #define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
|
| 238 | #define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 239 | #define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 240 | #define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 241 | #define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 242 | #define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 243 | #define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 244 | #define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 245 | #define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 246 | #define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 247 | #define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 248 | #define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 249 | #define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
|
| 250 | #define RTC_MODE2_CTRLA_BKTRST_Pos 13 /**< \brief (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable */
|
| 251 | #define RTC_MODE2_CTRLA_BKTRST (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)
|
| 252 | #define RTC_MODE2_CTRLA_GPTRST_Pos 14 /**< \brief (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable */
|
| 253 | #define RTC_MODE2_CTRLA_GPTRST (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)
|
| 254 | #define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */
|
| 255 | #define RTC_MODE2_CTRLA_CLOCKSYNC (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)
|
| 256 | #define RTC_MODE2_CTRLA_MASK _U_(0xEFCF) /**< \brief (RTC_MODE2_CTRLA) MASK Register */
|
| 257 |
|
| 258 | /* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */
|
| 259 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 260 | typedef union {
|
| 261 | struct {
|
| 262 | uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
|
| 263 | uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
|
| 264 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 265 | uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
|
| 266 | uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
|
| 267 | uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
|
| 268 | uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
|
| 269 | uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
|
| 270 | uint16_t :1; /*!< bit: 11 Reserved */
|
| 271 | uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
|
| 272 | uint16_t :1; /*!< bit: 15 Reserved */
|
| 273 | } bit; /*!< Structure used for bit access */
|
| 274 | uint16_t reg; /*!< Type used for register access */
|
| 275 | } RTC_MODE0_CTRLB_Type;
|
| 276 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 277 |
|
| 278 | #define RTC_MODE0_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE0_CTRLB offset) MODE0 Control B */
|
| 279 | #define RTC_MODE0_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRLB reset_value) MODE0 Control B */
|
| 280 |
|
| 281 | #define RTC_MODE0_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE0_CTRLB) General Purpose 0 Enable */
|
| 282 | #define RTC_MODE0_CTRLB_GP0EN (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)
|
| 283 | #define RTC_MODE0_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE0_CTRLB) General Purpose 2 Enable */
|
| 284 | #define RTC_MODE0_CTRLB_GP2EN (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)
|
| 285 | #define RTC_MODE0_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE0_CTRLB) Debouncer Majority Enable */
|
| 286 | #define RTC_MODE0_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)
|
| 287 | #define RTC_MODE0_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable */
|
| 288 | #define RTC_MODE0_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)
|
| 289 | #define RTC_MODE0_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE0_CTRLB) RTC Output Enable */
|
| 290 | #define RTC_MODE0_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)
|
| 291 | #define RTC_MODE0_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE0_CTRLB) DMA Enable */
|
| 292 | #define RTC_MODE0_CTRLB_DMAEN (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)
|
| 293 | #define RTC_MODE0_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE0_CTRLB) Debounce Freqnuency */
|
| 294 | #define RTC_MODE0_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 295 | #define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
|
| 296 | #define RTC_MODE0_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
|
| 297 | #define RTC_MODE0_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
|
| 298 | #define RTC_MODE0_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
|
| 299 | #define RTC_MODE0_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
|
| 300 | #define RTC_MODE0_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
|
| 301 | #define RTC_MODE0_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
|
| 302 | #define RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
|
| 303 | #define RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
|
| 304 | #define RTC_MODE0_CTRLB_DEBF_DIV2 (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 305 | #define RTC_MODE0_CTRLB_DEBF_DIV4 (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 306 | #define RTC_MODE0_CTRLB_DEBF_DIV8 (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 307 | #define RTC_MODE0_CTRLB_DEBF_DIV16 (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 308 | #define RTC_MODE0_CTRLB_DEBF_DIV32 (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 309 | #define RTC_MODE0_CTRLB_DEBF_DIV64 (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 310 | #define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 311 | #define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)
|
| 312 | #define RTC_MODE0_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE0_CTRLB) Active Layer Freqnuency */
|
| 313 | #define RTC_MODE0_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 314 | #define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
|
| 315 | #define RTC_MODE0_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
|
| 316 | #define RTC_MODE0_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
|
| 317 | #define RTC_MODE0_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
|
| 318 | #define RTC_MODE0_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
|
| 319 | #define RTC_MODE0_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
|
| 320 | #define RTC_MODE0_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
|
| 321 | #define RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
|
| 322 | #define RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
|
| 323 | #define RTC_MODE0_CTRLB_ACTF_DIV2 (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 324 | #define RTC_MODE0_CTRLB_ACTF_DIV4 (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 325 | #define RTC_MODE0_CTRLB_ACTF_DIV8 (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 326 | #define RTC_MODE0_CTRLB_ACTF_DIV16 (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 327 | #define RTC_MODE0_CTRLB_ACTF_DIV32 (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 328 | #define RTC_MODE0_CTRLB_ACTF_DIV64 (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 329 | #define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 330 | #define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)
|
| 331 | #define RTC_MODE0_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE0_CTRLB) MASK Register */
|
| 332 |
|
| 333 | /* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */
|
| 334 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 335 | typedef union {
|
| 336 | struct {
|
| 337 | uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
|
| 338 | uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
|
| 339 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 340 | uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
|
| 341 | uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
|
| 342 | uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
|
| 343 | uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
|
| 344 | uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
|
| 345 | uint16_t :1; /*!< bit: 11 Reserved */
|
| 346 | uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
|
| 347 | uint16_t :1; /*!< bit: 15 Reserved */
|
| 348 | } bit; /*!< Structure used for bit access */
|
| 349 | uint16_t reg; /*!< Type used for register access */
|
| 350 | } RTC_MODE1_CTRLB_Type;
|
| 351 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 352 |
|
| 353 | #define RTC_MODE1_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE1_CTRLB offset) MODE1 Control B */
|
| 354 | #define RTC_MODE1_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRLB reset_value) MODE1 Control B */
|
| 355 |
|
| 356 | #define RTC_MODE1_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE1_CTRLB) General Purpose 0 Enable */
|
| 357 | #define RTC_MODE1_CTRLB_GP0EN (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)
|
| 358 | #define RTC_MODE1_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE1_CTRLB) General Purpose 2 Enable */
|
| 359 | #define RTC_MODE1_CTRLB_GP2EN (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)
|
| 360 | #define RTC_MODE1_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE1_CTRLB) Debouncer Majority Enable */
|
| 361 | #define RTC_MODE1_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)
|
| 362 | #define RTC_MODE1_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable */
|
| 363 | #define RTC_MODE1_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)
|
| 364 | #define RTC_MODE1_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE1_CTRLB) RTC Output Enable */
|
| 365 | #define RTC_MODE1_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)
|
| 366 | #define RTC_MODE1_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE1_CTRLB) DMA Enable */
|
| 367 | #define RTC_MODE1_CTRLB_DMAEN (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)
|
| 368 | #define RTC_MODE1_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE1_CTRLB) Debounce Freqnuency */
|
| 369 | #define RTC_MODE1_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 370 | #define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
|
| 371 | #define RTC_MODE1_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
|
| 372 | #define RTC_MODE1_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
|
| 373 | #define RTC_MODE1_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
|
| 374 | #define RTC_MODE1_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
|
| 375 | #define RTC_MODE1_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
|
| 376 | #define RTC_MODE1_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
|
| 377 | #define RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
|
| 378 | #define RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
|
| 379 | #define RTC_MODE1_CTRLB_DEBF_DIV2 (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 380 | #define RTC_MODE1_CTRLB_DEBF_DIV4 (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 381 | #define RTC_MODE1_CTRLB_DEBF_DIV8 (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 382 | #define RTC_MODE1_CTRLB_DEBF_DIV16 (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 383 | #define RTC_MODE1_CTRLB_DEBF_DIV32 (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 384 | #define RTC_MODE1_CTRLB_DEBF_DIV64 (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 385 | #define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 386 | #define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)
|
| 387 | #define RTC_MODE1_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE1_CTRLB) Active Layer Freqnuency */
|
| 388 | #define RTC_MODE1_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 389 | #define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
|
| 390 | #define RTC_MODE1_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
|
| 391 | #define RTC_MODE1_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
|
| 392 | #define RTC_MODE1_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
|
| 393 | #define RTC_MODE1_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
|
| 394 | #define RTC_MODE1_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
|
| 395 | #define RTC_MODE1_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
|
| 396 | #define RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
|
| 397 | #define RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
|
| 398 | #define RTC_MODE1_CTRLB_ACTF_DIV2 (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 399 | #define RTC_MODE1_CTRLB_ACTF_DIV4 (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 400 | #define RTC_MODE1_CTRLB_ACTF_DIV8 (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 401 | #define RTC_MODE1_CTRLB_ACTF_DIV16 (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 402 | #define RTC_MODE1_CTRLB_ACTF_DIV32 (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 403 | #define RTC_MODE1_CTRLB_ACTF_DIV64 (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 404 | #define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 405 | #define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)
|
| 406 | #define RTC_MODE1_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE1_CTRLB) MASK Register */
|
| 407 |
|
| 408 | /* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */
|
| 409 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 410 | typedef union {
|
| 411 | struct {
|
| 412 | uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */
|
| 413 | uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */
|
| 414 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 415 | uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */
|
| 416 | uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */
|
| 417 | uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */
|
| 418 | uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */
|
| 419 | uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */
|
| 420 | uint16_t :1; /*!< bit: 11 Reserved */
|
| 421 | uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */
|
| 422 | uint16_t :1; /*!< bit: 15 Reserved */
|
| 423 | } bit; /*!< Structure used for bit access */
|
| 424 | uint16_t reg; /*!< Type used for register access */
|
| 425 | } RTC_MODE2_CTRLB_Type;
|
| 426 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 427 |
|
| 428 | #define RTC_MODE2_CTRLB_OFFSET 0x02 /**< \brief (RTC_MODE2_CTRLB offset) MODE2 Control B */
|
| 429 | #define RTC_MODE2_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRLB reset_value) MODE2 Control B */
|
| 430 |
|
| 431 | #define RTC_MODE2_CTRLB_GP0EN_Pos 0 /**< \brief (RTC_MODE2_CTRLB) General Purpose 0 Enable */
|
| 432 | #define RTC_MODE2_CTRLB_GP0EN (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)
|
| 433 | #define RTC_MODE2_CTRLB_GP2EN_Pos 1 /**< \brief (RTC_MODE2_CTRLB) General Purpose 2 Enable */
|
| 434 | #define RTC_MODE2_CTRLB_GP2EN (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)
|
| 435 | #define RTC_MODE2_CTRLB_DEBMAJ_Pos 4 /**< \brief (RTC_MODE2_CTRLB) Debouncer Majority Enable */
|
| 436 | #define RTC_MODE2_CTRLB_DEBMAJ (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)
|
| 437 | #define RTC_MODE2_CTRLB_DEBASYNC_Pos 5 /**< \brief (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable */
|
| 438 | #define RTC_MODE2_CTRLB_DEBASYNC (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)
|
| 439 | #define RTC_MODE2_CTRLB_RTCOUT_Pos 6 /**< \brief (RTC_MODE2_CTRLB) RTC Output Enable */
|
| 440 | #define RTC_MODE2_CTRLB_RTCOUT (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)
|
| 441 | #define RTC_MODE2_CTRLB_DMAEN_Pos 7 /**< \brief (RTC_MODE2_CTRLB) DMA Enable */
|
| 442 | #define RTC_MODE2_CTRLB_DMAEN (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)
|
| 443 | #define RTC_MODE2_CTRLB_DEBF_Pos 8 /**< \brief (RTC_MODE2_CTRLB) Debounce Freqnuency */
|
| 444 | #define RTC_MODE2_CTRLB_DEBF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 445 | #define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
|
| 446 | #define RTC_MODE2_CTRLB_DEBF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
|
| 447 | #define RTC_MODE2_CTRLB_DEBF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
|
| 448 | #define RTC_MODE2_CTRLB_DEBF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
|
| 449 | #define RTC_MODE2_CTRLB_DEBF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
|
| 450 | #define RTC_MODE2_CTRLB_DEBF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
|
| 451 | #define RTC_MODE2_CTRLB_DEBF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
|
| 452 | #define RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
|
| 453 | #define RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
|
| 454 | #define RTC_MODE2_CTRLB_DEBF_DIV2 (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 455 | #define RTC_MODE2_CTRLB_DEBF_DIV4 (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 456 | #define RTC_MODE2_CTRLB_DEBF_DIV8 (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 457 | #define RTC_MODE2_CTRLB_DEBF_DIV16 (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 458 | #define RTC_MODE2_CTRLB_DEBF_DIV32 (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 459 | #define RTC_MODE2_CTRLB_DEBF_DIV64 (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 460 | #define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 461 | #define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)
|
| 462 | #define RTC_MODE2_CTRLB_ACTF_Pos 12 /**< \brief (RTC_MODE2_CTRLB) Active Layer Freqnuency */
|
| 463 | #define RTC_MODE2_CTRLB_ACTF_Msk (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 464 | #define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
|
| 465 | #define RTC_MODE2_CTRLB_ACTF_DIV2_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
|
| 466 | #define RTC_MODE2_CTRLB_ACTF_DIV4_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
|
| 467 | #define RTC_MODE2_CTRLB_ACTF_DIV8_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
|
| 468 | #define RTC_MODE2_CTRLB_ACTF_DIV16_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
|
| 469 | #define RTC_MODE2_CTRLB_ACTF_DIV32_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
|
| 470 | #define RTC_MODE2_CTRLB_ACTF_DIV64_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
|
| 471 | #define RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
|
| 472 | #define RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
|
| 473 | #define RTC_MODE2_CTRLB_ACTF_DIV2 (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 474 | #define RTC_MODE2_CTRLB_ACTF_DIV4 (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 475 | #define RTC_MODE2_CTRLB_ACTF_DIV8 (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 476 | #define RTC_MODE2_CTRLB_ACTF_DIV16 (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 477 | #define RTC_MODE2_CTRLB_ACTF_DIV32 (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 478 | #define RTC_MODE2_CTRLB_ACTF_DIV64 (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 479 | #define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 480 | #define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)
|
| 481 | #define RTC_MODE2_CTRLB_MASK _U_(0x77F3) /**< \brief (RTC_MODE2_CTRLB) MASK Register */
|
| 482 |
|
| 483 | /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */
|
| 484 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 485 | typedef union {
|
| 486 | struct {
|
| 487 | uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
|
| 488 | uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
|
| 489 | uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
|
| 490 | uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
|
| 491 | uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
|
| 492 | uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
|
| 493 | uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
|
| 494 | uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
|
| 495 | uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
|
| 496 | uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
|
| 497 | uint32_t :4; /*!< bit: 10..13 Reserved */
|
| 498 | uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
|
| 499 | uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
|
| 500 | uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
|
| 501 | uint32_t :15; /*!< bit: 17..31 Reserved */
|
| 502 | } bit; /*!< Structure used for bit access */
|
| 503 | struct {
|
| 504 | uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
|
| 505 | uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
|
| 506 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 507 | } vec; /*!< Structure used for vec access */
|
| 508 | uint32_t reg; /*!< Type used for register access */
|
| 509 | } RTC_MODE0_EVCTRL_Type;
|
| 510 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 511 |
|
| 512 | #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
|
| 513 | #define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
|
| 514 |
|
| 515 | #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
|
| 516 | #define RTC_MODE0_EVCTRL_PEREO0 (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)
|
| 517 | #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
|
| 518 | #define RTC_MODE0_EVCTRL_PEREO1 (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)
|
| 519 | #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
|
| 520 | #define RTC_MODE0_EVCTRL_PEREO2 (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)
|
| 521 | #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
|
| 522 | #define RTC_MODE0_EVCTRL_PEREO3 (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)
|
| 523 | #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
|
| 524 | #define RTC_MODE0_EVCTRL_PEREO4 (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)
|
| 525 | #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
|
| 526 | #define RTC_MODE0_EVCTRL_PEREO5 (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)
|
| 527 | #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
|
| 528 | #define RTC_MODE0_EVCTRL_PEREO6 (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)
|
| 529 | #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
|
| 530 | #define RTC_MODE0_EVCTRL_PEREO7 (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)
|
| 531 | #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
|
| 532 | #define RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
|
| 533 | #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
|
| 534 | #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
|
| 535 | #define RTC_MODE0_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)
|
| 536 | #define RTC_MODE0_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable */
|
| 537 | #define RTC_MODE0_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)
|
| 538 | #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
|
| 539 | #define RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)
|
| 540 | #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
|
| 541 | #define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Output Enable */
|
| 542 | #define RTC_MODE0_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
|
| 543 | #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
|
| 544 | #define RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
|
| 545 | #define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Input Enable */
|
| 546 | #define RTC_MODE0_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)
|
| 547 | #define RTC_MODE0_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
|
| 548 |
|
| 549 | /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */
|
| 550 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 551 | typedef union {
|
| 552 | struct {
|
| 553 | uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
|
| 554 | uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
|
| 555 | uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
|
| 556 | uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
|
| 557 | uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
|
| 558 | uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
|
| 559 | uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
|
| 560 | uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
|
| 561 | uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
|
| 562 | uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
|
| 563 | uint32_t CMPEO2:1; /*!< bit: 10 Compare 2 Event Output Enable */
|
| 564 | uint32_t CMPEO3:1; /*!< bit: 11 Compare 3 Event Output Enable */
|
| 565 | uint32_t :2; /*!< bit: 12..13 Reserved */
|
| 566 | uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
|
| 567 | uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
|
| 568 | uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
|
| 569 | uint32_t :15; /*!< bit: 17..31 Reserved */
|
| 570 | } bit; /*!< Structure used for bit access */
|
| 571 | struct {
|
| 572 | uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
|
| 573 | uint32_t CMPEO:4; /*!< bit: 8..11 Compare x Event Output Enable */
|
| 574 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
| 575 | } vec; /*!< Structure used for vec access */
|
| 576 | uint32_t reg; /*!< Type used for register access */
|
| 577 | } RTC_MODE1_EVCTRL_Type;
|
| 578 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 579 |
|
| 580 | #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
|
| 581 | #define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
|
| 582 |
|
| 583 | #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
|
| 584 | #define RTC_MODE1_EVCTRL_PEREO0 (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)
|
| 585 | #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
|
| 586 | #define RTC_MODE1_EVCTRL_PEREO1 (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)
|
| 587 | #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
|
| 588 | #define RTC_MODE1_EVCTRL_PEREO2 (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)
|
| 589 | #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
|
| 590 | #define RTC_MODE1_EVCTRL_PEREO3 (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)
|
| 591 | #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
|
| 592 | #define RTC_MODE1_EVCTRL_PEREO4 (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)
|
| 593 | #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
|
| 594 | #define RTC_MODE1_EVCTRL_PEREO5 (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)
|
| 595 | #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
|
| 596 | #define RTC_MODE1_EVCTRL_PEREO6 (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)
|
| 597 | #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
|
| 598 | #define RTC_MODE1_EVCTRL_PEREO7 (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)
|
| 599 | #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
|
| 600 | #define RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
|
| 601 | #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
|
| 602 | #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
|
| 603 | #define RTC_MODE1_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)
|
| 604 | #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
|
| 605 | #define RTC_MODE1_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)
|
| 606 | #define RTC_MODE1_EVCTRL_CMPEO2_Pos 10 /**< \brief (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable */
|
| 607 | #define RTC_MODE1_EVCTRL_CMPEO2 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)
|
| 608 | #define RTC_MODE1_EVCTRL_CMPEO3_Pos 11 /**< \brief (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable */
|
| 609 | #define RTC_MODE1_EVCTRL_CMPEO3 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)
|
| 610 | #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
|
| 611 | #define RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)
|
| 612 | #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
|
| 613 | #define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Output Enable */
|
| 614 | #define RTC_MODE1_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)
|
| 615 | #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
|
| 616 | #define RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
|
| 617 | #define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Input Enable */
|
| 618 | #define RTC_MODE1_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)
|
| 619 | #define RTC_MODE1_EVCTRL_MASK _U_(0x0001CFFF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
|
| 620 |
|
| 621 | /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */
|
| 622 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 623 | typedef union {
|
| 624 | struct {
|
| 625 | uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
|
| 626 | uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
|
| 627 | uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
|
| 628 | uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
|
| 629 | uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
|
| 630 | uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
|
| 631 | uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
|
| 632 | uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
|
| 633 | uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
|
| 634 | uint32_t ALARMEO1:1; /*!< bit: 9 Alarm 1 Event Output Enable */
|
| 635 | uint32_t :4; /*!< bit: 10..13 Reserved */
|
| 636 | uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */
|
| 637 | uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
|
| 638 | uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */
|
| 639 | uint32_t :15; /*!< bit: 17..31 Reserved */
|
| 640 | } bit; /*!< Structure used for bit access */
|
| 641 | struct {
|
| 642 | uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
|
| 643 | uint32_t ALARMEO:2; /*!< bit: 8.. 9 Alarm x Event Output Enable */
|
| 644 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 645 | } vec; /*!< Structure used for vec access */
|
| 646 | uint32_t reg; /*!< Type used for register access */
|
| 647 | } RTC_MODE2_EVCTRL_Type;
|
| 648 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 649 |
|
| 650 | #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
|
| 651 | #define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
|
| 652 |
|
| 653 | #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
|
| 654 | #define RTC_MODE2_EVCTRL_PEREO0 (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)
|
| 655 | #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
|
| 656 | #define RTC_MODE2_EVCTRL_PEREO1 (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)
|
| 657 | #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
|
| 658 | #define RTC_MODE2_EVCTRL_PEREO2 (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)
|
| 659 | #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
|
| 660 | #define RTC_MODE2_EVCTRL_PEREO3 (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)
|
| 661 | #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
|
| 662 | #define RTC_MODE2_EVCTRL_PEREO4 (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)
|
| 663 | #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
|
| 664 | #define RTC_MODE2_EVCTRL_PEREO5 (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)
|
| 665 | #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
|
| 666 | #define RTC_MODE2_EVCTRL_PEREO6 (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)
|
| 667 | #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
|
| 668 | #define RTC_MODE2_EVCTRL_PEREO7 (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)
|
| 669 | #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
|
| 670 | #define RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
|
| 671 | #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
|
| 672 | #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
|
| 673 | #define RTC_MODE2_EVCTRL_ALARMEO0 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
|
| 674 | #define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9 /**< \brief (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable */
|
| 675 | #define RTC_MODE2_EVCTRL_ALARMEO1 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)
|
| 676 | #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
|
| 677 | #define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
|
| 678 | #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
|
| 679 | #define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Output Enable */
|
| 680 | #define RTC_MODE2_EVCTRL_TAMPEREO (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)
|
| 681 | #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
|
| 682 | #define RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
|
| 683 | #define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16 /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Input Enable */
|
| 684 | #define RTC_MODE2_EVCTRL_TAMPEVEI (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)
|
| 685 | #define RTC_MODE2_EVCTRL_MASK _U_(0x0001C3FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
|
| 686 |
|
| 687 | /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */
|
| 688 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 689 | typedef union {
|
| 690 | struct {
|
| 691 | uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
|
| 692 | uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
|
| 693 | uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
|
| 694 | uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
|
| 695 | uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
|
| 696 | uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
|
| 697 | uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
|
| 698 | uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
|
| 699 | uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
|
| 700 | uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
|
| 701 | uint16_t :4; /*!< bit: 10..13 Reserved */
|
| 702 | uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
|
| 703 | uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
|
| 704 | } bit; /*!< Structure used for bit access */
|
| 705 | struct {
|
| 706 | uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
|
| 707 | uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
|
| 708 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 709 | } vec; /*!< Structure used for vec access */
|
| 710 | uint16_t reg; /*!< Type used for register access */
|
| 711 | } RTC_MODE0_INTENCLR_Type;
|
| 712 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 713 |
|
| 714 | #define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
|
| 715 | #define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
|
| 716 |
|
| 717 | #define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */
|
| 718 | #define RTC_MODE0_INTENCLR_PER0 (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)
|
| 719 | #define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */
|
| 720 | #define RTC_MODE0_INTENCLR_PER1 (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)
|
| 721 | #define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */
|
| 722 | #define RTC_MODE0_INTENCLR_PER2 (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)
|
| 723 | #define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */
|
| 724 | #define RTC_MODE0_INTENCLR_PER3 (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)
|
| 725 | #define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */
|
| 726 | #define RTC_MODE0_INTENCLR_PER4 (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)
|
| 727 | #define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */
|
| 728 | #define RTC_MODE0_INTENCLR_PER5 (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)
|
| 729 | #define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */
|
| 730 | #define RTC_MODE0_INTENCLR_PER6 (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)
|
| 731 | #define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */
|
| 732 | #define RTC_MODE0_INTENCLR_PER7 (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)
|
| 733 | #define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */
|
| 734 | #define RTC_MODE0_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)
|
| 735 | #define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))
|
| 736 | #define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
|
| 737 | #define RTC_MODE0_INTENCLR_CMP0 (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)
|
| 738 | #define RTC_MODE0_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable */
|
| 739 | #define RTC_MODE0_INTENCLR_CMP1 (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)
|
| 740 | #define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
|
| 741 | #define RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)
|
| 742 | #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
|
| 743 | #define RTC_MODE0_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENCLR) Tamper Enable */
|
| 744 | #define RTC_MODE0_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)
|
| 745 | #define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
|
| 746 | #define RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
|
| 747 | #define RTC_MODE0_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
|
| 748 |
|
| 749 | /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */
|
| 750 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 751 | typedef union {
|
| 752 | struct {
|
| 753 | uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
|
| 754 | uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
|
| 755 | uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
|
| 756 | uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
|
| 757 | uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
|
| 758 | uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
|
| 759 | uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
|
| 760 | uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
|
| 761 | uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
|
| 762 | uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
|
| 763 | uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
|
| 764 | uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
|
| 765 | uint16_t :2; /*!< bit: 12..13 Reserved */
|
| 766 | uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
|
| 767 | uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
|
| 768 | } bit; /*!< Structure used for bit access */
|
| 769 | struct {
|
| 770 | uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
|
| 771 | uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
|
| 772 | uint16_t :4; /*!< bit: 12..15 Reserved */
|
| 773 | } vec; /*!< Structure used for vec access */
|
| 774 | uint16_t reg; /*!< Type used for register access */
|
| 775 | } RTC_MODE1_INTENCLR_Type;
|
| 776 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 777 |
|
| 778 | #define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
|
| 779 | #define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
|
| 780 |
|
| 781 | #define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */
|
| 782 | #define RTC_MODE1_INTENCLR_PER0 (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)
|
| 783 | #define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */
|
| 784 | #define RTC_MODE1_INTENCLR_PER1 (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)
|
| 785 | #define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */
|
| 786 | #define RTC_MODE1_INTENCLR_PER2 (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)
|
| 787 | #define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */
|
| 788 | #define RTC_MODE1_INTENCLR_PER3 (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)
|
| 789 | #define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */
|
| 790 | #define RTC_MODE1_INTENCLR_PER4 (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)
|
| 791 | #define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */
|
| 792 | #define RTC_MODE1_INTENCLR_PER5 (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)
|
| 793 | #define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */
|
| 794 | #define RTC_MODE1_INTENCLR_PER6 (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)
|
| 795 | #define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */
|
| 796 | #define RTC_MODE1_INTENCLR_PER7 (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)
|
| 797 | #define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */
|
| 798 | #define RTC_MODE1_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)
|
| 799 | #define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))
|
| 800 | #define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
|
| 801 | #define RTC_MODE1_INTENCLR_CMP0 (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)
|
| 802 | #define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
|
| 803 | #define RTC_MODE1_INTENCLR_CMP1 (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)
|
| 804 | #define RTC_MODE1_INTENCLR_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable */
|
| 805 | #define RTC_MODE1_INTENCLR_CMP2 (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)
|
| 806 | #define RTC_MODE1_INTENCLR_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable */
|
| 807 | #define RTC_MODE1_INTENCLR_CMP3 (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)
|
| 808 | #define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
|
| 809 | #define RTC_MODE1_INTENCLR_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)
|
| 810 | #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
|
| 811 | #define RTC_MODE1_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENCLR) Tamper Enable */
|
| 812 | #define RTC_MODE1_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)
|
| 813 | #define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
|
| 814 | #define RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
|
| 815 | #define RTC_MODE1_INTENCLR_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
|
| 816 |
|
| 817 | /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */
|
| 818 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 819 | typedef union {
|
| 820 | struct {
|
| 821 | uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
|
| 822 | uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
|
| 823 | uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
|
| 824 | uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
|
| 825 | uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
|
| 826 | uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
|
| 827 | uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
|
| 828 | uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
|
| 829 | uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
|
| 830 | uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
|
| 831 | uint16_t :4; /*!< bit: 10..13 Reserved */
|
| 832 | uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
|
| 833 | uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
|
| 834 | } bit; /*!< Structure used for bit access */
|
| 835 | struct {
|
| 836 | uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
|
| 837 | uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
|
| 838 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 839 | } vec; /*!< Structure used for vec access */
|
| 840 | uint16_t reg; /*!< Type used for register access */
|
| 841 | } RTC_MODE2_INTENCLR_Type;
|
| 842 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 843 |
|
| 844 | #define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
|
| 845 | #define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
|
| 846 |
|
| 847 | #define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */
|
| 848 | #define RTC_MODE2_INTENCLR_PER0 (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)
|
| 849 | #define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */
|
| 850 | #define RTC_MODE2_INTENCLR_PER1 (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)
|
| 851 | #define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */
|
| 852 | #define RTC_MODE2_INTENCLR_PER2 (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)
|
| 853 | #define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */
|
| 854 | #define RTC_MODE2_INTENCLR_PER3 (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)
|
| 855 | #define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */
|
| 856 | #define RTC_MODE2_INTENCLR_PER4 (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)
|
| 857 | #define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */
|
| 858 | #define RTC_MODE2_INTENCLR_PER5 (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)
|
| 859 | #define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */
|
| 860 | #define RTC_MODE2_INTENCLR_PER6 (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)
|
| 861 | #define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */
|
| 862 | #define RTC_MODE2_INTENCLR_PER7 (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)
|
| 863 | #define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */
|
| 864 | #define RTC_MODE2_INTENCLR_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)
|
| 865 | #define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))
|
| 866 | #define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
|
| 867 | #define RTC_MODE2_INTENCLR_ALARM0 (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)
|
| 868 | #define RTC_MODE2_INTENCLR_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable */
|
| 869 | #define RTC_MODE2_INTENCLR_ALARM1 (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)
|
| 870 | #define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
|
| 871 | #define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)
|
| 872 | #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
|
| 873 | #define RTC_MODE2_INTENCLR_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENCLR) Tamper Enable */
|
| 874 | #define RTC_MODE2_INTENCLR_TAMPER (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)
|
| 875 | #define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
|
| 876 | #define RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
|
| 877 | #define RTC_MODE2_INTENCLR_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
|
| 878 |
|
| 879 | /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */
|
| 880 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 881 | typedef union {
|
| 882 | struct {
|
| 883 | uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
|
| 884 | uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
|
| 885 | uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
|
| 886 | uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
|
| 887 | uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
|
| 888 | uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
|
| 889 | uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
|
| 890 | uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
|
| 891 | uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
|
| 892 | uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
|
| 893 | uint16_t :4; /*!< bit: 10..13 Reserved */
|
| 894 | uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
|
| 895 | uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
|
| 896 | } bit; /*!< Structure used for bit access */
|
| 897 | struct {
|
| 898 | uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
|
| 899 | uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */
|
| 900 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 901 | } vec; /*!< Structure used for vec access */
|
| 902 | uint16_t reg; /*!< Type used for register access */
|
| 903 | } RTC_MODE0_INTENSET_Type;
|
| 904 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 905 |
|
| 906 | #define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
|
| 907 | #define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
|
| 908 |
|
| 909 | #define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */
|
| 910 | #define RTC_MODE0_INTENSET_PER0 (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)
|
| 911 | #define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */
|
| 912 | #define RTC_MODE0_INTENSET_PER1 (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)
|
| 913 | #define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */
|
| 914 | #define RTC_MODE0_INTENSET_PER2 (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)
|
| 915 | #define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */
|
| 916 | #define RTC_MODE0_INTENSET_PER3 (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)
|
| 917 | #define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */
|
| 918 | #define RTC_MODE0_INTENSET_PER4 (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)
|
| 919 | #define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */
|
| 920 | #define RTC_MODE0_INTENSET_PER5 (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)
|
| 921 | #define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */
|
| 922 | #define RTC_MODE0_INTENSET_PER6 (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)
|
| 923 | #define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */
|
| 924 | #define RTC_MODE0_INTENSET_PER7 (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)
|
| 925 | #define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */
|
| 926 | #define RTC_MODE0_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)
|
| 927 | #define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))
|
| 928 | #define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
|
| 929 | #define RTC_MODE0_INTENSET_CMP0 (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)
|
| 930 | #define RTC_MODE0_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable */
|
| 931 | #define RTC_MODE0_INTENSET_CMP1 (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)
|
| 932 | #define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
|
| 933 | #define RTC_MODE0_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)
|
| 934 | #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
|
| 935 | #define RTC_MODE0_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTENSET) Tamper Enable */
|
| 936 | #define RTC_MODE0_INTENSET_TAMPER (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)
|
| 937 | #define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
|
| 938 | #define RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
|
| 939 | #define RTC_MODE0_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTENSET) MASK Register */
|
| 940 |
|
| 941 | /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */
|
| 942 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 943 | typedef union {
|
| 944 | struct {
|
| 945 | uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */
|
| 946 | uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */
|
| 947 | uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */
|
| 948 | uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */
|
| 949 | uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */
|
| 950 | uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */
|
| 951 | uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */
|
| 952 | uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */
|
| 953 | uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */
|
| 954 | uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */
|
| 955 | uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */
|
| 956 | uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */
|
| 957 | uint16_t :2; /*!< bit: 12..13 Reserved */
|
| 958 | uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
|
| 959 | uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
|
| 960 | } bit; /*!< Structure used for bit access */
|
| 961 | struct {
|
| 962 | uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */
|
| 963 | uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */
|
| 964 | uint16_t :4; /*!< bit: 12..15 Reserved */
|
| 965 | } vec; /*!< Structure used for vec access */
|
| 966 | uint16_t reg; /*!< Type used for register access */
|
| 967 | } RTC_MODE1_INTENSET_Type;
|
| 968 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 969 |
|
| 970 | #define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
|
| 971 | #define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
|
| 972 |
|
| 973 | #define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */
|
| 974 | #define RTC_MODE1_INTENSET_PER0 (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)
|
| 975 | #define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */
|
| 976 | #define RTC_MODE1_INTENSET_PER1 (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)
|
| 977 | #define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */
|
| 978 | #define RTC_MODE1_INTENSET_PER2 (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)
|
| 979 | #define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */
|
| 980 | #define RTC_MODE1_INTENSET_PER3 (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)
|
| 981 | #define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */
|
| 982 | #define RTC_MODE1_INTENSET_PER4 (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)
|
| 983 | #define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */
|
| 984 | #define RTC_MODE1_INTENSET_PER5 (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)
|
| 985 | #define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */
|
| 986 | #define RTC_MODE1_INTENSET_PER6 (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)
|
| 987 | #define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */
|
| 988 | #define RTC_MODE1_INTENSET_PER7 (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)
|
| 989 | #define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */
|
| 990 | #define RTC_MODE1_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)
|
| 991 | #define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))
|
| 992 | #define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
|
| 993 | #define RTC_MODE1_INTENSET_CMP0 (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)
|
| 994 | #define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
|
| 995 | #define RTC_MODE1_INTENSET_CMP1 (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)
|
| 996 | #define RTC_MODE1_INTENSET_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable */
|
| 997 | #define RTC_MODE1_INTENSET_CMP2 (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)
|
| 998 | #define RTC_MODE1_INTENSET_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable */
|
| 999 | #define RTC_MODE1_INTENSET_CMP3 (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)
|
| 1000 | #define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
|
| 1001 | #define RTC_MODE1_INTENSET_CMP_Msk (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)
|
| 1002 | #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
|
| 1003 | #define RTC_MODE1_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTENSET) Tamper Enable */
|
| 1004 | #define RTC_MODE1_INTENSET_TAMPER (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)
|
| 1005 | #define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
|
| 1006 | #define RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
|
| 1007 | #define RTC_MODE1_INTENSET_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTENSET) MASK Register */
|
| 1008 |
|
| 1009 | /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */
|
| 1010 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1011 | typedef union {
|
| 1012 | struct {
|
| 1013 | uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */
|
| 1014 | uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */
|
| 1015 | uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */
|
| 1016 | uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */
|
| 1017 | uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */
|
| 1018 | uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */
|
| 1019 | uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */
|
| 1020 | uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */
|
| 1021 | uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */
|
| 1022 | uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */
|
| 1023 | uint16_t :4; /*!< bit: 10..13 Reserved */
|
| 1024 | uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */
|
| 1025 | uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */
|
| 1026 | } bit; /*!< Structure used for bit access */
|
| 1027 | struct {
|
| 1028 | uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */
|
| 1029 | uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */
|
| 1030 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 1031 | } vec; /*!< Structure used for vec access */
|
| 1032 | uint16_t reg; /*!< Type used for register access */
|
| 1033 | } RTC_MODE2_INTENSET_Type;
|
| 1034 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1035 |
|
| 1036 | #define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
|
| 1037 | #define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
|
| 1038 |
|
| 1039 | #define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */
|
| 1040 | #define RTC_MODE2_INTENSET_PER0 (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)
|
| 1041 | #define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */
|
| 1042 | #define RTC_MODE2_INTENSET_PER1 (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)
|
| 1043 | #define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */
|
| 1044 | #define RTC_MODE2_INTENSET_PER2 (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)
|
| 1045 | #define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */
|
| 1046 | #define RTC_MODE2_INTENSET_PER3 (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)
|
| 1047 | #define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */
|
| 1048 | #define RTC_MODE2_INTENSET_PER4 (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)
|
| 1049 | #define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */
|
| 1050 | #define RTC_MODE2_INTENSET_PER5 (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)
|
| 1051 | #define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */
|
| 1052 | #define RTC_MODE2_INTENSET_PER6 (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)
|
| 1053 | #define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */
|
| 1054 | #define RTC_MODE2_INTENSET_PER7 (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)
|
| 1055 | #define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */
|
| 1056 | #define RTC_MODE2_INTENSET_PER_Msk (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)
|
| 1057 | #define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))
|
| 1058 | #define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
|
| 1059 | #define RTC_MODE2_INTENSET_ALARM0 (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)
|
| 1060 | #define RTC_MODE2_INTENSET_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable */
|
| 1061 | #define RTC_MODE2_INTENSET_ALARM1 (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)
|
| 1062 | #define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
|
| 1063 | #define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)
|
| 1064 | #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
|
| 1065 | #define RTC_MODE2_INTENSET_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTENSET) Tamper Enable */
|
| 1066 | #define RTC_MODE2_INTENSET_TAMPER (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)
|
| 1067 | #define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
|
| 1068 | #define RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
|
| 1069 | #define RTC_MODE2_INTENSET_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTENSET) MASK Register */
|
| 1070 |
|
| 1071 | /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
|
| 1072 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1073 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 1074 | struct {
|
| 1075 | __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
|
| 1076 | __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
|
| 1077 | __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
|
| 1078 | __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
|
| 1079 | __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
|
| 1080 | __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
|
| 1081 | __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
|
| 1082 | __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
|
| 1083 | __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
|
| 1084 | __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
|
| 1085 | __I uint16_t :4; /*!< bit: 10..13 Reserved */
|
| 1086 | __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
|
| 1087 | __I uint16_t OVF:1; /*!< bit: 15 Overflow */
|
| 1088 | } bit; /*!< Structure used for bit access */
|
| 1089 | struct {
|
| 1090 | __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
|
| 1091 | __I uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */
|
| 1092 | __I uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 1093 | } vec; /*!< Structure used for vec access */
|
| 1094 | uint16_t reg; /*!< Type used for register access */
|
| 1095 | } RTC_MODE0_INTFLAG_Type;
|
| 1096 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1097 |
|
| 1098 | #define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
|
| 1099 | #define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
|
| 1100 |
|
| 1101 | #define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */
|
| 1102 | #define RTC_MODE0_INTFLAG_PER0 (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)
|
| 1103 | #define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */
|
| 1104 | #define RTC_MODE0_INTFLAG_PER1 (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)
|
| 1105 | #define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */
|
| 1106 | #define RTC_MODE0_INTFLAG_PER2 (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)
|
| 1107 | #define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */
|
| 1108 | #define RTC_MODE0_INTFLAG_PER3 (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)
|
| 1109 | #define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */
|
| 1110 | #define RTC_MODE0_INTFLAG_PER4 (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)
|
| 1111 | #define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */
|
| 1112 | #define RTC_MODE0_INTFLAG_PER5 (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)
|
| 1113 | #define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */
|
| 1114 | #define RTC_MODE0_INTFLAG_PER6 (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)
|
| 1115 | #define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */
|
| 1116 | #define RTC_MODE0_INTFLAG_PER7 (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)
|
| 1117 | #define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */
|
| 1118 | #define RTC_MODE0_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)
|
| 1119 | #define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))
|
| 1120 | #define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
|
| 1121 | #define RTC_MODE0_INTFLAG_CMP0 (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)
|
| 1122 | #define RTC_MODE0_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE0_INTFLAG) Compare 1 */
|
| 1123 | #define RTC_MODE0_INTFLAG_CMP1 (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)
|
| 1124 | #define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
|
| 1125 | #define RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)
|
| 1126 | #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
|
| 1127 | #define RTC_MODE0_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE0_INTFLAG) Tamper */
|
| 1128 | #define RTC_MODE0_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)
|
| 1129 | #define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
|
| 1130 | #define RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
|
| 1131 | #define RTC_MODE0_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
|
| 1132 |
|
| 1133 | /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
|
| 1134 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1135 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 1136 | struct {
|
| 1137 | __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
|
| 1138 | __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
|
| 1139 | __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
|
| 1140 | __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
|
| 1141 | __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
|
| 1142 | __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
|
| 1143 | __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
|
| 1144 | __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
|
| 1145 | __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
|
| 1146 | __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
|
| 1147 | __I uint16_t CMP2:1; /*!< bit: 10 Compare 2 */
|
| 1148 | __I uint16_t CMP3:1; /*!< bit: 11 Compare 3 */
|
| 1149 | __I uint16_t :2; /*!< bit: 12..13 Reserved */
|
| 1150 | __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
|
| 1151 | __I uint16_t OVF:1; /*!< bit: 15 Overflow */
|
| 1152 | } bit; /*!< Structure used for bit access */
|
| 1153 | struct {
|
| 1154 | __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
|
| 1155 | __I uint16_t CMP:4; /*!< bit: 8..11 Compare x */
|
| 1156 | __I uint16_t :4; /*!< bit: 12..15 Reserved */
|
| 1157 | } vec; /*!< Structure used for vec access */
|
| 1158 | uint16_t reg; /*!< Type used for register access */
|
| 1159 | } RTC_MODE1_INTFLAG_Type;
|
| 1160 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1161 |
|
| 1162 | #define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
|
| 1163 | #define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
|
| 1164 |
|
| 1165 | #define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */
|
| 1166 | #define RTC_MODE1_INTFLAG_PER0 (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)
|
| 1167 | #define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */
|
| 1168 | #define RTC_MODE1_INTFLAG_PER1 (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)
|
| 1169 | #define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */
|
| 1170 | #define RTC_MODE1_INTFLAG_PER2 (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)
|
| 1171 | #define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */
|
| 1172 | #define RTC_MODE1_INTFLAG_PER3 (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)
|
| 1173 | #define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */
|
| 1174 | #define RTC_MODE1_INTFLAG_PER4 (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)
|
| 1175 | #define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */
|
| 1176 | #define RTC_MODE1_INTFLAG_PER5 (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)
|
| 1177 | #define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */
|
| 1178 | #define RTC_MODE1_INTFLAG_PER6 (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)
|
| 1179 | #define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */
|
| 1180 | #define RTC_MODE1_INTFLAG_PER7 (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)
|
| 1181 | #define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */
|
| 1182 | #define RTC_MODE1_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)
|
| 1183 | #define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))
|
| 1184 | #define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
|
| 1185 | #define RTC_MODE1_INTFLAG_CMP0 (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)
|
| 1186 | #define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
|
| 1187 | #define RTC_MODE1_INTFLAG_CMP1 (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)
|
| 1188 | #define RTC_MODE1_INTFLAG_CMP2_Pos 10 /**< \brief (RTC_MODE1_INTFLAG) Compare 2 */
|
| 1189 | #define RTC_MODE1_INTFLAG_CMP2 (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)
|
| 1190 | #define RTC_MODE1_INTFLAG_CMP3_Pos 11 /**< \brief (RTC_MODE1_INTFLAG) Compare 3 */
|
| 1191 | #define RTC_MODE1_INTFLAG_CMP3 (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)
|
| 1192 | #define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
|
| 1193 | #define RTC_MODE1_INTFLAG_CMP_Msk (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)
|
| 1194 | #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
|
| 1195 | #define RTC_MODE1_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE1_INTFLAG) Tamper */
|
| 1196 | #define RTC_MODE1_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)
|
| 1197 | #define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
|
| 1198 | #define RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
|
| 1199 | #define RTC_MODE1_INTFLAG_MASK _U_(0xCFFF) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
|
| 1200 |
|
| 1201 | /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
|
| 1202 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1203 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 1204 | struct {
|
| 1205 | __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
|
| 1206 | __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
|
| 1207 | __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
|
| 1208 | __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
|
| 1209 | __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
|
| 1210 | __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
|
| 1211 | __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
|
| 1212 | __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
|
| 1213 | __I uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */
|
| 1214 | __I uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 */
|
| 1215 | __I uint16_t :4; /*!< bit: 10..13 Reserved */
|
| 1216 | __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */
|
| 1217 | __I uint16_t OVF:1; /*!< bit: 15 Overflow */
|
| 1218 | } bit; /*!< Structure used for bit access */
|
| 1219 | struct {
|
| 1220 | __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */
|
| 1221 | __I uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x */
|
| 1222 | __I uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 1223 | } vec; /*!< Structure used for vec access */
|
| 1224 | uint16_t reg; /*!< Type used for register access */
|
| 1225 | } RTC_MODE2_INTFLAG_Type;
|
| 1226 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1227 |
|
| 1228 | #define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
|
| 1229 | #define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
|
| 1230 |
|
| 1231 | #define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */
|
| 1232 | #define RTC_MODE2_INTFLAG_PER0 (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)
|
| 1233 | #define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */
|
| 1234 | #define RTC_MODE2_INTFLAG_PER1 (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)
|
| 1235 | #define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */
|
| 1236 | #define RTC_MODE2_INTFLAG_PER2 (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)
|
| 1237 | #define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */
|
| 1238 | #define RTC_MODE2_INTFLAG_PER3 (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)
|
| 1239 | #define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */
|
| 1240 | #define RTC_MODE2_INTFLAG_PER4 (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)
|
| 1241 | #define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */
|
| 1242 | #define RTC_MODE2_INTFLAG_PER5 (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)
|
| 1243 | #define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */
|
| 1244 | #define RTC_MODE2_INTFLAG_PER6 (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)
|
| 1245 | #define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */
|
| 1246 | #define RTC_MODE2_INTFLAG_PER7 (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)
|
| 1247 | #define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */
|
| 1248 | #define RTC_MODE2_INTFLAG_PER_Msk (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)
|
| 1249 | #define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))
|
| 1250 | #define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
|
| 1251 | #define RTC_MODE2_INTFLAG_ALARM0 (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)
|
| 1252 | #define RTC_MODE2_INTFLAG_ALARM1_Pos 9 /**< \brief (RTC_MODE2_INTFLAG) Alarm 1 */
|
| 1253 | #define RTC_MODE2_INTFLAG_ALARM1 (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)
|
| 1254 | #define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
|
| 1255 | #define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)
|
| 1256 | #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
|
| 1257 | #define RTC_MODE2_INTFLAG_TAMPER_Pos 14 /**< \brief (RTC_MODE2_INTFLAG) Tamper */
|
| 1258 | #define RTC_MODE2_INTFLAG_TAMPER (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)
|
| 1259 | #define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
|
| 1260 | #define RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
|
| 1261 | #define RTC_MODE2_INTFLAG_MASK _U_(0xC3FF) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
|
| 1262 |
|
| 1263 | /* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */
|
| 1264 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1265 | typedef union {
|
| 1266 | struct {
|
| 1267 | uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
|
| 1268 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
| 1269 | } bit; /*!< Structure used for bit access */
|
| 1270 | uint8_t reg; /*!< Type used for register access */
|
| 1271 | } RTC_DBGCTRL_Type;
|
| 1272 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1273 |
|
| 1274 | #define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */
|
| 1275 | #define RTC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
|
| 1276 |
|
| 1277 | #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
|
| 1278 | #define RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
|
| 1279 | #define RTC_DBGCTRL_MASK _U_(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */
|
| 1280 |
|
| 1281 | /* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */
|
| 1282 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1283 | typedef union {
|
| 1284 | struct {
|
| 1285 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */
|
| 1286 | uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
|
| 1287 | uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
|
| 1288 | uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
|
| 1289 | uint32_t :1; /*!< bit: 4 Reserved */
|
| 1290 | uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
|
| 1291 | uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
|
| 1292 | uint32_t :8; /*!< bit: 7..14 Reserved */
|
| 1293 | uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
|
| 1294 | uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
|
| 1295 | uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
|
| 1296 | uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
|
| 1297 | uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
|
| 1298 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 1299 | } bit; /*!< Structure used for bit access */
|
| 1300 | struct {
|
| 1301 | uint32_t :5; /*!< bit: 0.. 4 Reserved */
|
| 1302 | uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */
|
| 1303 | uint32_t :9; /*!< bit: 7..15 Reserved */
|
| 1304 | uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
|
| 1305 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 1306 | } vec; /*!< Structure used for vec access */
|
| 1307 | uint32_t reg; /*!< Type used for register access */
|
| 1308 | } RTC_MODE0_SYNCBUSY_Type;
|
| 1309 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1310 |
|
| 1311 | #define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */
|
| 1312 | #define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */
|
| 1313 |
|
| 1314 | #define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */
|
| 1315 | #define RTC_MODE0_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)
|
| 1316 | #define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */
|
| 1317 | #define RTC_MODE0_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)
|
| 1318 | #define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */
|
| 1319 | #define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)
|
| 1320 | #define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */
|
| 1321 | #define RTC_MODE0_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)
|
| 1322 | #define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */
|
| 1323 | #define RTC_MODE0_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)
|
| 1324 | #define RTC_MODE0_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy */
|
| 1325 | #define RTC_MODE0_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)
|
| 1326 | #define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */
|
| 1327 | #define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)
|
| 1328 | #define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))
|
| 1329 | #define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy */
|
| 1330 | #define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)
|
| 1331 | #define RTC_MODE0_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy */
|
| 1332 | #define RTC_MODE0_SYNCBUSY_GP0 (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)
|
| 1333 | #define RTC_MODE0_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy */
|
| 1334 | #define RTC_MODE0_SYNCBUSY_GP1 (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)
|
| 1335 | #define RTC_MODE0_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy */
|
| 1336 | #define RTC_MODE0_SYNCBUSY_GP2 (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)
|
| 1337 | #define RTC_MODE0_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy */
|
| 1338 | #define RTC_MODE0_SYNCBUSY_GP3 (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)
|
| 1339 | #define RTC_MODE0_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose x Register Busy */
|
| 1340 | #define RTC_MODE0_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)
|
| 1341 | #define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))
|
| 1342 | #define RTC_MODE0_SYNCBUSY_MASK _U_(0x000F806F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */
|
| 1343 |
|
| 1344 | /* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */
|
| 1345 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1346 | typedef union {
|
| 1347 | struct {
|
| 1348 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
|
| 1349 | uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
|
| 1350 | uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
|
| 1351 | uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */
|
| 1352 | uint32_t PER:1; /*!< bit: 4 PER Register Busy */
|
| 1353 | uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */
|
| 1354 | uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */
|
| 1355 | uint32_t COMP2:1; /*!< bit: 7 COMP 2 Register Busy */
|
| 1356 | uint32_t COMP3:1; /*!< bit: 8 COMP 3 Register Busy */
|
| 1357 | uint32_t :6; /*!< bit: 9..14 Reserved */
|
| 1358 | uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */
|
| 1359 | uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
|
| 1360 | uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
|
| 1361 | uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
|
| 1362 | uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
|
| 1363 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 1364 | } bit; /*!< Structure used for bit access */
|
| 1365 | struct {
|
| 1366 | uint32_t :5; /*!< bit: 0.. 4 Reserved */
|
| 1367 | uint32_t COMP:4; /*!< bit: 5.. 8 COMP x Register Busy */
|
| 1368 | uint32_t :7; /*!< bit: 9..15 Reserved */
|
| 1369 | uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
|
| 1370 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 1371 | } vec; /*!< Structure used for vec access */
|
| 1372 | uint32_t reg; /*!< Type used for register access */
|
| 1373 | } RTC_MODE1_SYNCBUSY_Type;
|
| 1374 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1375 |
|
| 1376 | #define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */
|
| 1377 | #define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */
|
| 1378 |
|
| 1379 | #define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */
|
| 1380 | #define RTC_MODE1_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)
|
| 1381 | #define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */
|
| 1382 | #define RTC_MODE1_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)
|
| 1383 | #define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */
|
| 1384 | #define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)
|
| 1385 | #define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */
|
| 1386 | #define RTC_MODE1_SYNCBUSY_COUNT (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)
|
| 1387 | #define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */
|
| 1388 | #define RTC_MODE1_SYNCBUSY_PER (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)
|
| 1389 | #define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */
|
| 1390 | #define RTC_MODE1_SYNCBUSY_COMP0 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)
|
| 1391 | #define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */
|
| 1392 | #define RTC_MODE1_SYNCBUSY_COMP1 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)
|
| 1393 | #define RTC_MODE1_SYNCBUSY_COMP2_Pos 7 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy */
|
| 1394 | #define RTC_MODE1_SYNCBUSY_COMP2 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)
|
| 1395 | #define RTC_MODE1_SYNCBUSY_COMP3_Pos 8 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy */
|
| 1396 | #define RTC_MODE1_SYNCBUSY_COMP3 (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)
|
| 1397 | #define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */
|
| 1398 | #define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)
|
| 1399 | #define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))
|
| 1400 | #define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy */
|
| 1401 | #define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)
|
| 1402 | #define RTC_MODE1_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy */
|
| 1403 | #define RTC_MODE1_SYNCBUSY_GP0 (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)
|
| 1404 | #define RTC_MODE1_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy */
|
| 1405 | #define RTC_MODE1_SYNCBUSY_GP1 (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)
|
| 1406 | #define RTC_MODE1_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy */
|
| 1407 | #define RTC_MODE1_SYNCBUSY_GP2 (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)
|
| 1408 | #define RTC_MODE1_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy */
|
| 1409 | #define RTC_MODE1_SYNCBUSY_GP3 (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)
|
| 1410 | #define RTC_MODE1_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose x Register Busy */
|
| 1411 | #define RTC_MODE1_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)
|
| 1412 | #define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))
|
| 1413 | #define RTC_MODE1_SYNCBUSY_MASK _U_(0x000F81FF) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */
|
| 1414 |
|
| 1415 | /* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */
|
| 1416 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1417 | typedef union {
|
| 1418 | struct {
|
| 1419 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */
|
| 1420 | uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */
|
| 1421 | uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */
|
| 1422 | uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */
|
| 1423 | uint32_t :1; /*!< bit: 4 Reserved */
|
| 1424 | uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */
|
| 1425 | uint32_t ALARM1:1; /*!< bit: 6 ALARM 1 Register Busy */
|
| 1426 | uint32_t :4; /*!< bit: 7..10 Reserved */
|
| 1427 | uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */
|
| 1428 | uint32_t MASK1:1; /*!< bit: 12 MASK 1 Register Busy */
|
| 1429 | uint32_t :2; /*!< bit: 13..14 Reserved */
|
| 1430 | uint32_t CLOCKSYNC:1; /*!< bit: 15 Clock Synchronization Enable Bit Busy */
|
| 1431 | uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */
|
| 1432 | uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */
|
| 1433 | uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */
|
| 1434 | uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */
|
| 1435 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 1436 | } bit; /*!< Structure used for bit access */
|
| 1437 | struct {
|
| 1438 | uint32_t :5; /*!< bit: 0.. 4 Reserved */
|
| 1439 | uint32_t ALARM:2; /*!< bit: 5.. 6 ALARM x Register Busy */
|
| 1440 | uint32_t :4; /*!< bit: 7..10 Reserved */
|
| 1441 | uint32_t MASK:2; /*!< bit: 11..12 MASK x Register Busy */
|
| 1442 | uint32_t :3; /*!< bit: 13..15 Reserved */
|
| 1443 | uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */
|
| 1444 | uint32_t :12; /*!< bit: 20..31 Reserved */
|
| 1445 | } vec; /*!< Structure used for vec access */
|
| 1446 | uint32_t reg; /*!< Type used for register access */
|
| 1447 | } RTC_MODE2_SYNCBUSY_Type;
|
| 1448 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1449 |
|
| 1450 | #define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */
|
| 1451 | #define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */
|
| 1452 |
|
| 1453 | #define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */
|
| 1454 | #define RTC_MODE2_SYNCBUSY_SWRST (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)
|
| 1455 | #define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */
|
| 1456 | #define RTC_MODE2_SYNCBUSY_ENABLE (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)
|
| 1457 | #define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */
|
| 1458 | #define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)
|
| 1459 | #define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */
|
| 1460 | #define RTC_MODE2_SYNCBUSY_CLOCK (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)
|
| 1461 | #define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */
|
| 1462 | #define RTC_MODE2_SYNCBUSY_ALARM0 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)
|
| 1463 | #define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy */
|
| 1464 | #define RTC_MODE2_SYNCBUSY_ALARM1 (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)
|
| 1465 | #define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */
|
| 1466 | #define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)
|
| 1467 | #define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))
|
| 1468 | #define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */
|
| 1469 | #define RTC_MODE2_SYNCBUSY_MASK0 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)
|
| 1470 | #define RTC_MODE2_SYNCBUSY_MASK1_Pos 12 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy */
|
| 1471 | #define RTC_MODE2_SYNCBUSY_MASK1 (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)
|
| 1472 | #define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */
|
| 1473 | #define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)
|
| 1474 | #define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))
|
| 1475 | #define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy */
|
| 1476 | #define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)
|
| 1477 | #define RTC_MODE2_SYNCBUSY_GP0_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy */
|
| 1478 | #define RTC_MODE2_SYNCBUSY_GP0 (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)
|
| 1479 | #define RTC_MODE2_SYNCBUSY_GP1_Pos 17 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy */
|
| 1480 | #define RTC_MODE2_SYNCBUSY_GP1 (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)
|
| 1481 | #define RTC_MODE2_SYNCBUSY_GP2_Pos 18 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy */
|
| 1482 | #define RTC_MODE2_SYNCBUSY_GP2 (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)
|
| 1483 | #define RTC_MODE2_SYNCBUSY_GP3_Pos 19 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy */
|
| 1484 | #define RTC_MODE2_SYNCBUSY_GP3 (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)
|
| 1485 | #define RTC_MODE2_SYNCBUSY_GP_Pos 16 /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose x Register Busy */
|
| 1486 | #define RTC_MODE2_SYNCBUSY_GP_Msk (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)
|
| 1487 | #define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))
|
| 1488 | #define RTC_MODE2_SYNCBUSY_MASK_ _U_(0x000F986F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */
|
| 1489 |
|
| 1490 | /* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */
|
| 1491 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1492 | typedef union {
|
| 1493 | struct {
|
| 1494 | uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
|
| 1495 | uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
|
| 1496 | } bit; /*!< Structure used for bit access */
|
| 1497 | uint8_t reg; /*!< Type used for register access */
|
| 1498 | } RTC_FREQCORR_Type;
|
| 1499 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1500 |
|
| 1501 | #define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */
|
| 1502 | #define RTC_FREQCORR_RESETVALUE _U_(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
|
| 1503 |
|
| 1504 | #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
|
| 1505 | #define RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)
|
| 1506 | #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
|
| 1507 | #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
|
| 1508 | #define RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)
|
| 1509 | #define RTC_FREQCORR_MASK _U_(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */
|
| 1510 |
|
| 1511 | /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */
|
| 1512 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1513 | typedef union {
|
| 1514 | struct {
|
| 1515 | uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
|
| 1516 | } bit; /*!< Structure used for bit access */
|
| 1517 | uint32_t reg; /*!< Type used for register access */
|
| 1518 | } RTC_MODE0_COUNT_Type;
|
| 1519 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1520 |
|
| 1521 | #define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
|
| 1522 | #define RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
|
| 1523 |
|
| 1524 | #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
|
| 1525 | #define RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
|
| 1526 | #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
|
| 1527 | #define RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
|
| 1528 |
|
| 1529 | /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */
|
| 1530 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1531 | typedef union {
|
| 1532 | struct {
|
| 1533 | uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
|
| 1534 | } bit; /*!< Structure used for bit access */
|
| 1535 | uint16_t reg; /*!< Type used for register access */
|
| 1536 | } RTC_MODE1_COUNT_Type;
|
| 1537 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1538 |
|
| 1539 | #define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
|
| 1540 | #define RTC_MODE1_COUNT_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
|
| 1541 |
|
| 1542 | #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
|
| 1543 | #define RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
|
| 1544 | #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
|
| 1545 | #define RTC_MODE1_COUNT_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */
|
| 1546 |
|
| 1547 | /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */
|
| 1548 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1549 | typedef union {
|
| 1550 | struct {
|
| 1551 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
|
| 1552 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
|
| 1553 | uint32_t HOUR:5; /*!< bit: 12..16 Hour */
|
| 1554 | uint32_t DAY:5; /*!< bit: 17..21 Day */
|
| 1555 | uint32_t MONTH:4; /*!< bit: 22..25 Month */
|
| 1556 | uint32_t YEAR:6; /*!< bit: 26..31 Year */
|
| 1557 | } bit; /*!< Structure used for bit access */
|
| 1558 | uint32_t reg; /*!< Type used for register access */
|
| 1559 | } RTC_MODE2_CLOCK_Type;
|
| 1560 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1561 |
|
| 1562 | #define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
|
| 1563 | #define RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
|
| 1564 |
|
| 1565 | #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
|
| 1566 | #define RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
|
| 1567 | #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
|
| 1568 | #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
|
| 1569 | #define RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
|
| 1570 | #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
|
| 1571 | #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
|
| 1572 | #define RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
|
| 1573 | #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
|
| 1574 | #define RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
|
| 1575 | #define RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
|
| 1576 | #define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
|
| 1577 | #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
|
| 1578 | #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
|
| 1579 | #define RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
|
| 1580 | #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
|
| 1581 | #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
|
| 1582 | #define RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
|
| 1583 | #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
|
| 1584 | #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
|
| 1585 | #define RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
|
| 1586 | #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
|
| 1587 | #define RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
|
| 1588 |
|
| 1589 | /* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */
|
| 1590 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1591 | typedef union {
|
| 1592 | struct {
|
| 1593 | uint16_t PER:16; /*!< bit: 0..15 Counter Period */
|
| 1594 | } bit; /*!< Structure used for bit access */
|
| 1595 | uint16_t reg; /*!< Type used for register access */
|
| 1596 | } RTC_MODE1_PER_Type;
|
| 1597 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1598 |
|
| 1599 | #define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
|
| 1600 | #define RTC_MODE1_PER_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
|
| 1601 |
|
| 1602 | #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
|
| 1603 | #define RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)
|
| 1604 | #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
|
| 1605 | #define RTC_MODE1_PER_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */
|
| 1606 |
|
| 1607 | /* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */
|
| 1608 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1609 | typedef union {
|
| 1610 | struct {
|
| 1611 | uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
|
| 1612 | } bit; /*!< Structure used for bit access */
|
| 1613 | uint32_t reg; /*!< Type used for register access */
|
| 1614 | } RTC_MODE0_COMP_Type;
|
| 1615 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1616 |
|
| 1617 | #define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
|
| 1618 | #define RTC_MODE0_COMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
|
| 1619 |
|
| 1620 | #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
|
| 1621 | #define RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
|
| 1622 | #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
|
| 1623 | #define RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
|
| 1624 |
|
| 1625 | /* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */
|
| 1626 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1627 | typedef union {
|
| 1628 | struct {
|
| 1629 | uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
|
| 1630 | } bit; /*!< Structure used for bit access */
|
| 1631 | uint16_t reg; /*!< Type used for register access */
|
| 1632 | } RTC_MODE1_COMP_Type;
|
| 1633 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1634 |
|
| 1635 | #define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
|
| 1636 | #define RTC_MODE1_COMP_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
|
| 1637 |
|
| 1638 | #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
|
| 1639 | #define RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
|
| 1640 | #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
|
| 1641 | #define RTC_MODE1_COMP_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */
|
| 1642 |
|
| 1643 | /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
|
| 1644 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1645 | typedef union {
|
| 1646 | struct {
|
| 1647 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
|
| 1648 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
|
| 1649 | uint32_t HOUR:5; /*!< bit: 12..16 Hour */
|
| 1650 | uint32_t DAY:5; /*!< bit: 17..21 Day */
|
| 1651 | uint32_t MONTH:4; /*!< bit: 22..25 Month */
|
| 1652 | uint32_t YEAR:6; /*!< bit: 26..31 Year */
|
| 1653 | } bit; /*!< Structure used for bit access */
|
| 1654 | uint32_t reg; /*!< Type used for register access */
|
| 1655 | } RTC_MODE2_ALARM_Type;
|
| 1656 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1657 |
|
| 1658 | #define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
|
| 1659 | #define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
|
| 1660 |
|
| 1661 | #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
|
| 1662 | #define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
|
| 1663 | #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
|
| 1664 | #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
|
| 1665 | #define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
|
| 1666 | #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
|
| 1667 | #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
|
| 1668 | #define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
|
| 1669 | #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
|
| 1670 | #define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */
|
| 1671 | #define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
|
| 1672 | #define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)
|
| 1673 | #define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)
|
| 1674 | #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
|
| 1675 | #define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
|
| 1676 | #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
|
| 1677 | #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
|
| 1678 | #define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
|
| 1679 | #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
|
| 1680 | #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
|
| 1681 | #define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
|
| 1682 | #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
|
| 1683 | #define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
|
| 1684 |
|
| 1685 | /* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
|
| 1686 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1687 | typedef union {
|
| 1688 | struct {
|
| 1689 | uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
|
| 1690 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
| 1691 | } bit; /*!< Structure used for bit access */
|
| 1692 | uint8_t reg; /*!< Type used for register access */
|
| 1693 | } RTC_MODE2_MASK_Type;
|
| 1694 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1695 |
|
| 1696 | #define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
|
| 1697 | #define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
|
| 1698 |
|
| 1699 | #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
|
| 1700 | #define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)
|
| 1701 | #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
|
| 1702 | #define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
|
| 1703 | #define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */
|
| 1704 | #define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
|
| 1705 | #define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
|
| 1706 | #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
|
| 1707 | #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
|
| 1708 | #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
|
| 1709 | #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1710 | #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1711 | #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1712 | #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1713 | #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1714 | #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1715 | #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
|
| 1716 | #define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */
|
| 1717 |
|
| 1718 | /* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
|
| 1719 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1720 | typedef union {
|
| 1721 | struct {
|
| 1722 | uint32_t GP:32; /*!< bit: 0..31 General Purpose */
|
| 1723 | } bit; /*!< Structure used for bit access */
|
| 1724 | uint32_t reg; /*!< Type used for register access */
|
| 1725 | } RTC_GP_Type;
|
| 1726 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1727 |
|
| 1728 | #define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */
|
| 1729 | #define RTC_GP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */
|
| 1730 |
|
| 1731 | #define RTC_GP_GP_Pos 0 /**< \brief (RTC_GP) General Purpose */
|
| 1732 | #define RTC_GP_GP_Msk (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)
|
| 1733 | #define RTC_GP_GP(value) (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))
|
| 1734 | #define RTC_GP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */
|
| 1735 |
|
| 1736 | /* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
|
| 1737 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1738 | typedef union {
|
| 1739 | struct {
|
| 1740 | uint32_t IN0ACT:2; /*!< bit: 0.. 1 Tamper Input 0 Action */
|
| 1741 | uint32_t IN1ACT:2; /*!< bit: 2.. 3 Tamper Input 1 Action */
|
| 1742 | uint32_t IN2ACT:2; /*!< bit: 4.. 5 Tamper Input 2 Action */
|
| 1743 | uint32_t IN3ACT:2; /*!< bit: 6.. 7 Tamper Input 3 Action */
|
| 1744 | uint32_t IN4ACT:2; /*!< bit: 8.. 9 Tamper Input 4 Action */
|
| 1745 | uint32_t :6; /*!< bit: 10..15 Reserved */
|
| 1746 | uint32_t TAMLVL0:1; /*!< bit: 16 Tamper Level Select 0 */
|
| 1747 | uint32_t TAMLVL1:1; /*!< bit: 17 Tamper Level Select 1 */
|
| 1748 | uint32_t TAMLVL2:1; /*!< bit: 18 Tamper Level Select 2 */
|
| 1749 | uint32_t TAMLVL3:1; /*!< bit: 19 Tamper Level Select 3 */
|
| 1750 | uint32_t TAMLVL4:1; /*!< bit: 20 Tamper Level Select 4 */
|
| 1751 | uint32_t :3; /*!< bit: 21..23 Reserved */
|
| 1752 | uint32_t DEBNC0:1; /*!< bit: 24 Debouncer Enable 0 */
|
| 1753 | uint32_t DEBNC1:1; /*!< bit: 25 Debouncer Enable 1 */
|
| 1754 | uint32_t DEBNC2:1; /*!< bit: 26 Debouncer Enable 2 */
|
| 1755 | uint32_t DEBNC3:1; /*!< bit: 27 Debouncer Enable 3 */
|
| 1756 | uint32_t DEBNC4:1; /*!< bit: 28 Debouncer Enable 4 */
|
| 1757 | uint32_t :3; /*!< bit: 29..31 Reserved */
|
| 1758 | } bit; /*!< Structure used for bit access */
|
| 1759 | struct {
|
| 1760 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
| 1761 | uint32_t TAMLVL:5; /*!< bit: 16..20 Tamper Level Select x */
|
| 1762 | uint32_t :3; /*!< bit: 21..23 Reserved */
|
| 1763 | uint32_t DEBNC:5; /*!< bit: 24..28 Debouncer Enable x */
|
| 1764 | uint32_t :3; /*!< bit: 29..31 Reserved */
|
| 1765 | } vec; /*!< Structure used for vec access */
|
| 1766 | uint32_t reg; /*!< Type used for register access */
|
| 1767 | } RTC_TAMPCTRL_Type;
|
| 1768 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1769 |
|
| 1770 | #define RTC_TAMPCTRL_OFFSET 0x60 /**< \brief (RTC_TAMPCTRL offset) Tamper Control */
|
| 1771 | #define RTC_TAMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPCTRL reset_value) Tamper Control */
|
| 1772 |
|
| 1773 | #define RTC_TAMPCTRL_IN0ACT_Pos 0 /**< \brief (RTC_TAMPCTRL) Tamper Input 0 Action */
|
| 1774 | #define RTC_TAMPCTRL_IN0ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)
|
| 1775 | #define RTC_TAMPCTRL_IN0ACT(value) (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
|
| 1776 | #define RTC_TAMPCTRL_IN0ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
|
| 1777 | #define RTC_TAMPCTRL_IN0ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
|
| 1778 | #define RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
|
| 1779 | #define RTC_TAMPCTRL_IN0ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN0 to OUT */
|
| 1780 | #define RTC_TAMPCTRL_IN0ACT_OFF (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos)
|
| 1781 | #define RTC_TAMPCTRL_IN0ACT_WAKE (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
|
| 1782 | #define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
|
| 1783 | #define RTC_TAMPCTRL_IN0ACT_ACTL (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos)
|
| 1784 | #define RTC_TAMPCTRL_IN1ACT_Pos 2 /**< \brief (RTC_TAMPCTRL) Tamper Input 1 Action */
|
| 1785 | #define RTC_TAMPCTRL_IN1ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)
|
| 1786 | #define RTC_TAMPCTRL_IN1ACT(value) (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
|
| 1787 | #define RTC_TAMPCTRL_IN1ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
|
| 1788 | #define RTC_TAMPCTRL_IN1ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
|
| 1789 | #define RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
|
| 1790 | #define RTC_TAMPCTRL_IN1ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN1 to OUT */
|
| 1791 | #define RTC_TAMPCTRL_IN1ACT_OFF (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos)
|
| 1792 | #define RTC_TAMPCTRL_IN1ACT_WAKE (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
|
| 1793 | #define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
|
| 1794 | #define RTC_TAMPCTRL_IN1ACT_ACTL (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos)
|
| 1795 | #define RTC_TAMPCTRL_IN2ACT_Pos 4 /**< \brief (RTC_TAMPCTRL) Tamper Input 2 Action */
|
| 1796 | #define RTC_TAMPCTRL_IN2ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)
|
| 1797 | #define RTC_TAMPCTRL_IN2ACT(value) (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
|
| 1798 | #define RTC_TAMPCTRL_IN2ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
|
| 1799 | #define RTC_TAMPCTRL_IN2ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
|
| 1800 | #define RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
|
| 1801 | #define RTC_TAMPCTRL_IN2ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN2 to OUT */
|
| 1802 | #define RTC_TAMPCTRL_IN2ACT_OFF (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos)
|
| 1803 | #define RTC_TAMPCTRL_IN2ACT_WAKE (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
|
| 1804 | #define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
|
| 1805 | #define RTC_TAMPCTRL_IN2ACT_ACTL (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos)
|
| 1806 | #define RTC_TAMPCTRL_IN3ACT_Pos 6 /**< \brief (RTC_TAMPCTRL) Tamper Input 3 Action */
|
| 1807 | #define RTC_TAMPCTRL_IN3ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)
|
| 1808 | #define RTC_TAMPCTRL_IN3ACT(value) (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
|
| 1809 | #define RTC_TAMPCTRL_IN3ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
|
| 1810 | #define RTC_TAMPCTRL_IN3ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
|
| 1811 | #define RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
|
| 1812 | #define RTC_TAMPCTRL_IN3ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN3 to OUT */
|
| 1813 | #define RTC_TAMPCTRL_IN3ACT_OFF (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos)
|
| 1814 | #define RTC_TAMPCTRL_IN3ACT_WAKE (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
|
| 1815 | #define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
|
| 1816 | #define RTC_TAMPCTRL_IN3ACT_ACTL (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos)
|
| 1817 | #define RTC_TAMPCTRL_IN4ACT_Pos 8 /**< \brief (RTC_TAMPCTRL) Tamper Input 4 Action */
|
| 1818 | #define RTC_TAMPCTRL_IN4ACT_Msk (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)
|
| 1819 | #define RTC_TAMPCTRL_IN4ACT(value) (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))
|
| 1820 | #define RTC_TAMPCTRL_IN4ACT_OFF_Val _U_(0x0) /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
|
| 1821 | #define RTC_TAMPCTRL_IN4ACT_WAKE_Val _U_(0x1) /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
|
| 1822 | #define RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2) /**< \brief (RTC_TAMPCTRL) Capture timestamp */
|
| 1823 | #define RTC_TAMPCTRL_IN4ACT_ACTL_Val _U_(0x3) /**< \brief (RTC_TAMPCTRL) Compare IN4 to OUT */
|
| 1824 | #define RTC_TAMPCTRL_IN4ACT_OFF (RTC_TAMPCTRL_IN4ACT_OFF_Val << RTC_TAMPCTRL_IN4ACT_Pos)
|
| 1825 | #define RTC_TAMPCTRL_IN4ACT_WAKE (RTC_TAMPCTRL_IN4ACT_WAKE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
|
| 1826 | #define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
|
| 1827 | #define RTC_TAMPCTRL_IN4ACT_ACTL (RTC_TAMPCTRL_IN4ACT_ACTL_Val << RTC_TAMPCTRL_IN4ACT_Pos)
|
| 1828 | #define RTC_TAMPCTRL_TAMLVL0_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 0 */
|
| 1829 | #define RTC_TAMPCTRL_TAMLVL0 (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)
|
| 1830 | #define RTC_TAMPCTRL_TAMLVL1_Pos 17 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 1 */
|
| 1831 | #define RTC_TAMPCTRL_TAMLVL1 (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)
|
| 1832 | #define RTC_TAMPCTRL_TAMLVL2_Pos 18 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 2 */
|
| 1833 | #define RTC_TAMPCTRL_TAMLVL2 (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)
|
| 1834 | #define RTC_TAMPCTRL_TAMLVL3_Pos 19 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 3 */
|
| 1835 | #define RTC_TAMPCTRL_TAMLVL3 (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)
|
| 1836 | #define RTC_TAMPCTRL_TAMLVL4_Pos 20 /**< \brief (RTC_TAMPCTRL) Tamper Level Select 4 */
|
| 1837 | #define RTC_TAMPCTRL_TAMLVL4 (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)
|
| 1838 | #define RTC_TAMPCTRL_TAMLVL_Pos 16 /**< \brief (RTC_TAMPCTRL) Tamper Level Select x */
|
| 1839 | #define RTC_TAMPCTRL_TAMLVL_Msk (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)
|
| 1840 | #define RTC_TAMPCTRL_TAMLVL(value) (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))
|
| 1841 | #define RTC_TAMPCTRL_DEBNC0_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 0 */
|
| 1842 | #define RTC_TAMPCTRL_DEBNC0 (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)
|
| 1843 | #define RTC_TAMPCTRL_DEBNC1_Pos 25 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 1 */
|
| 1844 | #define RTC_TAMPCTRL_DEBNC1 (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)
|
| 1845 | #define RTC_TAMPCTRL_DEBNC2_Pos 26 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 2 */
|
| 1846 | #define RTC_TAMPCTRL_DEBNC2 (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)
|
| 1847 | #define RTC_TAMPCTRL_DEBNC3_Pos 27 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 3 */
|
| 1848 | #define RTC_TAMPCTRL_DEBNC3 (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)
|
| 1849 | #define RTC_TAMPCTRL_DEBNC4_Pos 28 /**< \brief (RTC_TAMPCTRL) Debouncer Enable 4 */
|
| 1850 | #define RTC_TAMPCTRL_DEBNC4 (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)
|
| 1851 | #define RTC_TAMPCTRL_DEBNC_Pos 24 /**< \brief (RTC_TAMPCTRL) Debouncer Enable x */
|
| 1852 | #define RTC_TAMPCTRL_DEBNC_Msk (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)
|
| 1853 | #define RTC_TAMPCTRL_DEBNC(value) (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))
|
| 1854 | #define RTC_TAMPCTRL_MASK _U_(0x1F1F03FF) /**< \brief (RTC_TAMPCTRL) MASK Register */
|
| 1855 |
|
| 1856 | /* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE0 MODE0 Timestamp -------- */
|
| 1857 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1858 | typedef union {
|
| 1859 | struct {
|
| 1860 | uint32_t COUNT:32; /*!< bit: 0..31 Count Timestamp Value */
|
| 1861 | } bit; /*!< Structure used for bit access */
|
| 1862 | uint32_t reg; /*!< Type used for register access */
|
| 1863 | } RTC_MODE0_TIMESTAMP_Type;
|
| 1864 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1865 |
|
| 1866 | #define RTC_MODE0_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp */
|
| 1867 | #define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp */
|
| 1868 |
|
| 1869 | #define RTC_MODE0_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE0_TIMESTAMP) Count Timestamp Value */
|
| 1870 | #define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)
|
| 1871 | #define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
|
| 1872 | #define RTC_MODE0_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_TIMESTAMP) MASK Register */
|
| 1873 |
|
| 1874 | /* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE1 MODE1 Timestamp -------- */
|
| 1875 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1876 | typedef union {
|
| 1877 | struct {
|
| 1878 | uint32_t COUNT:16; /*!< bit: 0..15 Count Timestamp Value */
|
| 1879 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 1880 | } bit; /*!< Structure used for bit access */
|
| 1881 | uint32_t reg; /*!< Type used for register access */
|
| 1882 | } RTC_MODE1_TIMESTAMP_Type;
|
| 1883 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1884 |
|
| 1885 | #define RTC_MODE1_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp */
|
| 1886 | #define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp */
|
| 1887 |
|
| 1888 | #define RTC_MODE1_TIMESTAMP_COUNT_Pos 0 /**< \brief (RTC_MODE1_TIMESTAMP) Count Timestamp Value */
|
| 1889 | #define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)
|
| 1890 | #define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
|
| 1891 | #define RTC_MODE1_TIMESTAMP_MASK _U_(0x0000FFFF) /**< \brief (RTC_MODE1_TIMESTAMP) MASK Register */
|
| 1892 |
|
| 1893 | /* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE2 MODE2 Timestamp -------- */
|
| 1894 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1895 | typedef union {
|
| 1896 | struct {
|
| 1897 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second Timestamp Value */
|
| 1898 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute Timestamp Value */
|
| 1899 | uint32_t HOUR:5; /*!< bit: 12..16 Hour Timestamp Value */
|
| 1900 | uint32_t DAY:5; /*!< bit: 17..21 Day Timestamp Value */
|
| 1901 | uint32_t MONTH:4; /*!< bit: 22..25 Month Timestamp Value */
|
| 1902 | uint32_t YEAR:6; /*!< bit: 26..31 Year Timestamp Value */
|
| 1903 | } bit; /*!< Structure used for bit access */
|
| 1904 | uint32_t reg; /*!< Type used for register access */
|
| 1905 | } RTC_MODE2_TIMESTAMP_Type;
|
| 1906 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1907 |
|
| 1908 | #define RTC_MODE2_TIMESTAMP_OFFSET 0x64 /**< \brief (RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp */
|
| 1909 | #define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp */
|
| 1910 |
|
| 1911 | #define RTC_MODE2_TIMESTAMP_SECOND_Pos 0 /**< \brief (RTC_MODE2_TIMESTAMP) Second Timestamp Value */
|
| 1912 | #define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)
|
| 1913 | #define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
|
| 1914 | #define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6 /**< \brief (RTC_MODE2_TIMESTAMP) Minute Timestamp Value */
|
| 1915 | #define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)
|
| 1916 | #define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
|
| 1917 | #define RTC_MODE2_TIMESTAMP_HOUR_Pos 12 /**< \brief (RTC_MODE2_TIMESTAMP) Hour Timestamp Value */
|
| 1918 | #define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)
|
| 1919 | #define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
|
| 1920 | #define RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */
|
| 1921 | #define RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */
|
| 1922 | #define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
|
| 1923 | #define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
|
| 1924 | #define RTC_MODE2_TIMESTAMP_DAY_Pos 17 /**< \brief (RTC_MODE2_TIMESTAMP) Day Timestamp Value */
|
| 1925 | #define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)
|
| 1926 | #define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
|
| 1927 | #define RTC_MODE2_TIMESTAMP_MONTH_Pos 22 /**< \brief (RTC_MODE2_TIMESTAMP) Month Timestamp Value */
|
| 1928 | #define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)
|
| 1929 | #define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
|
| 1930 | #define RTC_MODE2_TIMESTAMP_YEAR_Pos 26 /**< \brief (RTC_MODE2_TIMESTAMP) Year Timestamp Value */
|
| 1931 | #define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)
|
| 1932 | #define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
|
| 1933 | #define RTC_MODE2_TIMESTAMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_TIMESTAMP) MASK Register */
|
| 1934 |
|
| 1935 | /* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
|
| 1936 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1937 | typedef union {
|
| 1938 | struct {
|
| 1939 | uint32_t TAMPID0:1; /*!< bit: 0 Tamper Input 0 Detected */
|
| 1940 | uint32_t TAMPID1:1; /*!< bit: 1 Tamper Input 1 Detected */
|
| 1941 | uint32_t TAMPID2:1; /*!< bit: 2 Tamper Input 2 Detected */
|
| 1942 | uint32_t TAMPID3:1; /*!< bit: 3 Tamper Input 3 Detected */
|
| 1943 | uint32_t TAMPID4:1; /*!< bit: 4 Tamper Input 4 Detected */
|
| 1944 | uint32_t :26; /*!< bit: 5..30 Reserved */
|
| 1945 | uint32_t TAMPEVT:1; /*!< bit: 31 Tamper Event Detected */
|
| 1946 | } bit; /*!< Structure used for bit access */
|
| 1947 | struct {
|
| 1948 | uint32_t TAMPID:5; /*!< bit: 0.. 4 Tamper Input x Detected */
|
| 1949 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 1950 | } vec; /*!< Structure used for vec access */
|
| 1951 | uint32_t reg; /*!< Type used for register access */
|
| 1952 | } RTC_TAMPID_Type;
|
| 1953 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1954 |
|
| 1955 | #define RTC_TAMPID_OFFSET 0x68 /**< \brief (RTC_TAMPID offset) Tamper ID */
|
| 1956 | #define RTC_TAMPID_RESETVALUE _U_(0x00000000) /**< \brief (RTC_TAMPID reset_value) Tamper ID */
|
| 1957 |
|
| 1958 | #define RTC_TAMPID_TAMPID0_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input 0 Detected */
|
| 1959 | #define RTC_TAMPID_TAMPID0 (_U_(1) << RTC_TAMPID_TAMPID0_Pos)
|
| 1960 | #define RTC_TAMPID_TAMPID1_Pos 1 /**< \brief (RTC_TAMPID) Tamper Input 1 Detected */
|
| 1961 | #define RTC_TAMPID_TAMPID1 (_U_(1) << RTC_TAMPID_TAMPID1_Pos)
|
| 1962 | #define RTC_TAMPID_TAMPID2_Pos 2 /**< \brief (RTC_TAMPID) Tamper Input 2 Detected */
|
| 1963 | #define RTC_TAMPID_TAMPID2 (_U_(1) << RTC_TAMPID_TAMPID2_Pos)
|
| 1964 | #define RTC_TAMPID_TAMPID3_Pos 3 /**< \brief (RTC_TAMPID) Tamper Input 3 Detected */
|
| 1965 | #define RTC_TAMPID_TAMPID3 (_U_(1) << RTC_TAMPID_TAMPID3_Pos)
|
| 1966 | #define RTC_TAMPID_TAMPID4_Pos 4 /**< \brief (RTC_TAMPID) Tamper Input 4 Detected */
|
| 1967 | #define RTC_TAMPID_TAMPID4 (_U_(1) << RTC_TAMPID_TAMPID4_Pos)
|
| 1968 | #define RTC_TAMPID_TAMPID_Pos 0 /**< \brief (RTC_TAMPID) Tamper Input x Detected */
|
| 1969 | #define RTC_TAMPID_TAMPID_Msk (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)
|
| 1970 | #define RTC_TAMPID_TAMPID(value) (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))
|
| 1971 | #define RTC_TAMPID_TAMPEVT_Pos 31 /**< \brief (RTC_TAMPID) Tamper Event Detected */
|
| 1972 | #define RTC_TAMPID_TAMPEVT (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)
|
| 1973 | #define RTC_TAMPID_MASK _U_(0x8000001F) /**< \brief (RTC_TAMPID) MASK Register */
|
| 1974 |
|
| 1975 | /* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */
|
| 1976 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1977 | typedef union {
|
| 1978 | struct {
|
| 1979 | uint32_t BKUP:32; /*!< bit: 0..31 Backup */
|
| 1980 | } bit; /*!< Structure used for bit access */
|
| 1981 | uint32_t reg; /*!< Type used for register access */
|
| 1982 | } RTC_BKUP_Type;
|
| 1983 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1984 |
|
| 1985 | #define RTC_BKUP_OFFSET 0x80 /**< \brief (RTC_BKUP offset) Backup */
|
| 1986 | #define RTC_BKUP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_BKUP reset_value) Backup */
|
| 1987 |
|
| 1988 | #define RTC_BKUP_BKUP_Pos 0 /**< \brief (RTC_BKUP) Backup */
|
| 1989 | #define RTC_BKUP_BKUP_Msk (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)
|
| 1990 | #define RTC_BKUP_BKUP(value) (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))
|
| 1991 | #define RTC_BKUP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_BKUP) MASK Register */
|
| 1992 |
|
| 1993 | /** \brief RtcMode2Alarm hardware registers */
|
| 1994 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1995 | typedef struct {
|
| 1996 | __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
|
| 1997 | __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
|
| 1998 | RoReg8 Reserved1[0x3];
|
| 1999 | } RtcMode2Alarm;
|
| 2000 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2001 |
|
| 2002 | /** \brief RTC_MODE0 hardware registers */
|
| 2003 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2004 | typedef struct { /* 32-bit Counter with Single 32-bit Compare */
|
| 2005 | __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
|
| 2006 | __IO RTC_MODE0_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
|
| 2007 | __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */
|
| 2008 | __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */
|
| 2009 | __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */
|
| 2010 | __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */
|
| 2011 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
|
| 2012 | RoReg8 Reserved1[0x1];
|
| 2013 | __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */
|
| 2014 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
|
| 2015 | RoReg8 Reserved2[0x3];
|
| 2016 | __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */
|
| 2017 | RoReg8 Reserved3[0x4];
|
| 2018 | __IO RTC_MODE0_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */
|
| 2019 | RoReg8 Reserved4[0x18];
|
| 2020 | __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
|
| 2021 | RoReg8 Reserved5[0x10];
|
| 2022 | __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
|
| 2023 | __I RTC_MODE0_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE0 Timestamp */
|
| 2024 | __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
|
| 2025 | RoReg8 Reserved6[0x14];
|
| 2026 | __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
|
| 2027 | } RtcMode0;
|
| 2028 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2029 |
|
| 2030 | /** \brief RTC_MODE1 hardware registers */
|
| 2031 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2032 | typedef struct { /* 16-bit Counter with Two 16-bit Compares */
|
| 2033 | __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */
|
| 2034 | __IO RTC_MODE1_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */
|
| 2035 | __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */
|
| 2036 | __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */
|
| 2037 | __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */
|
| 2038 | __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */
|
| 2039 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
|
| 2040 | RoReg8 Reserved1[0x1];
|
| 2041 | __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */
|
| 2042 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
|
| 2043 | RoReg8 Reserved2[0x3];
|
| 2044 | __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */
|
| 2045 | RoReg8 Reserved3[0x2];
|
| 2046 | __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */
|
| 2047 | RoReg8 Reserved4[0x2];
|
| 2048 | __IO RTC_MODE1_COMP_Type COMP[4]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */
|
| 2049 | RoReg8 Reserved5[0x18];
|
| 2050 | __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
|
| 2051 | RoReg8 Reserved6[0x10];
|
| 2052 | __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
|
| 2053 | __I RTC_MODE1_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE1 Timestamp */
|
| 2054 | __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
|
| 2055 | RoReg8 Reserved7[0x14];
|
| 2056 | __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
|
| 2057 | } RtcMode1;
|
| 2058 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2059 |
|
| 2060 | /** \brief RTC_MODE2 hardware registers */
|
| 2061 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2062 | typedef struct { /* Clock/Calendar with Alarm */
|
| 2063 | __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */
|
| 2064 | __IO RTC_MODE2_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */
|
| 2065 | __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */
|
| 2066 | __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */
|
| 2067 | __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */
|
| 2068 | __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */
|
| 2069 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
|
| 2070 | RoReg8 Reserved1[0x1];
|
| 2071 | __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */
|
| 2072 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */
|
| 2073 | RoReg8 Reserved2[0x3];
|
| 2074 | __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */
|
| 2075 | RoReg8 Reserved3[0x4];
|
| 2076 | RtcMode2Alarm Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */
|
| 2077 | RoReg8 Reserved4[0x10];
|
| 2078 | __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */
|
| 2079 | RoReg8 Reserved5[0x10];
|
| 2080 | __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
|
| 2081 | __I RTC_MODE2_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE2 Timestamp */
|
| 2082 | __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
|
| 2083 | RoReg8 Reserved6[0x14];
|
| 2084 | __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */
|
| 2085 | } RtcMode2;
|
| 2086 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2087 |
|
| 2088 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 2089 | typedef union {
|
| 2090 | RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
|
| 2091 | RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
|
| 2092 | RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
|
| 2093 | } Rtc;
|
| 2094 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 2095 |
|
| 2096 | /*@}*/
|
| 2097 |
|
| 2098 | #endif /* _SAME54_RTC_COMPONENT_ */
|