| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for RAMECC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_RAMECC_COMPONENT_
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| 31 | #define _SAME54_RAMECC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR RAMECC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_RAMECC RAM ECC */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define RAMECC_U2268
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| 40 | #define REV_RAMECC 0x100
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| 41 |
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| 42 | /* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */
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| 47 | uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */
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| 48 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 49 | } bit; /*!< Structure used for bit access */
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| 50 | uint8_t reg; /*!< Type used for register access */
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| 51 | } RAMECC_INTENCLR_Type;
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| 52 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 53 |
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| 54 | #define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
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| 55 | #define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
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| 56 |
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| 57 | #define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
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| 58 | #define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
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| 59 | #define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
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| 60 | #define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
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| 61 | #define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */
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| 62 |
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| 63 | /* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
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| 64 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 65 | typedef union {
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| 66 | struct {
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| 67 | uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */
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| 68 | uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */
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| 69 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 70 | } bit; /*!< Structure used for bit access */
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| 71 | uint8_t reg; /*!< Type used for register access */
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| 72 | } RAMECC_INTENSET_Type;
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| 73 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 74 |
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| 75 | #define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
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| 76 | #define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
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| 77 |
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| 78 | #define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
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| 79 | #define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
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| 80 | #define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
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| 81 | #define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
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| 82 | #define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */
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| 83 |
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| 84 | /* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
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| 85 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 86 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 87 | struct {
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| 88 | __I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
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| 89 | __I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
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| 90 | __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 91 | } bit; /*!< Structure used for bit access */
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| 92 | uint8_t reg; /*!< Type used for register access */
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| 93 | } RAMECC_INTFLAG_Type;
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| 94 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 95 |
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| 96 | #define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
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| 97 | #define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
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| 98 |
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| 99 | #define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
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| 100 | #define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
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| 101 | #define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
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| 102 | #define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
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| 103 | #define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */
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| 104 |
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| 105 | /* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
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| 106 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 107 | typedef union {
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| 108 | struct {
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| 109 | uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
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| 110 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 111 | } bit; /*!< Structure used for bit access */
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| 112 | uint8_t reg; /*!< Type used for register access */
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| 113 | } RAMECC_STATUS_Type;
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| 114 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 115 |
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| 116 | #define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */
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| 117 | #define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */
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| 118 |
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| 119 | #define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */
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| 120 | #define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
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| 121 | #define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */
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| 122 |
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| 123 | /* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
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| 124 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 125 | typedef union {
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| 126 | struct {
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| 127 | uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */
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| 128 | uint32_t :15; /*!< bit: 17..31 Reserved */
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| 129 | } bit; /*!< Structure used for bit access */
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| 130 | uint32_t reg; /*!< Type used for register access */
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| 131 | } RAMECC_ERRADDR_Type;
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| 132 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 133 |
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| 134 | #define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */
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| 135 | #define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
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| 136 |
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| 137 | #define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */
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| 138 | #define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
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| 139 | #define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
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| 140 | #define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
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| 141 |
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| 142 | /* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
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| 143 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 144 | typedef union {
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| 145 | struct {
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| 146 | uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
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| 147 | uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */
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| 148 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 149 | } bit; /*!< Structure used for bit access */
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| 150 | uint8_t reg; /*!< Type used for register access */
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| 151 | } RAMECC_DBGCTRL_Type;
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| 152 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 153 |
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| 154 | #define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
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| 155 | #define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
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| 156 |
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| 157 | #define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */
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| 158 | #define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
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| 159 | #define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
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| 160 | #define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
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| 161 | #define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */
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| 162 |
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| 163 | /** \brief RAMECC hardware registers */
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| 164 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 165 | typedef struct {
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| 166 | __IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */
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| 167 | __IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */
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| 168 | __IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */
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| 169 | __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
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| 170 | __I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
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| 171 | RoReg8 Reserved1[0x7];
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| 172 | __IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */
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| 173 | } Ramecc;
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| 174 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 175 |
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| 176 | /*@}*/
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| 177 |
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| 178 | #endif /* _SAME54_RAMECC_COMPONENT_ */
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