| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for QSPI
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_QSPI_COMPONENT_
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| 31 | #define _SAME54_QSPI_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR QSPI */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_QSPI Quad SPI interface */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define QSPI_U2008
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| 40 | #define REV_QSPI 0x163
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| 41 |
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| 42 | /* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint32_t :22; /*!< bit: 2..23 Reserved */
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| 49 | uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */
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| 50 | uint32_t :7; /*!< bit: 25..31 Reserved */
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| 51 | } bit; /*!< Structure used for bit access */
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| 52 | uint32_t reg; /*!< Type used for register access */
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| 53 | } QSPI_CTRLA_Type;
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| 54 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 55 |
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| 56 | #define QSPI_CTRLA_OFFSET 0x00 /**< \brief (QSPI_CTRLA offset) Control A */
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| 57 | #define QSPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
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| 58 |
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| 59 | #define QSPI_CTRLA_SWRST_Pos 0 /**< \brief (QSPI_CTRLA) Software Reset */
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| 60 | #define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
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| 61 | #define QSPI_CTRLA_ENABLE_Pos 1 /**< \brief (QSPI_CTRLA) Enable */
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| 62 | #define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
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| 63 | #define QSPI_CTRLA_LASTXFER_Pos 24 /**< \brief (QSPI_CTRLA) Last Transfer */
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| 64 | #define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
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| 65 | #define QSPI_CTRLA_MASK _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
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| 66 |
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| 67 | /* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
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| 68 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 69 | typedef union {
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| 70 | struct {
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| 71 | uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */
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| 72 | uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */
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| 73 | uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */
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| 74 | uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */
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| 75 | uint32_t CSMODE:2; /*!< bit: 4.. 5 Chip Select Mode */
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| 76 | uint32_t :2; /*!< bit: 6.. 7 Reserved */
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| 77 | uint32_t DATALEN:4; /*!< bit: 8..11 Data Length */
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| 78 | uint32_t :4; /*!< bit: 12..15 Reserved */
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| 79 | uint32_t DLYBCT:8; /*!< bit: 16..23 Delay Between Consecutive Transfers */
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| 80 | uint32_t DLYCS:8; /*!< bit: 24..31 Minimum Inactive CS Delay */
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| 81 | } bit; /*!< Structure used for bit access */
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| 82 | uint32_t reg; /*!< Type used for register access */
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| 83 | } QSPI_CTRLB_Type;
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| 84 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 85 |
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| 86 | #define QSPI_CTRLB_OFFSET 0x04 /**< \brief (QSPI_CTRLB offset) Control B */
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| 87 | #define QSPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
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| 88 |
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| 89 | #define QSPI_CTRLB_MODE_Pos 0 /**< \brief (QSPI_CTRLB) Serial Memory Mode */
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| 90 | #define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
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| 91 | #define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) /**< \brief (QSPI_CTRLB) SPI operating mode */
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| 92 | #define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
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| 93 | #define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
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| 94 | #define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
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| 95 | #define QSPI_CTRLB_LOOPEN_Pos 1 /**< \brief (QSPI_CTRLB) Local Loopback Enable */
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| 96 | #define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
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| 97 | #define QSPI_CTRLB_WDRBT_Pos 2 /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
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| 98 | #define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
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| 99 | #define QSPI_CTRLB_SMEMREG_Pos 3 /**< \brief (QSPI_CTRLB) Serial Memory reg */
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| 100 | #define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
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| 101 | #define QSPI_CTRLB_CSMODE_Pos 4 /**< \brief (QSPI_CTRLB) Chip Select Mode */
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| 102 | #define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
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| 103 | #define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
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| 104 | #define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
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| 105 | #define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
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| 106 | #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
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| 107 | #define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
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| 108 | #define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
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| 109 | #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
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| 110 | #define QSPI_CTRLB_DATALEN_Pos 8 /**< \brief (QSPI_CTRLB) Data Length */
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| 111 | #define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
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| 112 | #define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
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| 113 | #define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) /**< \brief (QSPI_CTRLB) 8-bits transfer */
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| 114 | #define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) /**< \brief (QSPI_CTRLB) 9 bits transfer */
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| 115 | #define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) /**< \brief (QSPI_CTRLB) 10-bits transfer */
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| 116 | #define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) /**< \brief (QSPI_CTRLB) 11-bits transfer */
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| 117 | #define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) /**< \brief (QSPI_CTRLB) 12-bits transfer */
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| 118 | #define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) /**< \brief (QSPI_CTRLB) 13-bits transfer */
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| 119 | #define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) /**< \brief (QSPI_CTRLB) 14-bits transfer */
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| 120 | #define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) /**< \brief (QSPI_CTRLB) 15-bits transfer */
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| 121 | #define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) /**< \brief (QSPI_CTRLB) 16-bits transfer */
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| 122 | #define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 123 | #define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 124 | #define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 125 | #define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 126 | #define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 127 | #define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 128 | #define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 129 | #define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 130 | #define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
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| 131 | #define QSPI_CTRLB_DLYBCT_Pos 16 /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
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| 132 | #define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
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| 133 | #define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
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| 134 | #define QSPI_CTRLB_DLYCS_Pos 24 /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
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| 135 | #define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
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| 136 | #define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
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| 137 | #define QSPI_CTRLB_MASK _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
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| 138 |
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| 139 | /* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
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| 140 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 141 | typedef union {
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| 142 | struct {
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| 143 | uint32_t CPOL:1; /*!< bit: 0 Clock Polarity */
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| 144 | uint32_t CPHA:1; /*!< bit: 1 Clock Phase */
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| 145 | uint32_t :6; /*!< bit: 2.. 7 Reserved */
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| 146 | uint32_t BAUD:8; /*!< bit: 8..15 Serial Clock Baud Rate */
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| 147 | uint32_t DLYBS:8; /*!< bit: 16..23 Delay Before SCK */
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| 148 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 149 | } bit; /*!< Structure used for bit access */
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| 150 | uint32_t reg; /*!< Type used for register access */
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| 151 | } QSPI_BAUD_Type;
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| 152 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 153 |
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| 154 | #define QSPI_BAUD_OFFSET 0x08 /**< \brief (QSPI_BAUD offset) Baud Rate */
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| 155 | #define QSPI_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
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| 156 |
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| 157 | #define QSPI_BAUD_CPOL_Pos 0 /**< \brief (QSPI_BAUD) Clock Polarity */
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| 158 | #define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
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| 159 | #define QSPI_BAUD_CPHA_Pos 1 /**< \brief (QSPI_BAUD) Clock Phase */
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| 160 | #define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
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| 161 | #define QSPI_BAUD_BAUD_Pos 8 /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
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| 162 | #define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
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| 163 | #define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
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| 164 | #define QSPI_BAUD_DLYBS_Pos 16 /**< \brief (QSPI_BAUD) Delay Before SCK */
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| 165 | #define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
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| 166 | #define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
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| 167 | #define QSPI_BAUD_MASK _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
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| 168 |
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| 169 | /* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */
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| 170 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 171 | typedef union {
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| 172 | struct {
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| 173 | uint32_t DATA:16; /*!< bit: 0..15 Receive Data */
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| 174 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 175 | } bit; /*!< Structure used for bit access */
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| 176 | uint32_t reg; /*!< Type used for register access */
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| 177 | } QSPI_RXDATA_Type;
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| 178 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 179 |
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| 180 | #define QSPI_RXDATA_OFFSET 0x0C /**< \brief (QSPI_RXDATA offset) Receive Data */
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| 181 | #define QSPI_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
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| 182 |
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| 183 | #define QSPI_RXDATA_DATA_Pos 0 /**< \brief (QSPI_RXDATA) Receive Data */
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| 184 | #define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
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| 185 | #define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
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| 186 | #define QSPI_RXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
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| 187 |
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| 188 | /* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
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| 189 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 190 | typedef union {
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| 191 | struct {
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| 192 | uint32_t DATA:16; /*!< bit: 0..15 Transmit Data */
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| 193 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 194 | } bit; /*!< Structure used for bit access */
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| 195 | uint32_t reg; /*!< Type used for register access */
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| 196 | } QSPI_TXDATA_Type;
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| 197 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 198 |
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| 199 | #define QSPI_TXDATA_OFFSET 0x10 /**< \brief (QSPI_TXDATA offset) Transmit Data */
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| 200 | #define QSPI_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
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| 201 |
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| 202 | #define QSPI_TXDATA_DATA_Pos 0 /**< \brief (QSPI_TXDATA) Transmit Data */
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| 203 | #define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
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| 204 | #define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
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| 205 | #define QSPI_TXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
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| 206 |
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| 207 | /* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
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| 208 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 209 | typedef union {
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| 210 | struct {
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| 211 | uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Disable */
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| 212 | uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Disable */
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| 213 | uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Disable */
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| 214 | uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Disable */
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| 215 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
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| 216 | uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Disable */
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| 217 | uint32_t :1; /*!< bit: 9 Reserved */
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| 218 | uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Disable */
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| 219 | uint32_t :21; /*!< bit: 11..31 Reserved */
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| 220 | } bit; /*!< Structure used for bit access */
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| 221 | uint32_t reg; /*!< Type used for register access */
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| 222 | } QSPI_INTENCLR_Type;
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| 223 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 224 |
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| 225 | #define QSPI_INTENCLR_OFFSET 0x14 /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
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| 226 | #define QSPI_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
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| 227 |
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| 228 | #define QSPI_INTENCLR_RXC_Pos 0 /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
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| 229 | #define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
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| 230 | #define QSPI_INTENCLR_DRE_Pos 1 /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
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| 231 | #define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
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| 232 | #define QSPI_INTENCLR_TXC_Pos 2 /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
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| 233 | #define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
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| 234 | #define QSPI_INTENCLR_ERROR_Pos 3 /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
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| 235 | #define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
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| 236 | #define QSPI_INTENCLR_CSRISE_Pos 8 /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
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| 237 | #define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
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| 238 | #define QSPI_INTENCLR_INSTREND_Pos 10 /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
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| 239 | #define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
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| 240 | #define QSPI_INTENCLR_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
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| 241 |
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| 242 | /* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
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| 243 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 244 | typedef union {
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| 245 | struct {
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| 246 | uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Enable */
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| 247 | uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Enable */
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| 248 | uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Enable */
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| 249 | uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Enable */
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| 250 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
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| 251 | uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Enable */
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| 252 | uint32_t :1; /*!< bit: 9 Reserved */
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| 253 | uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Enable */
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| 254 | uint32_t :21; /*!< bit: 11..31 Reserved */
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| 255 | } bit; /*!< Structure used for bit access */
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| 256 | uint32_t reg; /*!< Type used for register access */
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| 257 | } QSPI_INTENSET_Type;
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| 258 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 259 |
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| 260 | #define QSPI_INTENSET_OFFSET 0x18 /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
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| 261 | #define QSPI_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
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| 262 |
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| 263 | #define QSPI_INTENSET_RXC_Pos 0 /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
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| 264 | #define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
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| 265 | #define QSPI_INTENSET_DRE_Pos 1 /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
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| 266 | #define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
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| 267 | #define QSPI_INTENSET_TXC_Pos 2 /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
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| 268 | #define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
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| 269 | #define QSPI_INTENSET_ERROR_Pos 3 /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
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| 270 | #define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
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| 271 | #define QSPI_INTENSET_CSRISE_Pos 8 /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
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| 272 | #define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
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| 273 | #define QSPI_INTENSET_INSTREND_Pos 10 /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
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| 274 | #define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
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| 275 | #define QSPI_INTENSET_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
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| 276 |
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| 277 | /* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
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| 278 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 279 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 280 | struct {
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| 281 | __I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */
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| 282 | __I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */
|
| 283 | __I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */
|
| 284 | __I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */
|
| 285 | __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
| 286 | __I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */
|
| 287 | __I uint32_t :1; /*!< bit: 9 Reserved */
|
| 288 | __I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */
|
| 289 | __I uint32_t :21; /*!< bit: 11..31 Reserved */
|
| 290 | } bit; /*!< Structure used for bit access */
|
| 291 | uint32_t reg; /*!< Type used for register access */
|
| 292 | } QSPI_INTFLAG_Type;
|
| 293 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 294 |
|
| 295 | #define QSPI_INTFLAG_OFFSET 0x1C /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
|
| 296 | #define QSPI_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
| 297 |
|
| 298 | #define QSPI_INTFLAG_RXC_Pos 0 /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
|
| 299 | #define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
|
| 300 | #define QSPI_INTFLAG_DRE_Pos 1 /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
|
| 301 | #define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
|
| 302 | #define QSPI_INTFLAG_TXC_Pos 2 /**< \brief (QSPI_INTFLAG) Transmission Complete */
|
| 303 | #define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
|
| 304 | #define QSPI_INTFLAG_ERROR_Pos 3 /**< \brief (QSPI_INTFLAG) Overrun Error */
|
| 305 | #define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
|
| 306 | #define QSPI_INTFLAG_CSRISE_Pos 8 /**< \brief (QSPI_INTFLAG) Chip Select Rise */
|
| 307 | #define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
|
| 308 | #define QSPI_INTFLAG_INSTREND_Pos 10 /**< \brief (QSPI_INTFLAG) Instruction End */
|
| 309 | #define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
|
| 310 | #define QSPI_INTFLAG_MASK _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
|
| 311 |
|
| 312 | /* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */
|
| 313 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 314 | typedef union {
|
| 315 | struct {
|
| 316 | uint32_t :1; /*!< bit: 0 Reserved */
|
| 317 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
| 318 | uint32_t :7; /*!< bit: 2.. 8 Reserved */
|
| 319 | uint32_t CSSTATUS:1; /*!< bit: 9 Chip Select */
|
| 320 | uint32_t :22; /*!< bit: 10..31 Reserved */
|
| 321 | } bit; /*!< Structure used for bit access */
|
| 322 | uint32_t reg; /*!< Type used for register access */
|
| 323 | } QSPI_STATUS_Type;
|
| 324 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 325 |
|
| 326 | #define QSPI_STATUS_OFFSET 0x20 /**< \brief (QSPI_STATUS offset) Status Register */
|
| 327 | #define QSPI_STATUS_RESETVALUE _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
|
| 328 |
|
| 329 | #define QSPI_STATUS_ENABLE_Pos 1 /**< \brief (QSPI_STATUS) Enable */
|
| 330 | #define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
|
| 331 | #define QSPI_STATUS_CSSTATUS_Pos 9 /**< \brief (QSPI_STATUS) Chip Select */
|
| 332 | #define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
|
| 333 | #define QSPI_STATUS_MASK _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
|
| 334 |
|
| 335 | /* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
|
| 336 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 337 | typedef union {
|
| 338 | struct {
|
| 339 | uint32_t ADDR:32; /*!< bit: 0..31 Instruction Address */
|
| 340 | } bit; /*!< Structure used for bit access */
|
| 341 | uint32_t reg; /*!< Type used for register access */
|
| 342 | } QSPI_INSTRADDR_Type;
|
| 343 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 344 |
|
| 345 | #define QSPI_INSTRADDR_OFFSET 0x30 /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
|
| 346 | #define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
|
| 347 |
|
| 348 | #define QSPI_INSTRADDR_ADDR_Pos 0 /**< \brief (QSPI_INSTRADDR) Instruction Address */
|
| 349 | #define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
|
| 350 | #define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
|
| 351 | #define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
|
| 352 |
|
| 353 | /* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
|
| 354 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 355 | typedef union {
|
| 356 | struct {
|
| 357 | uint32_t INSTR:8; /*!< bit: 0.. 7 Instruction Code */
|
| 358 | uint32_t :8; /*!< bit: 8..15 Reserved */
|
| 359 | uint32_t OPTCODE:8; /*!< bit: 16..23 Option Code */
|
| 360 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 361 | } bit; /*!< Structure used for bit access */
|
| 362 | uint32_t reg; /*!< Type used for register access */
|
| 363 | } QSPI_INSTRCTRL_Type;
|
| 364 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 365 |
|
| 366 | #define QSPI_INSTRCTRL_OFFSET 0x34 /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
|
| 367 | #define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
|
| 368 |
|
| 369 | #define QSPI_INSTRCTRL_INSTR_Pos 0 /**< \brief (QSPI_INSTRCTRL) Instruction Code */
|
| 370 | #define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
|
| 371 | #define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
|
| 372 | #define QSPI_INSTRCTRL_OPTCODE_Pos 16 /**< \brief (QSPI_INSTRCTRL) Option Code */
|
| 373 | #define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
|
| 374 | #define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
|
| 375 | #define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
|
| 376 |
|
| 377 | /* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
|
| 378 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 379 | typedef union {
|
| 380 | struct {
|
| 381 | uint32_t WIDTH:3; /*!< bit: 0.. 2 Instruction Code, Address, Option Code and Data Width */
|
| 382 | uint32_t :1; /*!< bit: 3 Reserved */
|
| 383 | uint32_t INSTREN:1; /*!< bit: 4 Instruction Enable */
|
| 384 | uint32_t ADDREN:1; /*!< bit: 5 Address Enable */
|
| 385 | uint32_t OPTCODEEN:1; /*!< bit: 6 Option Enable */
|
| 386 | uint32_t DATAEN:1; /*!< bit: 7 Data Enable */
|
| 387 | uint32_t OPTCODELEN:2; /*!< bit: 8.. 9 Option Code Length */
|
| 388 | uint32_t ADDRLEN:1; /*!< bit: 10 Address Length */
|
| 389 | uint32_t :1; /*!< bit: 11 Reserved */
|
| 390 | uint32_t TFRTYPE:2; /*!< bit: 12..13 Data Transfer Type */
|
| 391 | uint32_t CRMODE:1; /*!< bit: 14 Continuous Read Mode */
|
| 392 | uint32_t DDREN:1; /*!< bit: 15 Double Data Rate Enable */
|
| 393 | uint32_t DUMMYLEN:5; /*!< bit: 16..20 Dummy Cycles Length */
|
| 394 | uint32_t :11; /*!< bit: 21..31 Reserved */
|
| 395 | } bit; /*!< Structure used for bit access */
|
| 396 | uint32_t reg; /*!< Type used for register access */
|
| 397 | } QSPI_INSTRFRAME_Type;
|
| 398 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 399 |
|
| 400 | #define QSPI_INSTRFRAME_OFFSET 0x38 /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
|
| 401 | #define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
|
| 402 |
|
| 403 | #define QSPI_INSTRFRAME_WIDTH_Pos 0 /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
|
| 404 | #define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 405 | #define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
|
| 406 | #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
|
| 407 | #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
|
| 408 | #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
|
| 409 | #define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
|
| 410 | #define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
|
| 411 | #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
|
| 412 | #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
|
| 413 | #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 414 | #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 415 | #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 416 | #define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 417 | #define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 418 | #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 419 | #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
|
| 420 | #define QSPI_INSTRFRAME_INSTREN_Pos 4 /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
|
| 421 | #define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
|
| 422 | #define QSPI_INSTRFRAME_ADDREN_Pos 5 /**< \brief (QSPI_INSTRFRAME) Address Enable */
|
| 423 | #define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
|
| 424 | #define QSPI_INSTRFRAME_OPTCODEEN_Pos 6 /**< \brief (QSPI_INSTRFRAME) Option Enable */
|
| 425 | #define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
|
| 426 | #define QSPI_INSTRFRAME_DATAEN_Pos 7 /**< \brief (QSPI_INSTRFRAME) Data Enable */
|
| 427 | #define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
|
| 428 | #define QSPI_INSTRFRAME_OPTCODELEN_Pos 8 /**< \brief (QSPI_INSTRFRAME) Option Code Length */
|
| 429 | #define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
|
| 430 | #define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
|
| 431 | #define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
|
| 432 | #define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
|
| 433 | #define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
|
| 434 | #define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
|
| 435 | #define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
|
| 436 | #define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
|
| 437 | #define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
|
| 438 | #define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
|
| 439 | #define QSPI_INSTRFRAME_ADDRLEN_Pos 10 /**< \brief (QSPI_INSTRFRAME) Address Length */
|
| 440 | #define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
|
| 441 | #define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
|
| 442 | #define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
|
| 443 | #define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
|
| 444 | #define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
|
| 445 | #define QSPI_INSTRFRAME_TFRTYPE_Pos 12 /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
|
| 446 | #define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
|
| 447 | #define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
|
| 448 | #define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
|
| 449 | #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
|
| 450 | #define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
|
| 451 | #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
|
| 452 | #define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
|
| 453 | #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
|
| 454 | #define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
|
| 455 | #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
|
| 456 | #define QSPI_INSTRFRAME_CRMODE_Pos 14 /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
|
| 457 | #define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
|
| 458 | #define QSPI_INSTRFRAME_DDREN_Pos 15 /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
|
| 459 | #define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
|
| 460 | #define QSPI_INSTRFRAME_DUMMYLEN_Pos 16 /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
|
| 461 | #define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
|
| 462 | #define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
|
| 463 | #define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
|
| 464 |
|
| 465 | /* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
|
| 466 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 467 | typedef union {
|
| 468 | struct {
|
| 469 | uint32_t ENABLE:1; /*!< bit: 0 Scrambling/Unscrambling Enable */
|
| 470 | uint32_t RANDOMDIS:1; /*!< bit: 1 Scrambling/Unscrambling Random Value Disable */
|
| 471 | uint32_t :30; /*!< bit: 2..31 Reserved */
|
| 472 | } bit; /*!< Structure used for bit access */
|
| 473 | uint32_t reg; /*!< Type used for register access */
|
| 474 | } QSPI_SCRAMBCTRL_Type;
|
| 475 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 476 |
|
| 477 | #define QSPI_SCRAMBCTRL_OFFSET 0x40 /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
|
| 478 | #define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
|
| 479 |
|
| 480 | #define QSPI_SCRAMBCTRL_ENABLE_Pos 0 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
|
| 481 | #define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
|
| 482 | #define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
|
| 483 | #define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
|
| 484 | #define QSPI_SCRAMBCTRL_MASK _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
|
| 485 |
|
| 486 | /* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
|
| 487 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 488 | typedef union {
|
| 489 | struct {
|
| 490 | uint32_t KEY:32; /*!< bit: 0..31 Scrambling User Key */
|
| 491 | } bit; /*!< Structure used for bit access */
|
| 492 | uint32_t reg; /*!< Type used for register access */
|
| 493 | } QSPI_SCRAMBKEY_Type;
|
| 494 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 495 |
|
| 496 | #define QSPI_SCRAMBKEY_OFFSET 0x44 /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
|
| 497 | #define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
|
| 498 |
|
| 499 | #define QSPI_SCRAMBKEY_KEY_Pos 0 /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
|
| 500 | #define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
|
| 501 | #define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
|
| 502 | #define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
|
| 503 |
|
| 504 | /** \brief QSPI APB hardware registers */
|
| 505 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 506 | typedef struct {
|
| 507 | __IO QSPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
|
| 508 | __IO QSPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
|
| 509 | __IO QSPI_BAUD_Type BAUD; /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
|
| 510 | __I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */
|
| 511 | __O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
|
| 512 | __IO QSPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
|
| 513 | __IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
|
| 514 | __IO QSPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
|
| 515 | __I QSPI_STATUS_Type STATUS; /**< \brief Offset: 0x20 (R/ 32) Status Register */
|
| 516 | RoReg8 Reserved1[0xC];
|
| 517 | __IO QSPI_INSTRADDR_Type INSTRADDR; /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
|
| 518 | __IO QSPI_INSTRCTRL_Type INSTRCTRL; /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
|
| 519 | __IO QSPI_INSTRFRAME_Type INSTRFRAME; /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
|
| 520 | RoReg8 Reserved2[0x4];
|
| 521 | __IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL; /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
|
| 522 | __O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
|
| 523 | } Qspi;
|
| 524 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 525 |
|
| 526 | /*@}*/
|
| 527 |
|
| 528 | #endif /* _SAME54_QSPI_COMPONENT_ */
|