| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for PDEC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_PDEC_COMPONENT_
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| 31 | #define _SAME54_PDEC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR PDEC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_PDEC Quadrature Decodeur */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define PDEC_U2263
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| 40 | #define REV_PDEC 0x100
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| 41 |
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| 42 | /* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint32_t MODE:2; /*!< bit: 2.. 3 Operation Mode */
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| 49 | uint32_t :2; /*!< bit: 4.. 5 Reserved */
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| 50 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
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| 51 | uint32_t :1; /*!< bit: 7 Reserved */
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| 52 | uint32_t CONF:3; /*!< bit: 8..10 PDEC Configuration */
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| 53 | uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
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| 54 | uint32_t :2; /*!< bit: 12..13 Reserved */
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| 55 | uint32_t SWAP:1; /*!< bit: 14 PDEC Phase A and B Swap */
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| 56 | uint32_t PEREN:1; /*!< bit: 15 Period Enable */
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| 57 | uint32_t PINEN0:1; /*!< bit: 16 PDEC Input From Pin 0 Enable */
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| 58 | uint32_t PINEN1:1; /*!< bit: 17 PDEC Input From Pin 1 Enable */
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| 59 | uint32_t PINEN2:1; /*!< bit: 18 PDEC Input From Pin 2 Enable */
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| 60 | uint32_t :1; /*!< bit: 19 Reserved */
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| 61 | uint32_t PINVEN0:1; /*!< bit: 20 IO Pin 0 Invert Enable */
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| 62 | uint32_t PINVEN1:1; /*!< bit: 21 IO Pin 1 Invert Enable */
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| 63 | uint32_t PINVEN2:1; /*!< bit: 22 IO Pin 2 Invert Enable */
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| 64 | uint32_t :1; /*!< bit: 23 Reserved */
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| 65 | uint32_t ANGULAR:3; /*!< bit: 24..26 Angular Counter Length */
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| 66 | uint32_t :1; /*!< bit: 27 Reserved */
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| 67 | uint32_t MAXCMP:4; /*!< bit: 28..31 Maximum Consecutive Missing Pulses */
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| 68 | } bit; /*!< Structure used for bit access */
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| 69 | struct {
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| 70 | uint32_t :16; /*!< bit: 0..15 Reserved */
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| 71 | uint32_t PINEN:3; /*!< bit: 16..18 PDEC Input From Pin x Enable */
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| 72 | uint32_t :1; /*!< bit: 19 Reserved */
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| 73 | uint32_t PINVEN:3; /*!< bit: 20..22 IO Pin x Invert Enable */
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| 74 | uint32_t :9; /*!< bit: 23..31 Reserved */
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| 75 | } vec; /*!< Structure used for vec access */
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| 76 | uint32_t reg; /*!< Type used for register access */
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| 77 | } PDEC_CTRLA_Type;
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| 78 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 79 |
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| 80 | #define PDEC_CTRLA_OFFSET 0x00 /**< \brief (PDEC_CTRLA offset) Control A */
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| 81 | #define PDEC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
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| 82 |
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| 83 | #define PDEC_CTRLA_SWRST_Pos 0 /**< \brief (PDEC_CTRLA) Software Reset */
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| 84 | #define PDEC_CTRLA_SWRST (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
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| 85 | #define PDEC_CTRLA_ENABLE_Pos 1 /**< \brief (PDEC_CTRLA) Enable */
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| 86 | #define PDEC_CTRLA_ENABLE (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
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| 87 | #define PDEC_CTRLA_MODE_Pos 2 /**< \brief (PDEC_CTRLA) Operation Mode */
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| 88 | #define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
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| 89 | #define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
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| 90 | #define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< \brief (PDEC_CTRLA) QDEC operating mode */
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| 91 | #define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< \brief (PDEC_CTRLA) HALL operating mode */
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| 92 | #define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< \brief (PDEC_CTRLA) COUNTER operating mode */
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| 93 | #define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos)
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| 94 | #define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos)
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| 95 | #define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos)
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| 96 | #define PDEC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (PDEC_CTRLA) Run in Standby */
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| 97 | #define PDEC_CTRLA_RUNSTDBY (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
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| 98 | #define PDEC_CTRLA_CONF_Pos 8 /**< \brief (PDEC_CTRLA) PDEC Configuration */
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| 99 | #define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
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| 100 | #define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
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| 101 | #define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
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| 102 | #define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
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| 103 | #define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< \brief (PDEC_CTRLA) Decoder direction */
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| 104 | #define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< \brief (PDEC_CTRLA) Secure decoder direction */
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| 105 | #define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< \brief (PDEC_CTRLA) Auto correction mode */
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| 106 | #define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos)
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| 107 | #define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos)
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| 108 | #define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos)
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| 109 | #define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos)
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| 110 | #define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos)
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| 111 | #define PDEC_CTRLA_ALOCK_Pos 11 /**< \brief (PDEC_CTRLA) Auto Lock */
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| 112 | #define PDEC_CTRLA_ALOCK (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
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| 113 | #define PDEC_CTRLA_SWAP_Pos 14 /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
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| 114 | #define PDEC_CTRLA_SWAP (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
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| 115 | #define PDEC_CTRLA_PEREN_Pos 15 /**< \brief (PDEC_CTRLA) Period Enable */
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| 116 | #define PDEC_CTRLA_PEREN (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
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| 117 | #define PDEC_CTRLA_PINEN0_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
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| 118 | #define PDEC_CTRLA_PINEN0 (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
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| 119 | #define PDEC_CTRLA_PINEN1_Pos 17 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
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| 120 | #define PDEC_CTRLA_PINEN1 (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
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| 121 | #define PDEC_CTRLA_PINEN2_Pos 18 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
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| 122 | #define PDEC_CTRLA_PINEN2 (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
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| 123 | #define PDEC_CTRLA_PINEN_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
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| 124 | #define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
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| 125 | #define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
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| 126 | #define PDEC_CTRLA_PINVEN0_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
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| 127 | #define PDEC_CTRLA_PINVEN0 (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
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| 128 | #define PDEC_CTRLA_PINVEN1_Pos 21 /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
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| 129 | #define PDEC_CTRLA_PINVEN1 (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
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| 130 | #define PDEC_CTRLA_PINVEN2_Pos 22 /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
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| 131 | #define PDEC_CTRLA_PINVEN2 (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
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| 132 | #define PDEC_CTRLA_PINVEN_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
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| 133 | #define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
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| 134 | #define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
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| 135 | #define PDEC_CTRLA_ANGULAR_Pos 24 /**< \brief (PDEC_CTRLA) Angular Counter Length */
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| 136 | #define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
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| 137 | #define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
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| 138 | #define PDEC_CTRLA_MAXCMP_Pos 28 /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
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| 139 | #define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
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| 140 | #define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
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| 141 | #define PDEC_CTRLA_MASK _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
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| 142 |
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| 143 | /* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
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| 144 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 145 | typedef union {
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| 146 | struct {
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| 147 | uint8_t :1; /*!< bit: 0 Reserved */
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| 148 | uint8_t LUPD:1; /*!< bit: 1 Lock Update */
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| 149 | uint8_t :3; /*!< bit: 2.. 4 Reserved */
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| 150 | uint8_t CMD:3; /*!< bit: 5.. 7 Command */
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| 151 | } bit; /*!< Structure used for bit access */
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| 152 | uint8_t reg; /*!< Type used for register access */
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| 153 | } PDEC_CTRLBCLR_Type;
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| 154 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 155 |
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| 156 | #define PDEC_CTRLBCLR_OFFSET 0x04 /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
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| 157 | #define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
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| 158 |
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| 159 | #define PDEC_CTRLBCLR_LUPD_Pos 1 /**< \brief (PDEC_CTRLBCLR) Lock Update */
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| 160 | #define PDEC_CTRLBCLR_LUPD (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
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| 161 | #define PDEC_CTRLBCLR_CMD_Pos 5 /**< \brief (PDEC_CTRLBCLR) Command */
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| 162 | #define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
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| 163 | #define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
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| 164 | #define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBCLR) No action */
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| 165 | #define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
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| 166 | #define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
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| 167 | #define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
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| 168 | #define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
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| 169 | #define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
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| 170 | #define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos)
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| 171 | #define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
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| 172 | #define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos)
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| 173 | #define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
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| 174 | #define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos)
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| 175 | #define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos)
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| 176 | #define PDEC_CTRLBCLR_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBCLR) MASK Register */
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| 177 |
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| 178 | /* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
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| 179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 180 | typedef union {
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| 181 | struct {
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| 182 | uint8_t :1; /*!< bit: 0 Reserved */
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| 183 | uint8_t LUPD:1; /*!< bit: 1 Lock Update */
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| 184 | uint8_t :3; /*!< bit: 2.. 4 Reserved */
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| 185 | uint8_t CMD:3; /*!< bit: 5.. 7 Command */
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| 186 | } bit; /*!< Structure used for bit access */
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| 187 | uint8_t reg; /*!< Type used for register access */
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| 188 | } PDEC_CTRLBSET_Type;
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| 189 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 190 |
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| 191 | #define PDEC_CTRLBSET_OFFSET 0x05 /**< \brief (PDEC_CTRLBSET offset) Control B Set */
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| 192 | #define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
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| 193 |
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| 194 | #define PDEC_CTRLBSET_LUPD_Pos 1 /**< \brief (PDEC_CTRLBSET) Lock Update */
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| 195 | #define PDEC_CTRLBSET_LUPD (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
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| 196 | #define PDEC_CTRLBSET_CMD_Pos 5 /**< \brief (PDEC_CTRLBSET) Command */
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| 197 | #define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
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| 198 | #define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
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| 199 | #define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBSET) No action */
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| 200 | #define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
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| 201 | #define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
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| 202 | #define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
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| 203 | #define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
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| 204 | #define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
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| 205 | #define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos)
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| 206 | #define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
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| 207 | #define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos)
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| 208 | #define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
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| 209 | #define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos)
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| 210 | #define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos)
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| 211 | #define PDEC_CTRLBSET_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBSET) MASK Register */
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| 212 |
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| 213 | /* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
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| 214 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 215 | typedef union {
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| 216 | struct {
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| 217 | uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */
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| 218 | uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */
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| 219 | uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */
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| 220 | uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
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| 221 | uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */
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| 222 | uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */
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| 223 | uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */
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| 224 | uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */
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| 225 | uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */
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| 226 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 227 | } bit; /*!< Structure used for bit access */
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| 228 | struct {
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| 229 | uint16_t :12; /*!< bit: 0..11 Reserved */
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| 230 | uint16_t MCEO:2; /*!< bit: 12..13 Match Channel x Event Output Enable */
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| 231 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 232 | } vec; /*!< Structure used for vec access */
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| 233 | uint16_t reg; /*!< Type used for register access */
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| 234 | } PDEC_EVCTRL_Type;
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| 235 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 236 |
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| 237 | #define PDEC_EVCTRL_OFFSET 0x06 /**< \brief (PDEC_EVCTRL offset) Event Control */
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| 238 | #define PDEC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (PDEC_EVCTRL reset_value) Event Control */
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| 239 |
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| 240 | #define PDEC_EVCTRL_EVACT_Pos 0 /**< \brief (PDEC_EVCTRL) Event Action */
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| 241 | #define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
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| 242 | #define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
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| 243 | #define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (PDEC_EVCTRL) Event action disabled */
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| 244 | #define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
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| 245 | #define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (PDEC_EVCTRL) Count on event */
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| 246 | #define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos)
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| 247 | #define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
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| 248 | #define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos)
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| 249 | #define PDEC_EVCTRL_EVINV_Pos 2 /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
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| 250 | #define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
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| 251 | #define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
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| 252 | #define PDEC_EVCTRL_EVEI_Pos 5 /**< \brief (PDEC_EVCTRL) Event Input Enable */
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| 253 | #define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
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| 254 | #define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
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| 255 | #define PDEC_EVCTRL_OVFEO_Pos 8 /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
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| 256 | #define PDEC_EVCTRL_OVFEO (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
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| 257 | #define PDEC_EVCTRL_ERREO_Pos 9 /**< \brief (PDEC_EVCTRL) Error Output Event Enable */
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| 258 | #define PDEC_EVCTRL_ERREO (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
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| 259 | #define PDEC_EVCTRL_DIREO_Pos 10 /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
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| 260 | #define PDEC_EVCTRL_DIREO (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
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| 261 | #define PDEC_EVCTRL_VLCEO_Pos 11 /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
|
| 262 | #define PDEC_EVCTRL_VLCEO (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
|
| 263 | #define PDEC_EVCTRL_MCEO0_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
|
| 264 | #define PDEC_EVCTRL_MCEO0 (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
|
| 265 | #define PDEC_EVCTRL_MCEO1_Pos 13 /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
|
| 266 | #define PDEC_EVCTRL_MCEO1 (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
|
| 267 | #define PDEC_EVCTRL_MCEO_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
|
| 268 | #define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
|
| 269 | #define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
|
| 270 | #define PDEC_EVCTRL_MASK _U_(0x3FFF) /**< \brief (PDEC_EVCTRL) MASK Register */
|
| 271 |
|
| 272 | /* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
|
| 273 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 274 | typedef union {
|
| 275 | struct {
|
| 276 | uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Disable */
|
| 277 | uint8_t ERR:1; /*!< bit: 1 Error Interrupt Disable */
|
| 278 | uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Disable */
|
| 279 | uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Disable */
|
| 280 | uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Disable */
|
| 281 | uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Disable */
|
| 282 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 283 | } bit; /*!< Structure used for bit access */
|
| 284 | struct {
|
| 285 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
| 286 | uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Disable */
|
| 287 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 288 | } vec; /*!< Structure used for vec access */
|
| 289 | uint8_t reg; /*!< Type used for register access */
|
| 290 | } PDEC_INTENCLR_Type;
|
| 291 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 292 |
|
| 293 | #define PDEC_INTENCLR_OFFSET 0x08 /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
|
| 294 | #define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
|
| 295 |
|
| 296 | #define PDEC_INTENCLR_OVF_Pos 0 /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
|
| 297 | #define PDEC_INTENCLR_OVF (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
|
| 298 | #define PDEC_INTENCLR_ERR_Pos 1 /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
|
| 299 | #define PDEC_INTENCLR_ERR (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
|
| 300 | #define PDEC_INTENCLR_DIR_Pos 2 /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
|
| 301 | #define PDEC_INTENCLR_DIR (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
|
| 302 | #define PDEC_INTENCLR_VLC_Pos 3 /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
|
| 303 | #define PDEC_INTENCLR_VLC (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
|
| 304 | #define PDEC_INTENCLR_MC0_Pos 4 /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
|
| 305 | #define PDEC_INTENCLR_MC0 (_U_(1) << PDEC_INTENCLR_MC0_Pos)
|
| 306 | #define PDEC_INTENCLR_MC1_Pos 5 /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
|
| 307 | #define PDEC_INTENCLR_MC1 (_U_(1) << PDEC_INTENCLR_MC1_Pos)
|
| 308 | #define PDEC_INTENCLR_MC_Pos 4 /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
|
| 309 | #define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
|
| 310 | #define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
|
| 311 | #define PDEC_INTENCLR_MASK _U_(0x3F) /**< \brief (PDEC_INTENCLR) MASK Register */
|
| 312 |
|
| 313 | /* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
|
| 314 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 315 | typedef union {
|
| 316 | struct {
|
| 317 | uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Enable */
|
| 318 | uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
|
| 319 | uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Enable */
|
| 320 | uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Enable */
|
| 321 | uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Enable */
|
| 322 | uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Enable */
|
| 323 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 324 | } bit; /*!< Structure used for bit access */
|
| 325 | struct {
|
| 326 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
| 327 | uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Enable */
|
| 328 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 329 | } vec; /*!< Structure used for vec access */
|
| 330 | uint8_t reg; /*!< Type used for register access */
|
| 331 | } PDEC_INTENSET_Type;
|
| 332 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 333 |
|
| 334 | #define PDEC_INTENSET_OFFSET 0x09 /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
|
| 335 | #define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
|
| 336 |
|
| 337 | #define PDEC_INTENSET_OVF_Pos 0 /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
|
| 338 | #define PDEC_INTENSET_OVF (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
|
| 339 | #define PDEC_INTENSET_ERR_Pos 1 /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
|
| 340 | #define PDEC_INTENSET_ERR (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
|
| 341 | #define PDEC_INTENSET_DIR_Pos 2 /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
|
| 342 | #define PDEC_INTENSET_DIR (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
|
| 343 | #define PDEC_INTENSET_VLC_Pos 3 /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
|
| 344 | #define PDEC_INTENSET_VLC (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
|
| 345 | #define PDEC_INTENSET_MC0_Pos 4 /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
|
| 346 | #define PDEC_INTENSET_MC0 (_U_(1) << PDEC_INTENSET_MC0_Pos)
|
| 347 | #define PDEC_INTENSET_MC1_Pos 5 /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
|
| 348 | #define PDEC_INTENSET_MC1 (_U_(1) << PDEC_INTENSET_MC1_Pos)
|
| 349 | #define PDEC_INTENSET_MC_Pos 4 /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
|
| 350 | #define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos)
|
| 351 | #define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
|
| 352 | #define PDEC_INTENSET_MASK _U_(0x3F) /**< \brief (PDEC_INTENSET) MASK Register */
|
| 353 |
|
| 354 | /* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
|
| 355 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 356 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 357 | struct {
|
| 358 | __I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */
|
| 359 | __I uint8_t ERR:1; /*!< bit: 1 Error */
|
| 360 | __I uint8_t DIR:1; /*!< bit: 2 Direction Change */
|
| 361 | __I uint8_t VLC:1; /*!< bit: 3 Velocity */
|
| 362 | __I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */
|
| 363 | __I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */
|
| 364 | __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 365 | } bit; /*!< Structure used for bit access */
|
| 366 | struct {
|
| 367 | __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
| 368 | __I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */
|
| 369 | __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 370 | } vec; /*!< Structure used for vec access */
|
| 371 | uint8_t reg; /*!< Type used for register access */
|
| 372 | } PDEC_INTFLAG_Type;
|
| 373 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 374 |
|
| 375 | #define PDEC_INTFLAG_OFFSET 0x0A /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
|
| 376 | #define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
| 377 |
|
| 378 | #define PDEC_INTFLAG_OVF_Pos 0 /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
|
| 379 | #define PDEC_INTFLAG_OVF (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
|
| 380 | #define PDEC_INTFLAG_ERR_Pos 1 /**< \brief (PDEC_INTFLAG) Error */
|
| 381 | #define PDEC_INTFLAG_ERR (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
|
| 382 | #define PDEC_INTFLAG_DIR_Pos 2 /**< \brief (PDEC_INTFLAG) Direction Change */
|
| 383 | #define PDEC_INTFLAG_DIR (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
|
| 384 | #define PDEC_INTFLAG_VLC_Pos 3 /**< \brief (PDEC_INTFLAG) Velocity */
|
| 385 | #define PDEC_INTFLAG_VLC (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
|
| 386 | #define PDEC_INTFLAG_MC0_Pos 4 /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
|
| 387 | #define PDEC_INTFLAG_MC0 (_U_(1) << PDEC_INTFLAG_MC0_Pos)
|
| 388 | #define PDEC_INTFLAG_MC1_Pos 5 /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
|
| 389 | #define PDEC_INTFLAG_MC1 (_U_(1) << PDEC_INTFLAG_MC1_Pos)
|
| 390 | #define PDEC_INTFLAG_MC_Pos 4 /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
|
| 391 | #define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
|
| 392 | #define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
|
| 393 | #define PDEC_INTFLAG_MASK _U_(0x3F) /**< \brief (PDEC_INTFLAG) MASK Register */
|
| 394 |
|
| 395 | /* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
|
| 396 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 397 | typedef union {
|
| 398 | struct {
|
| 399 | uint16_t QERR:1; /*!< bit: 0 Quadrature Error Flag */
|
| 400 | uint16_t IDXERR:1; /*!< bit: 1 Index Error Flag */
|
| 401 | uint16_t MPERR:1; /*!< bit: 2 Missing Pulse Error flag */
|
| 402 | uint16_t :1; /*!< bit: 3 Reserved */
|
| 403 | uint16_t WINERR:1; /*!< bit: 4 Window Error Flag */
|
| 404 | uint16_t HERR:1; /*!< bit: 5 Hall Error Flag */
|
| 405 | uint16_t STOP:1; /*!< bit: 6 Stop */
|
| 406 | uint16_t DIR:1; /*!< bit: 7 Direction Status Flag */
|
| 407 | uint16_t PRESCBUFV:1; /*!< bit: 8 Prescaler Buffer Valid */
|
| 408 | uint16_t FILTERBUFV:1; /*!< bit: 9 Filter Buffer Valid */
|
| 409 | uint16_t :2; /*!< bit: 10..11 Reserved */
|
| 410 | uint16_t CCBUFV0:1; /*!< bit: 12 Compare Channel 0 Buffer Valid */
|
| 411 | uint16_t CCBUFV1:1; /*!< bit: 13 Compare Channel 1 Buffer Valid */
|
| 412 | uint16_t :2; /*!< bit: 14..15 Reserved */
|
| 413 | } bit; /*!< Structure used for bit access */
|
| 414 | struct {
|
| 415 | uint16_t :12; /*!< bit: 0..11 Reserved */
|
| 416 | uint16_t CCBUFV:2; /*!< bit: 12..13 Compare Channel x Buffer Valid */
|
| 417 | uint16_t :2; /*!< bit: 14..15 Reserved */
|
| 418 | } vec; /*!< Structure used for vec access */
|
| 419 | uint16_t reg; /*!< Type used for register access */
|
| 420 | } PDEC_STATUS_Type;
|
| 421 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 422 |
|
| 423 | #define PDEC_STATUS_OFFSET 0x0C /**< \brief (PDEC_STATUS offset) Status */
|
| 424 | #define PDEC_STATUS_RESETVALUE _U_(0x0040) /**< \brief (PDEC_STATUS reset_value) Status */
|
| 425 |
|
| 426 | #define PDEC_STATUS_QERR_Pos 0 /**< \brief (PDEC_STATUS) Quadrature Error Flag */
|
| 427 | #define PDEC_STATUS_QERR (_U_(0x1) << PDEC_STATUS_QERR_Pos)
|
| 428 | #define PDEC_STATUS_IDXERR_Pos 1 /**< \brief (PDEC_STATUS) Index Error Flag */
|
| 429 | #define PDEC_STATUS_IDXERR (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
|
| 430 | #define PDEC_STATUS_MPERR_Pos 2 /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
|
| 431 | #define PDEC_STATUS_MPERR (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
|
| 432 | #define PDEC_STATUS_WINERR_Pos 4 /**< \brief (PDEC_STATUS) Window Error Flag */
|
| 433 | #define PDEC_STATUS_WINERR (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
|
| 434 | #define PDEC_STATUS_HERR_Pos 5 /**< \brief (PDEC_STATUS) Hall Error Flag */
|
| 435 | #define PDEC_STATUS_HERR (_U_(0x1) << PDEC_STATUS_HERR_Pos)
|
| 436 | #define PDEC_STATUS_STOP_Pos 6 /**< \brief (PDEC_STATUS) Stop */
|
| 437 | #define PDEC_STATUS_STOP (_U_(0x1) << PDEC_STATUS_STOP_Pos)
|
| 438 | #define PDEC_STATUS_DIR_Pos 7 /**< \brief (PDEC_STATUS) Direction Status Flag */
|
| 439 | #define PDEC_STATUS_DIR (_U_(0x1) << PDEC_STATUS_DIR_Pos)
|
| 440 | #define PDEC_STATUS_PRESCBUFV_Pos 8 /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
|
| 441 | #define PDEC_STATUS_PRESCBUFV (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
|
| 442 | #define PDEC_STATUS_FILTERBUFV_Pos 9 /**< \brief (PDEC_STATUS) Filter Buffer Valid */
|
| 443 | #define PDEC_STATUS_FILTERBUFV (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
|
| 444 | #define PDEC_STATUS_CCBUFV0_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
|
| 445 | #define PDEC_STATUS_CCBUFV0 (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
|
| 446 | #define PDEC_STATUS_CCBUFV1_Pos 13 /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
|
| 447 | #define PDEC_STATUS_CCBUFV1 (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
|
| 448 | #define PDEC_STATUS_CCBUFV_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
|
| 449 | #define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
|
| 450 | #define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
|
| 451 | #define PDEC_STATUS_MASK _U_(0x33F7) /**< \brief (PDEC_STATUS) MASK Register */
|
| 452 |
|
| 453 | /* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
|
| 454 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 455 | typedef union {
|
| 456 | struct {
|
| 457 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
|
| 458 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
| 459 | } bit; /*!< Structure used for bit access */
|
| 460 | uint8_t reg; /*!< Type used for register access */
|
| 461 | } PDEC_DBGCTRL_Type;
|
| 462 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 463 |
|
| 464 | #define PDEC_DBGCTRL_OFFSET 0x0F /**< \brief (PDEC_DBGCTRL offset) Debug Control */
|
| 465 | #define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
|
| 466 |
|
| 467 | #define PDEC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
|
| 468 | #define PDEC_DBGCTRL_DBGRUN (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
|
| 469 | #define PDEC_DBGCTRL_MASK _U_(0x01) /**< \brief (PDEC_DBGCTRL) MASK Register */
|
| 470 |
|
| 471 | /* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/ 32) Synchronization Status -------- */
|
| 472 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 473 | typedef union {
|
| 474 | struct {
|
| 475 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
| 476 | uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
|
| 477 | uint32_t CTRLB:1; /*!< bit: 2 Control B Synchronization Busy */
|
| 478 | uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */
|
| 479 | uint32_t PRESC:1; /*!< bit: 4 Prescaler Synchronization Busy */
|
| 480 | uint32_t FILTER:1; /*!< bit: 5 Filter Synchronization Busy */
|
| 481 | uint32_t COUNT:1; /*!< bit: 6 Count Synchronization Busy */
|
| 482 | uint32_t CC0:1; /*!< bit: 7 Compare Channel 0 Synchronization Busy */
|
| 483 | uint32_t CC1:1; /*!< bit: 8 Compare Channel 1 Synchronization Busy */
|
| 484 | uint32_t :23; /*!< bit: 9..31 Reserved */
|
| 485 | } bit; /*!< Structure used for bit access */
|
| 486 | struct {
|
| 487 | uint32_t :7; /*!< bit: 0.. 6 Reserved */
|
| 488 | uint32_t CC:2; /*!< bit: 7.. 8 Compare Channel x Synchronization Busy */
|
| 489 | uint32_t :23; /*!< bit: 9..31 Reserved */
|
| 490 | } vec; /*!< Structure used for vec access */
|
| 491 | uint32_t reg; /*!< Type used for register access */
|
| 492 | } PDEC_SYNCBUSY_Type;
|
| 493 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 494 |
|
| 495 | #define PDEC_SYNCBUSY_OFFSET 0x10 /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
|
| 496 | #define PDEC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
|
| 497 |
|
| 498 | #define PDEC_SYNCBUSY_SWRST_Pos 0 /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
|
| 499 | #define PDEC_SYNCBUSY_SWRST (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
|
| 500 | #define PDEC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
|
| 501 | #define PDEC_SYNCBUSY_ENABLE (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
|
| 502 | #define PDEC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
|
| 503 | #define PDEC_SYNCBUSY_CTRLB (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
|
| 504 | #define PDEC_SYNCBUSY_STATUS_Pos 3 /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
|
| 505 | #define PDEC_SYNCBUSY_STATUS (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
|
| 506 | #define PDEC_SYNCBUSY_PRESC_Pos 4 /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
|
| 507 | #define PDEC_SYNCBUSY_PRESC (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
|
| 508 | #define PDEC_SYNCBUSY_FILTER_Pos 5 /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
|
| 509 | #define PDEC_SYNCBUSY_FILTER (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
|
| 510 | #define PDEC_SYNCBUSY_COUNT_Pos 6 /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
|
| 511 | #define PDEC_SYNCBUSY_COUNT (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
|
| 512 | #define PDEC_SYNCBUSY_CC0_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
|
| 513 | #define PDEC_SYNCBUSY_CC0 (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
|
| 514 | #define PDEC_SYNCBUSY_CC1_Pos 8 /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
|
| 515 | #define PDEC_SYNCBUSY_CC1 (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
|
| 516 | #define PDEC_SYNCBUSY_CC_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
|
| 517 | #define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
|
| 518 | #define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
|
| 519 | #define PDEC_SYNCBUSY_MASK _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
|
| 520 |
|
| 521 | /* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
|
| 522 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 523 | typedef union {
|
| 524 | struct {
|
| 525 | uint8_t PRESC:4; /*!< bit: 0.. 3 Prescaler Value */
|
| 526 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
| 527 | } bit; /*!< Structure used for bit access */
|
| 528 | uint8_t reg; /*!< Type used for register access */
|
| 529 | } PDEC_PRESC_Type;
|
| 530 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 531 |
|
| 532 | #define PDEC_PRESC_OFFSET 0x14 /**< \brief (PDEC_PRESC offset) Prescaler Value */
|
| 533 | #define PDEC_PRESC_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
|
| 534 |
|
| 535 | #define PDEC_PRESC_PRESC_Pos 0 /**< \brief (PDEC_PRESC) Prescaler Value */
|
| 536 | #define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
|
| 537 | #define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
|
| 538 | #define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESC) No division */
|
| 539 | #define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESC) Divide by 2 */
|
| 540 | #define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESC) Divide by 4 */
|
| 541 | #define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESC) Divide by 8 */
|
| 542 | #define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESC) Divide by 16 */
|
| 543 | #define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESC) Divide by 32 */
|
| 544 | #define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESC) Divide by 64 */
|
| 545 | #define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESC) Divide by 128 */
|
| 546 | #define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESC) Divide by 256 */
|
| 547 | #define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESC) Divide by 512 */
|
| 548 | #define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESC) Divide by 1024 */
|
| 549 | #define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos)
|
| 550 | #define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos)
|
| 551 | #define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos)
|
| 552 | #define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos)
|
| 553 | #define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos)
|
| 554 | #define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos)
|
| 555 | #define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos)
|
| 556 | #define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos)
|
| 557 | #define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos)
|
| 558 | #define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos)
|
| 559 | #define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos)
|
| 560 | #define PDEC_PRESC_MASK _U_(0x0F) /**< \brief (PDEC_PRESC) MASK Register */
|
| 561 |
|
| 562 | /* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
|
| 563 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 564 | typedef union {
|
| 565 | struct {
|
| 566 | uint8_t FILTER:8; /*!< bit: 0.. 7 Filter Value */
|
| 567 | } bit; /*!< Structure used for bit access */
|
| 568 | uint8_t reg; /*!< Type used for register access */
|
| 569 | } PDEC_FILTER_Type;
|
| 570 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 571 |
|
| 572 | #define PDEC_FILTER_OFFSET 0x15 /**< \brief (PDEC_FILTER offset) Filter Value */
|
| 573 | #define PDEC_FILTER_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTER reset_value) Filter Value */
|
| 574 |
|
| 575 | #define PDEC_FILTER_FILTER_Pos 0 /**< \brief (PDEC_FILTER) Filter Value */
|
| 576 | #define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
|
| 577 | #define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
|
| 578 | #define PDEC_FILTER_MASK _U_(0xFF) /**< \brief (PDEC_FILTER) MASK Register */
|
| 579 |
|
| 580 | /* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
|
| 581 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 582 | typedef union {
|
| 583 | struct {
|
| 584 | uint8_t PRESCBUF:4; /*!< bit: 0.. 3 Prescaler Buffer Value */
|
| 585 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
| 586 | } bit; /*!< Structure used for bit access */
|
| 587 | uint8_t reg; /*!< Type used for register access */
|
| 588 | } PDEC_PRESCBUF_Type;
|
| 589 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 590 |
|
| 591 | #define PDEC_PRESCBUF_OFFSET 0x18 /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
|
| 592 | #define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
|
| 593 |
|
| 594 | #define PDEC_PRESCBUF_PRESCBUF_Pos 0 /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
|
| 595 | #define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 596 | #define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
|
| 597 | #define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESCBUF) No division */
|
| 598 | #define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESCBUF) Divide by 2 */
|
| 599 | #define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESCBUF) Divide by 4 */
|
| 600 | #define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESCBUF) Divide by 8 */
|
| 601 | #define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESCBUF) Divide by 16 */
|
| 602 | #define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESCBUF) Divide by 32 */
|
| 603 | #define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESCBUF) Divide by 64 */
|
| 604 | #define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESCBUF) Divide by 128 */
|
| 605 | #define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESCBUF) Divide by 256 */
|
| 606 | #define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESCBUF) Divide by 512 */
|
| 607 | #define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
|
| 608 | #define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 609 | #define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 610 | #define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 611 | #define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 612 | #define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 613 | #define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 614 | #define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 615 | #define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 616 | #define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 617 | #define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 618 | #define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
|
| 619 | #define PDEC_PRESCBUF_MASK _U_(0x0F) /**< \brief (PDEC_PRESCBUF) MASK Register */
|
| 620 |
|
| 621 | /* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
|
| 622 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 623 | typedef union {
|
| 624 | struct {
|
| 625 | uint8_t FILTERBUF:8; /*!< bit: 0.. 7 Filter Buffer Value */
|
| 626 | } bit; /*!< Structure used for bit access */
|
| 627 | uint8_t reg; /*!< Type used for register access */
|
| 628 | } PDEC_FILTERBUF_Type;
|
| 629 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 630 |
|
| 631 | #define PDEC_FILTERBUF_OFFSET 0x19 /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
|
| 632 | #define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
|
| 633 |
|
| 634 | #define PDEC_FILTERBUF_FILTERBUF_Pos 0 /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
|
| 635 | #define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
|
| 636 | #define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
|
| 637 | #define PDEC_FILTERBUF_MASK _U_(0xFF) /**< \brief (PDEC_FILTERBUF) MASK Register */
|
| 638 |
|
| 639 | /* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
|
| 640 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 641 | typedef union {
|
| 642 | struct {
|
| 643 | uint32_t COUNT:16; /*!< bit: 0..15 Counter Value */
|
| 644 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 645 | } bit; /*!< Structure used for bit access */
|
| 646 | uint32_t reg; /*!< Type used for register access */
|
| 647 | } PDEC_COUNT_Type;
|
| 648 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 649 |
|
| 650 | #define PDEC_COUNT_OFFSET 0x1C /**< \brief (PDEC_COUNT offset) Counter Value */
|
| 651 | #define PDEC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
|
| 652 |
|
| 653 | #define PDEC_COUNT_COUNT_Pos 0 /**< \brief (PDEC_COUNT) Counter Value */
|
| 654 | #define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
|
| 655 | #define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
|
| 656 | #define PDEC_COUNT_MASK _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
|
| 657 |
|
| 658 | /* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
|
| 659 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 660 | typedef union {
|
| 661 | struct {
|
| 662 | uint32_t CC:16; /*!< bit: 0..15 Channel Compare Value */
|
| 663 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 664 | } bit; /*!< Structure used for bit access */
|
| 665 | uint32_t reg; /*!< Type used for register access */
|
| 666 | } PDEC_CC_Type;
|
| 667 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 668 |
|
| 669 | #define PDEC_CC_OFFSET 0x20 /**< \brief (PDEC_CC offset) Channel n Compare Value */
|
| 670 | #define PDEC_CC_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
|
| 671 |
|
| 672 | #define PDEC_CC_CC_Pos 0 /**< \brief (PDEC_CC) Channel Compare Value */
|
| 673 | #define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos)
|
| 674 | #define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
|
| 675 | #define PDEC_CC_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
|
| 676 |
|
| 677 | /* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
|
| 678 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 679 | typedef union {
|
| 680 | struct {
|
| 681 | uint32_t CCBUF:16; /*!< bit: 0..15 Channel Compare Buffer Value */
|
| 682 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 683 | } bit; /*!< Structure used for bit access */
|
| 684 | uint32_t reg; /*!< Type used for register access */
|
| 685 | } PDEC_CCBUF_Type;
|
| 686 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 687 |
|
| 688 | #define PDEC_CCBUF_OFFSET 0x30 /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
|
| 689 | #define PDEC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
|
| 690 |
|
| 691 | #define PDEC_CCBUF_CCBUF_Pos 0 /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
|
| 692 | #define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
|
| 693 | #define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
|
| 694 | #define PDEC_CCBUF_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
|
| 695 |
|
| 696 | /** \brief PDEC hardware registers */
|
| 697 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 698 | typedef struct {
|
| 699 | __IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
|
| 700 | __IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
|
| 701 | __IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
|
| 702 | __IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
|
| 703 | __IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
|
| 704 | __IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
|
| 705 | __IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
|
| 706 | RoReg8 Reserved1[0x1];
|
| 707 | __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */
|
| 708 | RoReg8 Reserved2[0x1];
|
| 709 | __IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
|
| 710 | __I PDEC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
|
| 711 | __IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */
|
| 712 | __IO PDEC_FILTER_Type FILTER; /**< \brief Offset: 0x15 (R/W 8) Filter Value */
|
| 713 | RoReg8 Reserved3[0x2];
|
| 714 | __IO PDEC_PRESCBUF_Type PRESCBUF; /**< \brief Offset: 0x18 (R/W 8) Prescaler Buffer Value */
|
| 715 | __IO PDEC_FILTERBUF_Type FILTERBUF; /**< \brief Offset: 0x19 (R/W 8) Filter Buffer Value */
|
| 716 | RoReg8 Reserved4[0x2];
|
| 717 | __IO PDEC_COUNT_Type COUNT; /**< \brief Offset: 0x1C (R/W 32) Counter Value */
|
| 718 | __IO PDEC_CC_Type CC[2]; /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
|
| 719 | RoReg8 Reserved5[0x8];
|
| 720 | __IO PDEC_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
|
| 721 | } Pdec;
|
| 722 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 723 |
|
| 724 | /*@}*/
|
| 725 |
|
| 726 | #endif /* _SAME54_PDEC_COMPONENT_ */
|