| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for PCC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_PCC_COMPONENT_
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| 31 | #define _SAME54_PCC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR PCC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_PCC Parallel Capture Controller */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define PCC_U2017
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| 40 | #define REV_PCC 0x110
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| 41 |
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| 42 | /* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */
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| 47 | uint32_t :3; /*!< bit: 1.. 3 Reserved */
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| 48 | uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */
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| 49 | uint32_t :2; /*!< bit: 6.. 7 Reserved */
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| 50 | uint32_t SCALE:1; /*!< bit: 8 Scale data */
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| 51 | uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */
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| 52 | uint32_t HALFS:1; /*!< bit: 10 Half Sampling */
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| 53 | uint32_t FRSTS:1; /*!< bit: 11 First sample */
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| 54 | uint32_t :4; /*!< bit: 12..15 Reserved */
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| 55 | uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */
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| 56 | uint32_t :11; /*!< bit: 19..29 Reserved */
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| 57 | uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */
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| 58 | } bit; /*!< Structure used for bit access */
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| 59 | uint32_t reg; /*!< Type used for register access */
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| 60 | } PCC_MR_Type;
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| 61 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 62 |
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| 63 | #define PCC_MR_OFFSET 0x00 /**< \brief (PCC_MR offset) Mode Register */
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| 64 | #define PCC_MR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
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| 65 |
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| 66 | #define PCC_MR_PCEN_Pos 0 /**< \brief (PCC_MR) Parallel Capture Enable */
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| 67 | #define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
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| 68 | #define PCC_MR_DSIZE_Pos 4 /**< \brief (PCC_MR) Data size */
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| 69 | #define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
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| 70 | #define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
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| 71 | #define PCC_MR_SCALE_Pos 8 /**< \brief (PCC_MR) Scale data */
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| 72 | #define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
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| 73 | #define PCC_MR_ALWYS_Pos 9 /**< \brief (PCC_MR) Always Sampling */
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| 74 | #define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
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| 75 | #define PCC_MR_HALFS_Pos 10 /**< \brief (PCC_MR) Half Sampling */
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| 76 | #define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
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| 77 | #define PCC_MR_FRSTS_Pos 11 /**< \brief (PCC_MR) First sample */
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| 78 | #define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
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| 79 | #define PCC_MR_ISIZE_Pos 16 /**< \brief (PCC_MR) Input Data Size */
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| 80 | #define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
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| 81 | #define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
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| 82 | #define PCC_MR_CID_Pos 30 /**< \brief (PCC_MR) Clear If Disabled */
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| 83 | #define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
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| 84 | #define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
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| 85 | #define PCC_MR_MASK _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
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| 86 |
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| 87 | /* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
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| 88 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 89 | typedef union {
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| 90 | struct {
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| 91 | uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
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| 92 | uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */
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| 93 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 94 | } bit; /*!< Structure used for bit access */
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| 95 | uint32_t reg; /*!< Type used for register access */
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| 96 | } PCC_IER_Type;
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| 97 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 98 |
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| 99 | #define PCC_IER_OFFSET 0x04 /**< \brief (PCC_IER offset) Interrupt Enable Register */
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| 100 | #define PCC_IER_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
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| 101 |
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| 102 | #define PCC_IER_DRDY_Pos 0 /**< \brief (PCC_IER) Data Ready Interrupt Enable */
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| 103 | #define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
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| 104 | #define PCC_IER_OVRE_Pos 1 /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
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| 105 | #define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
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| 106 | #define PCC_IER_MASK _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
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| 107 |
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| 108 | /* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
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| 109 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 110 | typedef union {
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| 111 | struct {
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| 112 | uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */
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| 113 | uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */
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| 114 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 115 | } bit; /*!< Structure used for bit access */
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| 116 | uint32_t reg; /*!< Type used for register access */
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| 117 | } PCC_IDR_Type;
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| 118 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 119 |
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| 120 | #define PCC_IDR_OFFSET 0x08 /**< \brief (PCC_IDR offset) Interrupt Disable Register */
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| 121 | #define PCC_IDR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
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| 122 |
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| 123 | #define PCC_IDR_DRDY_Pos 0 /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
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| 124 | #define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
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| 125 | #define PCC_IDR_OVRE_Pos 1 /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
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| 126 | #define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
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| 127 | #define PCC_IDR_MASK _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
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| 128 |
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| 129 | /* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */
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| 130 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 131 | typedef union {
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| 132 | struct {
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| 133 | uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */
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| 134 | uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */
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| 135 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 136 | } bit; /*!< Structure used for bit access */
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| 137 | uint32_t reg; /*!< Type used for register access */
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| 138 | } PCC_IMR_Type;
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| 139 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 140 |
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| 141 | #define PCC_IMR_OFFSET 0x0C /**< \brief (PCC_IMR offset) Interrupt Mask Register */
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| 142 | #define PCC_IMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
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| 143 |
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| 144 | #define PCC_IMR_DRDY_Pos 0 /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
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| 145 | #define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
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| 146 | #define PCC_IMR_OVRE_Pos 1 /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
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| 147 | #define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
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| 148 | #define PCC_IMR_MASK _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
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| 149 |
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| 150 | /* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */
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| 151 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 152 | typedef union {
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| 153 | struct {
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| 154 | uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */
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| 155 | uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */
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| 156 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 157 | } bit; /*!< Structure used for bit access */
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| 158 | uint32_t reg; /*!< Type used for register access */
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| 159 | } PCC_ISR_Type;
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| 160 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 161 |
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| 162 | #define PCC_ISR_OFFSET 0x10 /**< \brief (PCC_ISR offset) Interrupt Status Register */
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| 163 | #define PCC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
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| 164 |
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| 165 | #define PCC_ISR_DRDY_Pos 0 /**< \brief (PCC_ISR) Data Ready Interrupt Status */
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| 166 | #define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
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| 167 | #define PCC_ISR_OVRE_Pos 1 /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
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| 168 | #define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
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| 169 | #define PCC_ISR_MASK _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
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| 170 |
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| 171 | /* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */
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| 172 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 173 | typedef union {
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| 174 | struct {
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| 175 | uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */
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| 176 | } bit; /*!< Structure used for bit access */
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| 177 | uint32_t reg; /*!< Type used for register access */
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| 178 | } PCC_RHR_Type;
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| 179 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 180 |
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| 181 | #define PCC_RHR_OFFSET 0x14 /**< \brief (PCC_RHR offset) Reception Holding Register */
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| 182 | #define PCC_RHR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
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| 183 |
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| 184 | #define PCC_RHR_RDATA_Pos 0 /**< \brief (PCC_RHR) Reception Data */
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| 185 | #define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
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| 186 | #define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
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| 187 | #define PCC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
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| 188 |
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| 189 | /* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
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| 190 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 191 | typedef union {
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| 192 | struct {
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| 193 | uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */
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| 194 | uint32_t :7; /*!< bit: 1.. 7 Reserved */
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| 195 | uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */
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| 196 | } bit; /*!< Structure used for bit access */
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| 197 | uint32_t reg; /*!< Type used for register access */
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| 198 | } PCC_WPMR_Type;
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| 199 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 200 |
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| 201 | #define PCC_WPMR_OFFSET 0xE0 /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
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| 202 | #define PCC_WPMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
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| 203 |
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| 204 | #define PCC_WPMR_WPEN_Pos 0 /**< \brief (PCC_WPMR) Write Protection Enable */
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| 205 | #define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
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| 206 | #define PCC_WPMR_WPKEY_Pos 8 /**< \brief (PCC_WPMR) Write Protection Key */
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| 207 | #define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
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| 208 | #define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
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| 209 | #define PCC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
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| 210 |
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| 211 | /* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */
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| 212 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 213 | typedef union {
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| 214 | struct {
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| 215 | uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */
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| 216 | uint32_t :7; /*!< bit: 1.. 7 Reserved */
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| 217 | uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */
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| 218 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 219 | } bit; /*!< Structure used for bit access */
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| 220 | uint32_t reg; /*!< Type used for register access */
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| 221 | } PCC_WPSR_Type;
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| 222 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 223 |
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| 224 | #define PCC_WPSR_OFFSET 0xE4 /**< \brief (PCC_WPSR offset) Write Protection Status Register */
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| 225 | #define PCC_WPSR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
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| 226 |
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| 227 | #define PCC_WPSR_WPVS_Pos 0 /**< \brief (PCC_WPSR) Write Protection Violation Source */
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| 228 | #define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
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| 229 | #define PCC_WPSR_WPVSRC_Pos 8 /**< \brief (PCC_WPSR) Write Protection Violation Status */
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| 230 | #define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
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| 231 | #define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
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| 232 | #define PCC_WPSR_MASK _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
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| 233 |
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| 234 | /** \brief PCC hardware registers */
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| 235 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 236 | typedef struct {
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| 237 | __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */
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| 238 | __O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
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| 239 | __O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
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| 240 | __I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */
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| 241 | __I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */
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| 242 | __I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */
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| 243 | RoReg8 Reserved1[0xC8];
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| 244 | __IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
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| 245 | __I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */
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| 246 | } Pcc;
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| 247 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 248 |
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| 249 | /*@}*/
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| 250 |
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| 251 | #endif /* _SAME54_PCC_COMPONENT_ */
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