| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for MCLK
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_MCLK_COMPONENT_
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| 31 | #define _SAME54_MCLK_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR MCLK */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_MCLK Main Clock */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define MCLK_U2408
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| 40 | #define REV_MCLK 0x100
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| 41 |
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| 42 | /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
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| 47 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 48 | } bit; /*!< Structure used for bit access */
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| 49 | uint8_t reg; /*!< Type used for register access */
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| 50 | } MCLK_INTENCLR_Type;
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| 51 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 52 |
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| 53 | #define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
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| 54 | #define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
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| 55 |
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| 56 | #define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
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| 57 | #define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
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| 58 | #define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */
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| 59 |
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| 60 | /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
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| 61 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 62 | typedef union {
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| 63 | struct {
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| 64 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
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| 65 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 66 | } bit; /*!< Structure used for bit access */
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| 67 | uint8_t reg; /*!< Type used for register access */
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| 68 | } MCLK_INTENSET_Type;
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| 69 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 70 |
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| 71 | #define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
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| 72 | #define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
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| 73 |
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| 74 | #define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
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| 75 | #define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
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| 76 | #define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */
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| 77 |
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| 78 | /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 79 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 80 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 81 | struct {
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| 82 | __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
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| 83 | __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 84 | } bit; /*!< Structure used for bit access */
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| 85 | uint8_t reg; /*!< Type used for register access */
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| 86 | } MCLK_INTFLAG_Type;
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| 87 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 88 |
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| 89 | #define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
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| 90 | #define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 91 |
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| 92 | #define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */
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| 93 | #define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
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| 94 | #define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */
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| 95 |
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| 96 | /* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */
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| 97 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 98 | typedef union {
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| 99 | struct {
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| 100 | uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */
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| 101 | } bit; /*!< Structure used for bit access */
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| 102 | uint8_t reg; /*!< Type used for register access */
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| 103 | } MCLK_HSDIV_Type;
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| 104 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 105 |
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| 106 | #define MCLK_HSDIV_OFFSET 0x04 /**< \brief (MCLK_HSDIV offset) HS Clock Division */
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| 107 | #define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
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| 108 |
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| 109 | #define MCLK_HSDIV_DIV_Pos 0 /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
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| 110 | #define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
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| 111 | #define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
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| 112 | #define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_HSDIV) Divide by 1 */
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| 113 | #define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
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| 114 | #define MCLK_HSDIV_MASK _U_(0xFF) /**< \brief (MCLK_HSDIV) MASK Register */
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| 115 |
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| 116 | /* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
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| 117 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 118 | typedef union {
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| 119 | struct {
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| 120 | uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */
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| 121 | } bit; /*!< Structure used for bit access */
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| 122 | uint8_t reg; /*!< Type used for register access */
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| 123 | } MCLK_CPUDIV_Type;
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| 124 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 125 |
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| 126 | #define MCLK_CPUDIV_OFFSET 0x05 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
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| 127 | #define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
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| 128 |
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| 129 | #define MCLK_CPUDIV_DIV_Pos 0 /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
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| 130 | #define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
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| 131 | #define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
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| 132 | #define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */
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| 133 | #define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */
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| 134 | #define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */
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| 135 | #define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */
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| 136 | #define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */
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| 137 | #define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */
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| 138 | #define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */
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| 139 | #define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */
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| 140 | #define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
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| 141 | #define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
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| 142 | #define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
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| 143 | #define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
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| 144 | #define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
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| 145 | #define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
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| 146 | #define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
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| 147 | #define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
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| 148 | #define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */
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| 149 |
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| 150 | /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
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| 151 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 152 | typedef union {
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| 153 | struct {
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| 154 | uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
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| 155 | uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
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| 156 | uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
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| 157 | uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */
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| 158 | uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */
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| 159 | uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */
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| 160 | uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */
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| 161 | uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */
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| 162 | uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */
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| 163 | uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */
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| 164 | uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */
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| 165 | uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */
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| 166 | uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */
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| 167 | uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */
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| 168 | uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */
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| 169 | uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */
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| 170 | uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */
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| 171 | uint32_t CAN0_:1; /*!< bit: 17 CAN0 AHB Clock Mask */
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| 172 | uint32_t CAN1_:1; /*!< bit: 18 CAN1 AHB Clock Mask */
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| 173 | uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */
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| 174 | uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */
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| 175 | uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */
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| 176 | uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */
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| 177 | uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */
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| 178 | uint32_t :8; /*!< bit: 24..31 Reserved */
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| 179 | } bit; /*!< Structure used for bit access */
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| 180 | uint32_t reg; /*!< Type used for register access */
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| 181 | } MCLK_AHBMASK_Type;
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| 182 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 183 |
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| 184 | #define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */
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| 185 | #define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
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| 186 |
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| 187 | #define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
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| 188 | #define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
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| 189 | #define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
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| 190 | #define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
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| 191 | #define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
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| 192 | #define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
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| 193 | #define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
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| 194 | #define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
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| 195 | #define MCLK_AHBMASK_DSU_Pos 4 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
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| 196 | #define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
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| 197 | #define MCLK_AHBMASK_HMATRIX_Pos 5 /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
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| 198 | #define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
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| 199 | #define MCLK_AHBMASK_NVMCTRL_Pos 6 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
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| 200 | #define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
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| 201 | #define MCLK_AHBMASK_HSRAM_Pos 7 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
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| 202 | #define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
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| 203 | #define MCLK_AHBMASK_CMCC_Pos 8 /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
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| 204 | #define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
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| 205 | #define MCLK_AHBMASK_DMAC_Pos 9 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
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| 206 | #define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
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| 207 | #define MCLK_AHBMASK_USB_Pos 10 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
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| 208 | #define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
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| 209 | #define MCLK_AHBMASK_BKUPRAM_Pos 11 /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
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| 210 | #define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
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| 211 | #define MCLK_AHBMASK_PAC_Pos 12 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
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| 212 | #define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
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| 213 | #define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
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| 214 | #define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
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| 215 | #define MCLK_AHBMASK_GMAC_Pos 14 /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */
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| 216 | #define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
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| 217 | #define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
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| 218 | #define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
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| 219 | #define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
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| 220 | #define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
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| 221 | #define MCLK_AHBMASK_CAN0_Pos 17 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */
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| 222 | #define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
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| 223 | #define MCLK_AHBMASK_CAN1_Pos 18 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */
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| 224 | #define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
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| 225 | #define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
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| 226 | #define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
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| 227 | #define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
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| 228 | #define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
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| 229 | #define MCLK_AHBMASK_QSPI_2X_Pos 21 /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
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| 230 | #define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
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| 231 | #define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22 /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
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| 232 | #define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
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| 233 | #define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
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| 234 | #define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
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| 235 | #define MCLK_AHBMASK_MASK _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
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| 236 |
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| 237 | /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
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| 238 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 239 | typedef union {
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| 240 | struct {
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| 241 | uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */
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| 242 | uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
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| 243 | uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */
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| 244 | uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */
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| 245 | uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */
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| 246 | uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */
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| 247 | uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */
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| 248 | uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */
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| 249 | uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */
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| 250 | uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */
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| 251 | uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */
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| 252 | uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */
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| 253 | uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */
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| 254 | uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */
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| 255 | uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */
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| 256 | uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */
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| 257 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 258 | } bit; /*!< Structure used for bit access */
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| 259 | uint32_t reg; /*!< Type used for register access */
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| 260 | } MCLK_APBAMASK_Type;
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| 261 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 262 |
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| 263 | #define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */
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| 264 | #define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
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| 265 |
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| 266 | #define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
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| 267 | #define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
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| 268 | #define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
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| 269 | #define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
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| 270 | #define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
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| 271 | #define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
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| 272 | #define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
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| 273 | #define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
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| 274 | #define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
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| 275 | #define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
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| 276 | #define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
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| 277 | #define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
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| 278 | #define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
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| 279 | #define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
|
| 280 | #define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
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| 281 | #define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
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| 282 | #define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
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| 283 | #define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
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| 284 | #define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
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| 285 | #define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
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| 286 | #define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
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| 287 | #define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
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| 288 | #define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
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| 289 | #define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
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| 290 | #define MCLK_APBAMASK_SERCOM0_Pos 12 /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
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| 291 | #define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
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| 292 | #define MCLK_APBAMASK_SERCOM1_Pos 13 /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
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| 293 | #define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
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| 294 | #define MCLK_APBAMASK_TC0_Pos 14 /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
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| 295 | #define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
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| 296 | #define MCLK_APBAMASK_TC1_Pos 15 /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
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| 297 | #define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
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| 298 | #define MCLK_APBAMASK_MASK _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
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| 299 |
|
| 300 | /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
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| 301 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 302 | typedef union {
|
| 303 | struct {
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| 304 | uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */
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| 305 | uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
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| 306 | uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
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| 307 | uint32_t :1; /*!< bit: 3 Reserved */
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| 308 | uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */
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| 309 | uint32_t :1; /*!< bit: 5 Reserved */
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| 310 | uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
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| 311 | uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */
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| 312 | uint32_t :1; /*!< bit: 8 Reserved */
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| 313 | uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */
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| 314 | uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */
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| 315 | uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */
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| 316 | uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */
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| 317 | uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */
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| 318 | uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */
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| 319 | uint32_t :1; /*!< bit: 15 Reserved */
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| 320 | uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */
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| 321 | uint32_t :15; /*!< bit: 17..31 Reserved */
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| 322 | } bit; /*!< Structure used for bit access */
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| 323 | uint32_t reg; /*!< Type used for register access */
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| 324 | } MCLK_APBBMASK_Type;
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| 325 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 326 |
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| 327 | #define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */
|
| 328 | #define MCLK_APBBMASK_RESETVALUE _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
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| 329 |
|
| 330 | #define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
|
| 331 | #define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
|
| 332 | #define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
|
| 333 | #define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
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| 334 | #define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
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| 335 | #define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
|
| 336 | #define MCLK_APBBMASK_PORT_Pos 4 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
|
| 337 | #define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
|
| 338 | #define MCLK_APBBMASK_HMATRIX_Pos 6 /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
|
| 339 | #define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
|
| 340 | #define MCLK_APBBMASK_EVSYS_Pos 7 /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
|
| 341 | #define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
|
| 342 | #define MCLK_APBBMASK_SERCOM2_Pos 9 /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
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| 343 | #define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
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| 344 | #define MCLK_APBBMASK_SERCOM3_Pos 10 /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
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| 345 | #define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
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| 346 | #define MCLK_APBBMASK_TCC0_Pos 11 /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
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| 347 | #define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
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| 348 | #define MCLK_APBBMASK_TCC1_Pos 12 /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
|
| 349 | #define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
|
| 350 | #define MCLK_APBBMASK_TC2_Pos 13 /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
|
| 351 | #define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
|
| 352 | #define MCLK_APBBMASK_TC3_Pos 14 /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
|
| 353 | #define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
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| 354 | #define MCLK_APBBMASK_RAMECC_Pos 16 /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
|
| 355 | #define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
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| 356 | #define MCLK_APBBMASK_MASK _U_(0x00017ED7) /**< \brief (MCLK_APBBMASK) MASK Register */
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| 357 |
|
| 358 | /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
|
| 359 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 360 | typedef union {
|
| 361 | struct {
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| 362 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
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| 363 | uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */
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| 364 | uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */
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| 365 | uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */
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| 366 | uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */
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| 367 | uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */
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| 368 | uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */
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| 369 | uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */
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| 370 | uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */
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| 371 | uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */
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| 372 | uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */
|
| 373 | uint32_t :1; /*!< bit: 12 Reserved */
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| 374 | uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */
|
| 375 | uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */
|
| 376 | uint32_t :17; /*!< bit: 15..31 Reserved */
|
| 377 | } bit; /*!< Structure used for bit access */
|
| 378 | uint32_t reg; /*!< Type used for register access */
|
| 379 | } MCLK_APBCMASK_Type;
|
| 380 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 381 |
|
| 382 | #define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
|
| 383 | #define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
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| 384 |
|
| 385 | #define MCLK_APBCMASK_GMAC_Pos 2 /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */
|
| 386 | #define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
|
| 387 | #define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
|
| 388 | #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
|
| 389 | #define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
|
| 390 | #define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
|
| 391 | #define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
|
| 392 | #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
|
| 393 | #define MCLK_APBCMASK_TC5_Pos 6 /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
|
| 394 | #define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
|
| 395 | #define MCLK_APBCMASK_PDEC_Pos 7 /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
|
| 396 | #define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
|
| 397 | #define MCLK_APBCMASK_AC_Pos 8 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
|
| 398 | #define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
|
| 399 | #define MCLK_APBCMASK_AES_Pos 9 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
|
| 400 | #define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
|
| 401 | #define MCLK_APBCMASK_TRNG_Pos 10 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
|
| 402 | #define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
|
| 403 | #define MCLK_APBCMASK_ICM_Pos 11 /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
|
| 404 | #define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
|
| 405 | #define MCLK_APBCMASK_QSPI_Pos 13 /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
|
| 406 | #define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
|
| 407 | #define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
|
| 408 | #define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
|
| 409 | #define MCLK_APBCMASK_MASK _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */
|
| 410 |
|
| 411 | /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
|
| 412 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 413 | typedef union {
|
| 414 | struct {
|
| 415 | uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */
|
| 416 | uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */
|
| 417 | uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */
|
| 418 | uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */
|
| 419 | uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */
|
| 420 | uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */
|
| 421 | uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */
|
| 422 | uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */
|
| 423 | uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */
|
| 424 | uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */
|
| 425 | uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */
|
| 426 | uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */
|
| 427 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
| 428 | } bit; /*!< Structure used for bit access */
|
| 429 | uint32_t reg; /*!< Type used for register access */
|
| 430 | } MCLK_APBDMASK_Type;
|
| 431 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 432 |
|
| 433 | #define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */
|
| 434 | #define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
|
| 435 |
|
| 436 | #define MCLK_APBDMASK_SERCOM4_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
|
| 437 | #define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
|
| 438 | #define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
|
| 439 | #define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
|
| 440 | #define MCLK_APBDMASK_SERCOM6_Pos 2 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
|
| 441 | #define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
|
| 442 | #define MCLK_APBDMASK_SERCOM7_Pos 3 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
|
| 443 | #define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
|
| 444 | #define MCLK_APBDMASK_TCC4_Pos 4 /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
|
| 445 | #define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
|
| 446 | #define MCLK_APBDMASK_TC6_Pos 5 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
|
| 447 | #define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
|
| 448 | #define MCLK_APBDMASK_TC7_Pos 6 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
|
| 449 | #define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
|
| 450 | #define MCLK_APBDMASK_ADC0_Pos 7 /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
|
| 451 | #define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
|
| 452 | #define MCLK_APBDMASK_ADC1_Pos 8 /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
|
| 453 | #define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
|
| 454 | #define MCLK_APBDMASK_DAC_Pos 9 /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
|
| 455 | #define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
|
| 456 | #define MCLK_APBDMASK_I2S_Pos 10 /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
|
| 457 | #define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
|
| 458 | #define MCLK_APBDMASK_PCC_Pos 11 /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
|
| 459 | #define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
|
| 460 | #define MCLK_APBDMASK_MASK _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
|
| 461 |
|
| 462 | /** \brief MCLK hardware registers */
|
| 463 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 464 | typedef struct {
|
| 465 | RoReg8 Reserved1[0x1];
|
| 466 | __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */
|
| 467 | __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */
|
| 468 | __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
|
| 469 | __I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */
|
| 470 | __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */
|
| 471 | RoReg8 Reserved2[0xA];
|
| 472 | __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
|
| 473 | __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
|
| 474 | __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
|
| 475 | __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
|
| 476 | __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
|
| 477 | } Mclk;
|
| 478 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 479 |
|
| 480 | /*@}*/
|
| 481 |
|
| 482 | #endif /* _SAME54_MCLK_COMPONENT_ */
|