| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for GCLK
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_GCLK_COMPONENT_
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| 31 | #define _SAME54_GCLK_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR GCLK */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_GCLK Generic Clock Generator */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define GCLK_U2122
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| 40 | #define REV_GCLK 0x120
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| 41 |
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| 42 | /* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 48 | } bit; /*!< Structure used for bit access */
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| 49 | uint8_t reg; /*!< Type used for register access */
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| 50 | } GCLK_CTRLA_Type;
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| 51 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 52 |
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| 53 | #define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
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| 54 | #define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */
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| 55 |
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| 56 | #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
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| 57 | #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
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| 58 | #define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */
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| 59 |
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| 60 | /* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
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| 61 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 62 | typedef union {
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| 63 | struct {
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| 64 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
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| 65 | uint32_t :1; /*!< bit: 1 Reserved */
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| 66 | uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */
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| 67 | uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */
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| 68 | uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */
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| 69 | uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */
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| 70 | uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */
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| 71 | uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */
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| 72 | uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */
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| 73 | uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */
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| 74 | uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */
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| 75 | uint32_t GENCTRL9:1; /*!< bit: 11 Generic Clock Generator Control 9 Synchronization Busy bits */
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| 76 | uint32_t GENCTRL10:1; /*!< bit: 12 Generic Clock Generator Control 10 Synchronization Busy bits */
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| 77 | uint32_t GENCTRL11:1; /*!< bit: 13 Generic Clock Generator Control 11 Synchronization Busy bits */
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| 78 | uint32_t :18; /*!< bit: 14..31 Reserved */
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| 79 | } bit; /*!< Structure used for bit access */
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| 80 | struct {
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| 81 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
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| 82 | uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Busy bits */
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| 83 | uint32_t :18; /*!< bit: 14..31 Reserved */
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| 84 | } vec; /*!< Structure used for vec access */
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| 85 | uint32_t reg; /*!< Type used for register access */
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| 86 | } GCLK_SYNCBUSY_Type;
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| 87 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 88 |
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| 89 | #define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
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| 90 | #define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
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| 91 |
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| 92 | #define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
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| 93 | #define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
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| 94 | #define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
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| 95 | #define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
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| 96 | #define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
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| 97 | #define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
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| 98 | #define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
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| 99 | #define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
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| 100 | #define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
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| 101 | #define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
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| 102 | #define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
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| 103 | #define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
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| 104 | #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
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| 105 | #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
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| 106 | #define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
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| 107 | #define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
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| 108 | #define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
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| 109 | #define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
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| 110 | #define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
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| 111 | #define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
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| 112 | #define GCLK_SYNCBUSY_GENCTRL9_Pos 11 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
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| 113 | #define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
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| 114 | #define GCLK_SYNCBUSY_GENCTRL10_Pos 12 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
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| 115 | #define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
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| 116 | #define GCLK_SYNCBUSY_GENCTRL11_Pos 13 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
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| 117 | #define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
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| 118 | #define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
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| 119 | #define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 120 | #define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
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| 121 | #define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
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| 122 | #define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
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| 123 | #define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
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| 124 | #define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
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| 125 | #define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
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| 126 | #define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
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| 127 | #define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
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| 128 | #define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
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| 129 | #define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
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| 130 | #define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
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| 131 | #define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
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| 132 | #define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
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| 133 | #define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 134 | #define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 135 | #define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 136 | #define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 137 | #define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 138 | #define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 139 | #define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 140 | #define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 141 | #define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 142 | #define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 143 | #define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 144 | #define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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| 145 | #define GCLK_SYNCBUSY_MASK _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
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| 146 |
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| 147 | /* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
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| 148 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 149 | typedef union {
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| 150 | struct {
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| 151 | uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */
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| 152 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
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| 153 | uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
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| 154 | uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
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| 155 | uint32_t OOV:1; /*!< bit: 10 Output Off Value */
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| 156 | uint32_t OE:1; /*!< bit: 11 Output Enable */
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| 157 | uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
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| 158 | uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
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| 159 | uint32_t :2; /*!< bit: 14..15 Reserved */
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| 160 | uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
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| 161 | } bit; /*!< Structure used for bit access */
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| 162 | uint32_t reg; /*!< Type used for register access */
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| 163 | } GCLK_GENCTRL_Type;
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| 164 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 165 |
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| 166 | #define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
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| 167 | #define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
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| 168 |
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| 169 | #define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
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| 170 | #define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
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| 171 | #define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
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| 172 | #define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
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| 173 | #define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
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| 174 | #define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generator input pad */
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| 175 | #define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
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| 176 | #define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
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| 177 | #define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
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| 178 | #define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) DFLL output */
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| 179 | #define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL0 output */
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| 180 | #define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL1 output */
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| 181 | #define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
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| 182 | #define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
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| 183 | #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
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| 184 | #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
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| 185 | #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
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| 186 | #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
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| 187 | #define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
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| 188 | #define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
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| 189 | #define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
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| 190 | #define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
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| 191 | #define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
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| 192 | #define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
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| 193 | #define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
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| 194 | #define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
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| 195 | #define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
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| 196 | #define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
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| 197 | #define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
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| 198 | #define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
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| 199 | #define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
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| 200 | #define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
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| 201 | #define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
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| 202 | #define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
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| 203 | #define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
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| 204 | #define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
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| 205 | #define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
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| 206 |
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| 207 | /* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
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| 208 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 209 | typedef union {
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| 210 | struct {
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| 211 | uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
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| 212 | uint32_t :2; /*!< bit: 4.. 5 Reserved */
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| 213 | uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
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| 214 | uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
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| 215 | uint32_t :24; /*!< bit: 8..31 Reserved */
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| 216 | } bit; /*!< Structure used for bit access */
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| 217 | uint32_t reg; /*!< Type used for register access */
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| 218 | } GCLK_PCHCTRL_Type;
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| 219 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 220 |
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| 221 | #define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
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| 222 | #define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
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| 223 |
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| 224 | #define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
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| 225 | #define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
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| 226 | #define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
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| 227 | #define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
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| 228 | #define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
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| 229 | #define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
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| 230 | #define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
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| 231 | #define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
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| 232 | #define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
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| 233 | #define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
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| 234 | #define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
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| 235 | #define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
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| 236 | #define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
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| 237 | #define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
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| 238 | #define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
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| 239 | #define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
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| 240 | #define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
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| 241 | #define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
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| 242 | #define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
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| 243 | #define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
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| 244 | #define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
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| 245 | #define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
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| 246 | #define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
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| 247 | #define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
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| 248 | #define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
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| 249 | #define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
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| 250 | #define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
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| 251 | #define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
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| 252 | #define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
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| 253 | #define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
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| 254 | #define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
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| 255 | #define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
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| 256 |
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| 257 | /** \brief GCLK hardware registers */
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| 258 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 259 | typedef struct {
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| 260 | __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
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| 261 | RoReg8 Reserved1[0x3];
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| 262 | __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
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| 263 | RoReg8 Reserved2[0x18];
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| 264 | __IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
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| 265 | RoReg8 Reserved3[0x30];
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| 266 | __IO GCLK_PCHCTRL_Type PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
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| 267 | } Gclk;
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| 268 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 269 |
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| 270 | /*@}*/
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| 271 |
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| 272 | #endif /* _SAME54_GCLK_COMPONENT_ */
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