| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for EVSYS
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_EVSYS_COMPONENT_
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| 31 | #define _SAME54_EVSYS_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR EVSYS */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_EVSYS Event System Interface */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define EVSYS_U2504
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| 40 | #define REV_EVSYS 0x100
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| 41 |
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| 42 | /* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W 8) Control -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 48 | } bit; /*!< Structure used for bit access */
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| 49 | uint8_t reg; /*!< Type used for register access */
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| 50 | } EVSYS_CTRLA_Type;
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| 51 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 52 |
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| 53 | #define EVSYS_CTRLA_OFFSET 0x000 /**< \brief (EVSYS_CTRLA offset) Control */
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| 54 | #define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */
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| 55 |
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| 56 | #define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */
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| 57 | #define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
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| 58 | #define EVSYS_CTRLA_MASK _U_(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */
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| 59 |
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| 60 | /* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
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| 61 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 62 | typedef union {
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| 63 | struct {
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| 64 | uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */
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| 65 | uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */
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| 66 | uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */
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| 67 | uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */
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| 68 | uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */
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| 69 | uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */
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| 70 | uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */
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| 71 | uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */
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| 72 | uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */
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| 73 | uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */
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| 74 | uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */
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| 75 | uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */
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| 76 | uint32_t CHANNEL12:1; /*!< bit: 12 Channel 12 Software Selection */
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| 77 | uint32_t CHANNEL13:1; /*!< bit: 13 Channel 13 Software Selection */
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| 78 | uint32_t CHANNEL14:1; /*!< bit: 14 Channel 14 Software Selection */
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| 79 | uint32_t CHANNEL15:1; /*!< bit: 15 Channel 15 Software Selection */
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| 80 | uint32_t CHANNEL16:1; /*!< bit: 16 Channel 16 Software Selection */
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| 81 | uint32_t CHANNEL17:1; /*!< bit: 17 Channel 17 Software Selection */
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| 82 | uint32_t CHANNEL18:1; /*!< bit: 18 Channel 18 Software Selection */
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| 83 | uint32_t CHANNEL19:1; /*!< bit: 19 Channel 19 Software Selection */
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| 84 | uint32_t CHANNEL20:1; /*!< bit: 20 Channel 20 Software Selection */
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| 85 | uint32_t CHANNEL21:1; /*!< bit: 21 Channel 21 Software Selection */
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| 86 | uint32_t CHANNEL22:1; /*!< bit: 22 Channel 22 Software Selection */
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| 87 | uint32_t CHANNEL23:1; /*!< bit: 23 Channel 23 Software Selection */
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| 88 | uint32_t CHANNEL24:1; /*!< bit: 24 Channel 24 Software Selection */
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| 89 | uint32_t CHANNEL25:1; /*!< bit: 25 Channel 25 Software Selection */
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| 90 | uint32_t CHANNEL26:1; /*!< bit: 26 Channel 26 Software Selection */
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| 91 | uint32_t CHANNEL27:1; /*!< bit: 27 Channel 27 Software Selection */
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| 92 | uint32_t CHANNEL28:1; /*!< bit: 28 Channel 28 Software Selection */
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| 93 | uint32_t CHANNEL29:1; /*!< bit: 29 Channel 29 Software Selection */
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| 94 | uint32_t CHANNEL30:1; /*!< bit: 30 Channel 30 Software Selection */
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| 95 | uint32_t CHANNEL31:1; /*!< bit: 31 Channel 31 Software Selection */
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| 96 | } bit; /*!< Structure used for bit access */
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| 97 | struct {
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| 98 | uint32_t CHANNEL:32; /*!< bit: 0..31 Channel x Software Selection */
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| 99 | } vec; /*!< Structure used for vec access */
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| 100 | uint32_t reg; /*!< Type used for register access */
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| 101 | } EVSYS_SWEVT_Type;
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| 102 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 103 |
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| 104 | #define EVSYS_SWEVT_OFFSET 0x004 /**< \brief (EVSYS_SWEVT offset) Software Event */
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| 105 | #define EVSYS_SWEVT_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
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| 106 |
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| 107 | #define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
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| 108 | #define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
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| 109 | #define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
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| 110 | #define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
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| 111 | #define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
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| 112 | #define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
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| 113 | #define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
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| 114 | #define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
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| 115 | #define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
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| 116 | #define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
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| 117 | #define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
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| 118 | #define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
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| 119 | #define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
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| 120 | #define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
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| 121 | #define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
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| 122 | #define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
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| 123 | #define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
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| 124 | #define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
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| 125 | #define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
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| 126 | #define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
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| 127 | #define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
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| 128 | #define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
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| 129 | #define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
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| 130 | #define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
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| 131 | #define EVSYS_SWEVT_CHANNEL12_Pos 12 /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
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| 132 | #define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
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| 133 | #define EVSYS_SWEVT_CHANNEL13_Pos 13 /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
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| 134 | #define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
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| 135 | #define EVSYS_SWEVT_CHANNEL14_Pos 14 /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
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| 136 | #define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
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| 137 | #define EVSYS_SWEVT_CHANNEL15_Pos 15 /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
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| 138 | #define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
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| 139 | #define EVSYS_SWEVT_CHANNEL16_Pos 16 /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
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| 140 | #define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
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| 141 | #define EVSYS_SWEVT_CHANNEL17_Pos 17 /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
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| 142 | #define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
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| 143 | #define EVSYS_SWEVT_CHANNEL18_Pos 18 /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
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| 144 | #define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
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| 145 | #define EVSYS_SWEVT_CHANNEL19_Pos 19 /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
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| 146 | #define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
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| 147 | #define EVSYS_SWEVT_CHANNEL20_Pos 20 /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
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| 148 | #define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
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| 149 | #define EVSYS_SWEVT_CHANNEL21_Pos 21 /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
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| 150 | #define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
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| 151 | #define EVSYS_SWEVT_CHANNEL22_Pos 22 /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
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| 152 | #define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
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| 153 | #define EVSYS_SWEVT_CHANNEL23_Pos 23 /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
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| 154 | #define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
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| 155 | #define EVSYS_SWEVT_CHANNEL24_Pos 24 /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
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| 156 | #define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
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| 157 | #define EVSYS_SWEVT_CHANNEL25_Pos 25 /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
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| 158 | #define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
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| 159 | #define EVSYS_SWEVT_CHANNEL26_Pos 26 /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
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| 160 | #define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
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| 161 | #define EVSYS_SWEVT_CHANNEL27_Pos 27 /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
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| 162 | #define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
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| 163 | #define EVSYS_SWEVT_CHANNEL28_Pos 28 /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
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| 164 | #define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
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| 165 | #define EVSYS_SWEVT_CHANNEL29_Pos 29 /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
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| 166 | #define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
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| 167 | #define EVSYS_SWEVT_CHANNEL30_Pos 30 /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
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| 168 | #define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
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| 169 | #define EVSYS_SWEVT_CHANNEL31_Pos 31 /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
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| 170 | #define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
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| 171 | #define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
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| 172 | #define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
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| 173 | #define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
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| 174 | #define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
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| 175 |
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| 176 | /* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W 8) Priority Control -------- */
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| 177 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 178 | typedef union {
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| 179 | struct {
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| 180 | uint8_t PRI:4; /*!< bit: 0.. 3 Channel Priority Number */
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| 181 | uint8_t :3; /*!< bit: 4.. 6 Reserved */
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| 182 | uint8_t RREN:1; /*!< bit: 7 Round-Robin Scheduling Enable */
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| 183 | } bit; /*!< Structure used for bit access */
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| 184 | uint8_t reg; /*!< Type used for register access */
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| 185 | } EVSYS_PRICTRL_Type;
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| 186 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 187 |
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| 188 | #define EVSYS_PRICTRL_OFFSET 0x008 /**< \brief (EVSYS_PRICTRL offset) Priority Control */
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| 189 | #define EVSYS_PRICTRL_RESETVALUE _U_(0x00) /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
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| 190 |
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| 191 | #define EVSYS_PRICTRL_PRI_Pos 0 /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
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| 192 | #define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
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| 193 | #define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
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| 194 | #define EVSYS_PRICTRL_RREN_Pos 7 /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
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| 195 | #define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
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| 196 | #define EVSYS_PRICTRL_MASK _U_(0x8F) /**< \brief (EVSYS_PRICTRL) MASK Register */
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| 197 |
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| 198 | /* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
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| 199 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 200 | typedef union {
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| 201 | struct {
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| 202 | uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
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| 203 | uint16_t :4; /*!< bit: 4.. 7 Reserved */
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| 204 | uint16_t OVR:1; /*!< bit: 8 Channel Overrun */
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| 205 | uint16_t EVD:1; /*!< bit: 9 Channel Event Detected */
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| 206 | uint16_t :4; /*!< bit: 10..13 Reserved */
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| 207 | uint16_t READY:1; /*!< bit: 14 Ready */
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| 208 | uint16_t BUSY:1; /*!< bit: 15 Busy */
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| 209 | } bit; /*!< Structure used for bit access */
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| 210 | uint16_t reg; /*!< Type used for register access */
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| 211 | } EVSYS_INTPEND_Type;
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| 212 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 213 |
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| 214 | #define EVSYS_INTPEND_OFFSET 0x010 /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
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| 215 | #define EVSYS_INTPEND_RESETVALUE _U_(0x4000) /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
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| 216 |
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| 217 | #define EVSYS_INTPEND_ID_Pos 0 /**< \brief (EVSYS_INTPEND) Channel ID */
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| 218 | #define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
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| 219 | #define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
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| 220 | #define EVSYS_INTPEND_OVR_Pos 8 /**< \brief (EVSYS_INTPEND) Channel Overrun */
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| 221 | #define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
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| 222 | #define EVSYS_INTPEND_EVD_Pos 9 /**< \brief (EVSYS_INTPEND) Channel Event Detected */
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| 223 | #define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
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| 224 | #define EVSYS_INTPEND_READY_Pos 14 /**< \brief (EVSYS_INTPEND) Ready */
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| 225 | #define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
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| 226 | #define EVSYS_INTPEND_BUSY_Pos 15 /**< \brief (EVSYS_INTPEND) Busy */
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| 227 | #define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
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| 228 | #define EVSYS_INTPEND_MASK _U_(0xC30F) /**< \brief (EVSYS_INTPEND) MASK Register */
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| 229 |
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| 230 | /* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/ 32) Interrupt Status -------- */
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| 231 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 232 | typedef union {
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| 233 | struct {
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| 234 | uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
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| 235 | uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
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| 236 | uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
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| 237 | uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
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| 238 | uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
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| 239 | uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
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| 240 | uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
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| 241 | uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
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| 242 | uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
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| 243 | uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
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| 244 | uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
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| 245 | uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
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| 246 | uint32_t :20; /*!< bit: 12..31 Reserved */
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| 247 | } bit; /*!< Structure used for bit access */
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| 248 | struct {
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| 249 | uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
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| 250 | uint32_t :20; /*!< bit: 12..31 Reserved */
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| 251 | } vec; /*!< Structure used for vec access */
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| 252 | uint32_t reg; /*!< Type used for register access */
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| 253 | } EVSYS_INTSTATUS_Type;
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| 254 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 255 |
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| 256 | #define EVSYS_INTSTATUS_OFFSET 0x014 /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
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| 257 | #define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
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| 258 |
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| 259 | #define EVSYS_INTSTATUS_CHINT0_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
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| 260 | #define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
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| 261 | #define EVSYS_INTSTATUS_CHINT1_Pos 1 /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
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| 262 | #define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
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| 263 | #define EVSYS_INTSTATUS_CHINT2_Pos 2 /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
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| 264 | #define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
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| 265 | #define EVSYS_INTSTATUS_CHINT3_Pos 3 /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
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| 266 | #define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
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| 267 | #define EVSYS_INTSTATUS_CHINT4_Pos 4 /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
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| 268 | #define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
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| 269 | #define EVSYS_INTSTATUS_CHINT5_Pos 5 /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
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| 270 | #define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
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| 271 | #define EVSYS_INTSTATUS_CHINT6_Pos 6 /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
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| 272 | #define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
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| 273 | #define EVSYS_INTSTATUS_CHINT7_Pos 7 /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
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| 274 | #define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
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| 275 | #define EVSYS_INTSTATUS_CHINT8_Pos 8 /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
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| 276 | #define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
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| 277 | #define EVSYS_INTSTATUS_CHINT9_Pos 9 /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
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| 278 | #define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
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| 279 | #define EVSYS_INTSTATUS_CHINT10_Pos 10 /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
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| 280 | #define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
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| 281 | #define EVSYS_INTSTATUS_CHINT11_Pos 11 /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
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| 282 | #define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
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| 283 | #define EVSYS_INTSTATUS_CHINT_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
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| 284 | #define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
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| 285 | #define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
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| 286 | #define EVSYS_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
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| 287 |
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| 288 | /* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/ 32) Busy Channels -------- */
|
| 289 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 290 | typedef union {
|
| 291 | struct {
|
| 292 | uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
|
| 293 | uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
|
| 294 | uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
|
| 295 | uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
|
| 296 | uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
|
| 297 | uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
|
| 298 | uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
|
| 299 | uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
|
| 300 | uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
|
| 301 | uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
|
| 302 | uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
|
| 303 | uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
|
| 304 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
| 305 | } bit; /*!< Structure used for bit access */
|
| 306 | struct {
|
| 307 | uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
|
| 308 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
| 309 | } vec; /*!< Structure used for vec access */
|
| 310 | uint32_t reg; /*!< Type used for register access */
|
| 311 | } EVSYS_BUSYCH_Type;
|
| 312 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 313 |
|
| 314 | #define EVSYS_BUSYCH_OFFSET 0x018 /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
|
| 315 | #define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
|
| 316 |
|
| 317 | #define EVSYS_BUSYCH_BUSYCH0_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
|
| 318 | #define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
|
| 319 | #define EVSYS_BUSYCH_BUSYCH1_Pos 1 /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
|
| 320 | #define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
|
| 321 | #define EVSYS_BUSYCH_BUSYCH2_Pos 2 /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
|
| 322 | #define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
|
| 323 | #define EVSYS_BUSYCH_BUSYCH3_Pos 3 /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
|
| 324 | #define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
|
| 325 | #define EVSYS_BUSYCH_BUSYCH4_Pos 4 /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
|
| 326 | #define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
|
| 327 | #define EVSYS_BUSYCH_BUSYCH5_Pos 5 /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
|
| 328 | #define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
|
| 329 | #define EVSYS_BUSYCH_BUSYCH6_Pos 6 /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
|
| 330 | #define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
|
| 331 | #define EVSYS_BUSYCH_BUSYCH7_Pos 7 /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
|
| 332 | #define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
|
| 333 | #define EVSYS_BUSYCH_BUSYCH8_Pos 8 /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
|
| 334 | #define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
|
| 335 | #define EVSYS_BUSYCH_BUSYCH9_Pos 9 /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
|
| 336 | #define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
|
| 337 | #define EVSYS_BUSYCH_BUSYCH10_Pos 10 /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
|
| 338 | #define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
|
| 339 | #define EVSYS_BUSYCH_BUSYCH11_Pos 11 /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
|
| 340 | #define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
|
| 341 | #define EVSYS_BUSYCH_BUSYCH_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel x */
|
| 342 | #define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
|
| 343 | #define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
|
| 344 | #define EVSYS_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
|
| 345 |
|
| 346 | /* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/ 32) Ready Users -------- */
|
| 347 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 348 | typedef union {
|
| 349 | struct {
|
| 350 | uint32_t READYUSR0:1; /*!< bit: 0 Ready User for Channel 0 */
|
| 351 | uint32_t READYUSR1:1; /*!< bit: 1 Ready User for Channel 1 */
|
| 352 | uint32_t READYUSR2:1; /*!< bit: 2 Ready User for Channel 2 */
|
| 353 | uint32_t READYUSR3:1; /*!< bit: 3 Ready User for Channel 3 */
|
| 354 | uint32_t READYUSR4:1; /*!< bit: 4 Ready User for Channel 4 */
|
| 355 | uint32_t READYUSR5:1; /*!< bit: 5 Ready User for Channel 5 */
|
| 356 | uint32_t READYUSR6:1; /*!< bit: 6 Ready User for Channel 6 */
|
| 357 | uint32_t READYUSR7:1; /*!< bit: 7 Ready User for Channel 7 */
|
| 358 | uint32_t READYUSR8:1; /*!< bit: 8 Ready User for Channel 8 */
|
| 359 | uint32_t READYUSR9:1; /*!< bit: 9 Ready User for Channel 9 */
|
| 360 | uint32_t READYUSR10:1; /*!< bit: 10 Ready User for Channel 10 */
|
| 361 | uint32_t READYUSR11:1; /*!< bit: 11 Ready User for Channel 11 */
|
| 362 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
| 363 | } bit; /*!< Structure used for bit access */
|
| 364 | struct {
|
| 365 | uint32_t READYUSR:12; /*!< bit: 0..11 Ready User for Channel x */
|
| 366 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
| 367 | } vec; /*!< Structure used for vec access */
|
| 368 | uint32_t reg; /*!< Type used for register access */
|
| 369 | } EVSYS_READYUSR_Type;
|
| 370 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 371 |
|
| 372 | #define EVSYS_READYUSR_OFFSET 0x01C /**< \brief (EVSYS_READYUSR offset) Ready Users */
|
| 373 | #define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
|
| 374 |
|
| 375 | #define EVSYS_READYUSR_READYUSR0_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
|
| 376 | #define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
|
| 377 | #define EVSYS_READYUSR_READYUSR1_Pos 1 /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
|
| 378 | #define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
|
| 379 | #define EVSYS_READYUSR_READYUSR2_Pos 2 /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
|
| 380 | #define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
|
| 381 | #define EVSYS_READYUSR_READYUSR3_Pos 3 /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
|
| 382 | #define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
|
| 383 | #define EVSYS_READYUSR_READYUSR4_Pos 4 /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
|
| 384 | #define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
|
| 385 | #define EVSYS_READYUSR_READYUSR5_Pos 5 /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
|
| 386 | #define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
|
| 387 | #define EVSYS_READYUSR_READYUSR6_Pos 6 /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
|
| 388 | #define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
|
| 389 | #define EVSYS_READYUSR_READYUSR7_Pos 7 /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
|
| 390 | #define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
|
| 391 | #define EVSYS_READYUSR_READYUSR8_Pos 8 /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
|
| 392 | #define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
|
| 393 | #define EVSYS_READYUSR_READYUSR9_Pos 9 /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
|
| 394 | #define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
|
| 395 | #define EVSYS_READYUSR_READYUSR10_Pos 10 /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
|
| 396 | #define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
|
| 397 | #define EVSYS_READYUSR_READYUSR11_Pos 11 /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
|
| 398 | #define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
|
| 399 | #define EVSYS_READYUSR_READYUSR_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
|
| 400 | #define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
|
| 401 | #define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
|
| 402 | #define EVSYS_READYUSR_MASK _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
|
| 403 |
|
| 404 | /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
|
| 405 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 406 | typedef union {
|
| 407 | struct {
|
| 408 | uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */
|
| 409 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 410 | uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */
|
| 411 | uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */
|
| 412 | uint32_t :2; /*!< bit: 12..13 Reserved */
|
| 413 | uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */
|
| 414 | uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */
|
| 415 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 416 | } bit; /*!< Structure used for bit access */
|
| 417 | uint32_t reg; /*!< Type used for register access */
|
| 418 | } EVSYS_CHANNEL_Type;
|
| 419 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 420 |
|
| 421 | #define EVSYS_CHANNEL_OFFSET 0x020 /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
|
| 422 | #define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
|
| 423 |
|
| 424 | #define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
|
| 425 | #define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
|
| 426 | #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
|
| 427 | #define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */
|
| 428 | #define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
|
| 429 | #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
|
| 430 | #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */
|
| 431 | #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */
|
| 432 | #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */
|
| 433 | #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
| 434 | #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
|
| 435 | #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
| 436 | #define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
|
| 437 | #define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
|
| 438 | #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
|
| 439 | #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
|
| 440 | #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
|
| 441 | #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
|
| 442 | #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
|
| 443 | #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
| 444 | #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
| 445 | #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
| 446 | #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
| 447 | #define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */
|
| 448 | #define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
|
| 449 | #define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
|
| 450 | #define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
|
| 451 | #define EVSYS_CHANNEL_MASK _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
|
| 452 |
|
| 453 | /* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
|
| 454 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 455 | typedef union {
|
| 456 | struct {
|
| 457 | uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Disable */
|
| 458 | uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Disable */
|
| 459 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 460 | } bit; /*!< Structure used for bit access */
|
| 461 | uint8_t reg; /*!< Type used for register access */
|
| 462 | } EVSYS_CHINTENCLR_Type;
|
| 463 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 464 |
|
| 465 | #define EVSYS_CHINTENCLR_OFFSET 0x024 /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
|
| 466 | #define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
|
| 467 |
|
| 468 | #define EVSYS_CHINTENCLR_OVR_Pos 0 /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
|
| 469 | #define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
|
| 470 | #define EVSYS_CHINTENCLR_EVD_Pos 1 /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
|
| 471 | #define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
|
| 472 | #define EVSYS_CHINTENCLR_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENCLR) MASK Register */
|
| 473 |
|
| 474 | /* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
|
| 475 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 476 | typedef union {
|
| 477 | struct {
|
| 478 | uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Enable */
|
| 479 | uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Enable */
|
| 480 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 481 | } bit; /*!< Structure used for bit access */
|
| 482 | uint8_t reg; /*!< Type used for register access */
|
| 483 | } EVSYS_CHINTENSET_Type;
|
| 484 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 485 |
|
| 486 | #define EVSYS_CHINTENSET_OFFSET 0x025 /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
|
| 487 | #define EVSYS_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
|
| 488 |
|
| 489 | #define EVSYS_CHINTENSET_OVR_Pos 0 /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
|
| 490 | #define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
|
| 491 | #define EVSYS_CHINTENSET_EVD_Pos 1 /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
|
| 492 | #define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
|
| 493 | #define EVSYS_CHINTENSET_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENSET) MASK Register */
|
| 494 |
|
| 495 | /* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
|
| 496 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 497 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 498 | struct {
|
| 499 | __I uint8_t OVR:1; /*!< bit: 0 Channel Overrun */
|
| 500 | __I uint8_t EVD:1; /*!< bit: 1 Channel Event Detected */
|
| 501 | __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 502 | } bit; /*!< Structure used for bit access */
|
| 503 | uint8_t reg; /*!< Type used for register access */
|
| 504 | } EVSYS_CHINTFLAG_Type;
|
| 505 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 506 |
|
| 507 | #define EVSYS_CHINTFLAG_OFFSET 0x026 /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
|
| 508 | #define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
|
| 509 |
|
| 510 | #define EVSYS_CHINTFLAG_OVR_Pos 0 /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
|
| 511 | #define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
|
| 512 | #define EVSYS_CHINTFLAG_EVD_Pos 1 /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
|
| 513 | #define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
|
| 514 | #define EVSYS_CHINTFLAG_MASK _U_(0x03) /**< \brief (EVSYS_CHINTFLAG) MASK Register */
|
| 515 |
|
| 516 | /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/ 8) CHANNEL Channel n Status -------- */
|
| 517 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 518 | typedef union {
|
| 519 | struct {
|
| 520 | uint8_t RDYUSR:1; /*!< bit: 0 Ready User */
|
| 521 | uint8_t BUSYCH:1; /*!< bit: 1 Busy Channel */
|
| 522 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 523 | } bit; /*!< Structure used for bit access */
|
| 524 | uint8_t reg; /*!< Type used for register access */
|
| 525 | } EVSYS_CHSTATUS_Type;
|
| 526 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 527 |
|
| 528 | #define EVSYS_CHSTATUS_OFFSET 0x027 /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
|
| 529 | #define EVSYS_CHSTATUS_RESETVALUE _U_(0x01) /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
|
| 530 |
|
| 531 | #define EVSYS_CHSTATUS_RDYUSR_Pos 0 /**< \brief (EVSYS_CHSTATUS) Ready User */
|
| 532 | #define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
|
| 533 | #define EVSYS_CHSTATUS_BUSYCH_Pos 1 /**< \brief (EVSYS_CHSTATUS) Busy Channel */
|
| 534 | #define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
|
| 535 | #define EVSYS_CHSTATUS_MASK _U_(0x03) /**< \brief (EVSYS_CHSTATUS) MASK Register */
|
| 536 |
|
| 537 | /* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
|
| 538 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 539 | typedef union {
|
| 540 | struct {
|
| 541 | uint32_t CHANNEL:6; /*!< bit: 0.. 5 Channel Event Selection */
|
| 542 | uint32_t :26; /*!< bit: 6..31 Reserved */
|
| 543 | } bit; /*!< Structure used for bit access */
|
| 544 | uint32_t reg; /*!< Type used for register access */
|
| 545 | } EVSYS_USER_Type;
|
| 546 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 547 |
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| 548 | #define EVSYS_USER_OFFSET 0x120 /**< \brief (EVSYS_USER offset) User Multiplexer n */
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| 549 | #define EVSYS_USER_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
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| 550 |
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| 551 | #define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */
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| 552 | #define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
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| 553 | #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
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| 554 | #define EVSYS_USER_MASK _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
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| 555 |
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| 556 | /** \brief EvsysChannel hardware registers */
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| 557 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 558 | typedef struct {
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| 559 | __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
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| 560 | __IO EVSYS_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear */
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| 561 | __IO EVSYS_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set */
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| 562 | __IO EVSYS_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear */
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| 563 | __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x007 (R/ 8) Channel n Status */
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| 564 | } EvsysChannel;
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| 565 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 566 |
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| 567 | /** \brief EVSYS hardware registers */
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| 568 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 569 | typedef struct {
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| 570 | __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control */
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| 571 | RoReg8 Reserved1[0x3];
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| 572 | __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x004 ( /W 32) Software Event */
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| 573 | __IO EVSYS_PRICTRL_Type PRICTRL; /**< \brief Offset: 0x008 (R/W 8) Priority Control */
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| 574 | RoReg8 Reserved2[0x7];
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| 575 | __IO EVSYS_INTPEND_Type INTPEND; /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
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| 576 | RoReg8 Reserved3[0x2];
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| 577 | __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */
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| 578 | __I EVSYS_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x018 (R/ 32) Busy Channels */
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| 579 | __I EVSYS_READYUSR_Type READYUSR; /**< \brief Offset: 0x01C (R/ 32) Ready Users */
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| 580 | EvsysChannel Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
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| 581 | __IO EVSYS_USER_Type USER[67]; /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
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| 582 | } Evsys;
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| 583 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 584 |
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| 585 | /*@}*/
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| 586 |
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| 587 | #endif /* _SAME54_EVSYS_COMPONENT_ */
|