| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for EIC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_EIC_COMPONENT_
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| 31 | #define _SAME54_EIC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR EIC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_EIC External Interrupt Controller */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define EIC_U2254
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| 40 | #define REV_EIC 0x300
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| 41 |
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| 42 | /* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 49 | uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */
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| 50 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 51 | } bit; /*!< Structure used for bit access */
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| 52 | uint8_t reg; /*!< Type used for register access */
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| 53 | } EIC_CTRLA_Type;
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| 54 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 55 |
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| 56 | #define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control A */
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| 57 | #define EIC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRLA reset_value) Control A */
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| 58 |
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| 59 | #define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */
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| 60 | #define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
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| 61 | #define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */
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| 62 | #define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
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| 63 | #define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */
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| 64 | #define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
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| 65 | #define EIC_CTRLA_MASK _U_(0x13) /**< \brief (EIC_CTRLA) MASK Register */
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| 66 |
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| 67 | /* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
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| 68 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 69 | typedef union {
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| 70 | struct {
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| 71 | uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense Configuration */
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| 72 | uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
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| 73 | uint8_t NMIASYNCH:1; /*!< bit: 4 Asynchronous Edge Detection Mode */
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| 74 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 75 | } bit; /*!< Structure used for bit access */
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| 76 | uint8_t reg; /*!< Type used for register access */
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| 77 | } EIC_NMICTRL_Type;
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| 78 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 79 |
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| 80 | #define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
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| 81 | #define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
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| 82 |
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| 83 | #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
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| 84 | #define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
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| 85 | #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
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| 86 | #define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */
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| 87 | #define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising-edge detection */
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| 88 | #define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling-edge detection */
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| 89 | #define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both-edges detection */
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| 90 | #define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High-level detection */
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| 91 | #define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low-level detection */
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| 92 | #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
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| 93 | #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
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| 94 | #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
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| 95 | #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
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| 96 | #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
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| 97 | #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
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| 98 | #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
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| 99 | #define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
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| 100 | #define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
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| 101 | #define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
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| 102 | #define EIC_NMICTRL_MASK _U_(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */
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| 103 |
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| 104 | /* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
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| 105 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 106 | typedef union {
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| 107 | struct {
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| 108 | uint16_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
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| 109 | uint16_t :15; /*!< bit: 1..15 Reserved */
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| 110 | } bit; /*!< Structure used for bit access */
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| 111 | uint16_t reg; /*!< Type used for register access */
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| 112 | } EIC_NMIFLAG_Type;
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| 113 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 114 |
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| 115 | #define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
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| 116 | #define EIC_NMIFLAG_RESETVALUE _U_(0x0000) /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
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| 117 |
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| 118 | #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
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| 119 | #define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
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| 120 | #define EIC_NMIFLAG_MASK _U_(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */
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| 121 |
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| 122 | /* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Synchronization Busy -------- */
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| 123 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 124 | typedef union {
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| 125 | struct {
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| 126 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy Status */
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| 127 | uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy Status */
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| 128 | uint32_t :30; /*!< bit: 2..31 Reserved */
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| 129 | } bit; /*!< Structure used for bit access */
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| 130 | uint32_t reg; /*!< Type used for register access */
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| 131 | } EIC_SYNCBUSY_Type;
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| 132 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 133 |
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| 134 | #define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
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| 135 | #define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
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| 136 |
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| 137 | #define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
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| 138 | #define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
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| 139 | #define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
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| 140 | #define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
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| 141 | #define EIC_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
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| 142 |
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| 143 | /* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
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| 144 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 145 | typedef union {
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| 146 | struct {
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| 147 | uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */
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| 148 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 149 | } bit; /*!< Structure used for bit access */
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| 150 | uint32_t reg; /*!< Type used for register access */
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| 151 | } EIC_EVCTRL_Type;
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| 152 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 153 |
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| 154 | #define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */
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| 155 | #define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
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| 156 |
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| 157 | #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
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| 158 | #define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
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| 159 | #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
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| 160 | #define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
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| 161 |
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| 162 | /* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
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| 163 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 164 | typedef union {
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| 165 | struct {
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| 166 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
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| 167 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 168 | } bit; /*!< Structure used for bit access */
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| 169 | uint32_t reg; /*!< Type used for register access */
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| 170 | } EIC_INTENCLR_Type;
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| 171 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 172 |
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| 173 | #define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
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| 174 | #define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
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| 175 |
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| 176 | #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Enable */
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| 177 | #define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
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| 178 | #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
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| 179 | #define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
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| 180 |
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| 181 | /* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
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| 182 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 183 | typedef union {
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| 184 | struct {
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| 185 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
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| 186 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 187 | } bit; /*!< Structure used for bit access */
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| 188 | uint32_t reg; /*!< Type used for register access */
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| 189 | } EIC_INTENSET_Type;
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| 190 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 191 |
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| 192 | #define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
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| 193 | #define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
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| 194 |
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| 195 | #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Enable */
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| 196 | #define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
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| 197 | #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
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| 198 | #define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
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| 199 |
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| 200 | /* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
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| 201 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 202 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 203 | struct {
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| 204 | __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt */
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| 205 | __I uint32_t :16; /*!< bit: 16..31 Reserved */
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| 206 | } bit; /*!< Structure used for bit access */
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| 207 | uint32_t reg; /*!< Type used for register access */
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| 208 | } EIC_INTFLAG_Type;
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| 209 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 210 |
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| 211 | #define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
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| 212 | #define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 213 |
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| 214 | #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt */
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| 215 | #define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
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| 216 | #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
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| 217 | #define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
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| 218 |
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| 219 | /* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
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| 220 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 221 | typedef union {
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| 222 | struct {
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| 223 | uint32_t ASYNCH:16; /*!< bit: 0..15 Asynchronous Edge Detection Mode */
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| 224 | uint32_t :16; /*!< bit: 16..31 Reserved */
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| 225 | } bit; /*!< Structure used for bit access */
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| 226 | uint32_t reg; /*!< Type used for register access */
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| 227 | } EIC_ASYNCH_Type;
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| 228 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 229 |
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| 230 | #define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
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| 231 | #define EIC_ASYNCH_RESETVALUE _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
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| 232 |
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| 233 | #define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
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| 234 | #define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
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| 235 | #define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
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| 236 | #define EIC_ASYNCH_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
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| 237 |
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| 238 | /* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
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| 239 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 240 | typedef union {
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| 241 | struct {
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| 242 | uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */
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| 243 | uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */
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| 244 | uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */
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| 245 | uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */
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| 246 | uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */
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| 247 | uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */
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| 248 | uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */
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| 249 | uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */
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| 250 | uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */
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| 251 | uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */
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| 252 | uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */
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| 253 | uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */
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| 254 | uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */
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| 255 | uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */
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| 256 | uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */
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| 257 | uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */
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| 258 | } bit; /*!< Structure used for bit access */
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| 259 | uint32_t reg; /*!< Type used for register access */
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| 260 | } EIC_CONFIG_Type;
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| 261 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 262 |
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| 263 | #define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
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| 264 | #define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
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| 265 |
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| 266 | #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
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| 267 | #define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
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| 268 | #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
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| 269 | #define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
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| 270 | #define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
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| 271 | #define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
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| 272 | #define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
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| 273 | #define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
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| 274 | #define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
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| 275 | #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
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| 276 | #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
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| 277 | #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
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| 278 | #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
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| 279 | #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
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| 280 | #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
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| 281 | #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */
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| 282 | #define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
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| 283 | #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
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| 284 | #define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
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| 285 | #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
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| 286 | #define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
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| 287 | #define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
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| 288 | #define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
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| 289 | #define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
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| 290 | #define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
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| 291 | #define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
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| 292 | #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
|
| 293 | #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
|
| 294 | #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
|
| 295 | #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
|
| 296 | #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
|
| 297 | #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
|
| 298 | #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */
|
| 299 | #define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
|
| 300 | #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
|
| 301 | #define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
|
| 302 | #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
|
| 303 | #define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
|
| 304 | #define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
|
| 305 | #define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
|
| 306 | #define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
|
| 307 | #define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
|
| 308 | #define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
|
| 309 | #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
|
| 310 | #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
|
| 311 | #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
|
| 312 | #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
|
| 313 | #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
|
| 314 | #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
|
| 315 | #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */
|
| 316 | #define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
|
| 317 | #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
|
| 318 | #define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
|
| 319 | #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
|
| 320 | #define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
|
| 321 | #define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
|
| 322 | #define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
|
| 323 | #define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
|
| 324 | #define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
|
| 325 | #define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
|
| 326 | #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
|
| 327 | #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
|
| 328 | #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
|
| 329 | #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
|
| 330 | #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
|
| 331 | #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
|
| 332 | #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */
|
| 333 | #define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
|
| 334 | #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
|
| 335 | #define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
|
| 336 | #define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
|
| 337 | #define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
|
| 338 | #define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
|
| 339 | #define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
|
| 340 | #define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
|
| 341 | #define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
|
| 342 | #define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
|
| 343 | #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
|
| 344 | #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
|
| 345 | #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
|
| 346 | #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
|
| 347 | #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
|
| 348 | #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
|
| 349 | #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */
|
| 350 | #define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
|
| 351 | #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
|
| 352 | #define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
|
| 353 | #define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
|
| 354 | #define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
|
| 355 | #define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
|
| 356 | #define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
|
| 357 | #define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
|
| 358 | #define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
|
| 359 | #define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
|
| 360 | #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
|
| 361 | #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
|
| 362 | #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
|
| 363 | #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
|
| 364 | #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
|
| 365 | #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
|
| 366 | #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */
|
| 367 | #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
|
| 368 | #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
|
| 369 | #define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
|
| 370 | #define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
|
| 371 | #define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
|
| 372 | #define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
|
| 373 | #define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
|
| 374 | #define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
|
| 375 | #define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
|
| 376 | #define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
|
| 377 | #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
|
| 378 | #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
|
| 379 | #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
|
| 380 | #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
|
| 381 | #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
|
| 382 | #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
|
| 383 | #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */
|
| 384 | #define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
|
| 385 | #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
|
| 386 | #define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
|
| 387 | #define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
|
| 388 | #define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
|
| 389 | #define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
|
| 390 | #define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
|
| 391 | #define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
|
| 392 | #define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
|
| 393 | #define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
|
| 394 | #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
|
| 395 | #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
|
| 396 | #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
|
| 397 | #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
|
| 398 | #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
|
| 399 | #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
|
| 400 | #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */
|
| 401 | #define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
|
| 402 | #define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
|
| 403 |
|
| 404 | /* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
|
| 405 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 406 | typedef union {
|
| 407 | struct {
|
| 408 | uint32_t DEBOUNCEN:16; /*!< bit: 0..15 Debouncer Enable */
|
| 409 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 410 | } bit; /*!< Structure used for bit access */
|
| 411 | uint32_t reg; /*!< Type used for register access */
|
| 412 | } EIC_DEBOUNCEN_Type;
|
| 413 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 414 |
|
| 415 | #define EIC_DEBOUNCEN_OFFSET 0x30 /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
|
| 416 | #define EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
|
| 417 |
|
| 418 | #define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0 /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
|
| 419 | #define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
|
| 420 | #define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
|
| 421 | #define EIC_DEBOUNCEN_MASK _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
|
| 422 |
|
| 423 | /* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
|
| 424 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 425 | typedef union {
|
| 426 | struct {
|
| 427 | uint32_t PRESCALER0:3; /*!< bit: 0.. 2 Debouncer Prescaler */
|
| 428 | uint32_t STATES0:1; /*!< bit: 3 Debouncer number of states */
|
| 429 | uint32_t PRESCALER1:3; /*!< bit: 4.. 6 Debouncer Prescaler */
|
| 430 | uint32_t STATES1:1; /*!< bit: 7 Debouncer number of states */
|
| 431 | uint32_t :8; /*!< bit: 8..15 Reserved */
|
| 432 | uint32_t TICKON:1; /*!< bit: 16 Pin Sampler frequency selection */
|
| 433 | uint32_t :15; /*!< bit: 17..31 Reserved */
|
| 434 | } bit; /*!< Structure used for bit access */
|
| 435 | uint32_t reg; /*!< Type used for register access */
|
| 436 | } EIC_DPRESCALER_Type;
|
| 437 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 438 |
|
| 439 | #define EIC_DPRESCALER_OFFSET 0x34 /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
|
| 440 | #define EIC_DPRESCALER_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
|
| 441 |
|
| 442 | #define EIC_DPRESCALER_PRESCALER0_Pos 0 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
|
| 443 | #define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
|
| 444 | #define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
|
| 445 | #define EIC_DPRESCALER_STATES0_Pos 3 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
|
| 446 | #define EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
|
| 447 | #define EIC_DPRESCALER_PRESCALER1_Pos 4 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
|
| 448 | #define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
|
| 449 | #define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
|
| 450 | #define EIC_DPRESCALER_STATES1_Pos 7 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
|
| 451 | #define EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
|
| 452 | #define EIC_DPRESCALER_TICKON_Pos 16 /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
|
| 453 | #define EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
|
| 454 | #define EIC_DPRESCALER_MASK _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
|
| 455 |
|
| 456 | /* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/ 32) Pin State -------- */
|
| 457 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 458 | typedef union {
|
| 459 | struct {
|
| 460 | uint32_t PINSTATE:16; /*!< bit: 0..15 Pin State */
|
| 461 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
| 462 | } bit; /*!< Structure used for bit access */
|
| 463 | uint32_t reg; /*!< Type used for register access */
|
| 464 | } EIC_PINSTATE_Type;
|
| 465 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 466 |
|
| 467 | #define EIC_PINSTATE_OFFSET 0x38 /**< \brief (EIC_PINSTATE offset) Pin State */
|
| 468 | #define EIC_PINSTATE_RESETVALUE _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
|
| 469 |
|
| 470 | #define EIC_PINSTATE_PINSTATE_Pos 0 /**< \brief (EIC_PINSTATE) Pin State */
|
| 471 | #define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
|
| 472 | #define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
|
| 473 | #define EIC_PINSTATE_MASK _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
|
| 474 |
|
| 475 | /** \brief EIC hardware registers */
|
| 476 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 477 | typedef struct {
|
| 478 | __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
| 479 | __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */
|
| 480 | __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
|
| 481 | __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
|
| 482 | __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
|
| 483 | __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
|
| 484 | __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
|
| 485 | __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
|
| 486 | __IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
|
| 487 | __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
|
| 488 | RoReg8 Reserved1[0xC];
|
| 489 | __IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
|
| 490 | __IO EIC_DPRESCALER_Type DPRESCALER; /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
|
| 491 | __I EIC_PINSTATE_Type PINSTATE; /**< \brief Offset: 0x38 (R/ 32) Pin State */
|
| 492 | } Eic;
|
| 493 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 494 |
|
| 495 | /*@}*/
|
| 496 |
|
| 497 | #endif /* _SAME54_EIC_COMPONENT_ */
|