| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for DMAC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_DMAC_COMPONENT_
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| 31 | #define _SAME54_DMAC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR DMAC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_DMAC Direct Memory Access Controller */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define DMAC_U2503
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| 40 | #define REV_DMAC 0x101
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| 41 |
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| 42 | /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
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| 48 | uint16_t :6; /*!< bit: 2.. 7 Reserved */
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| 49 | uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
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| 50 | uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
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| 51 | uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
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| 52 | uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
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| 53 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 54 | } bit; /*!< Structure used for bit access */
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| 55 | struct {
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| 56 | uint16_t :8; /*!< bit: 0.. 7 Reserved */
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| 57 | uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
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| 58 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 59 | } vec; /*!< Structure used for vec access */
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| 60 | uint16_t reg; /*!< Type used for register access */
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| 61 | } DMAC_CTRL_Type;
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| 62 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 63 |
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| 64 | #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
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| 65 | #define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */
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| 66 |
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| 67 | #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
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| 68 | #define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
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| 69 | #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
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| 70 | #define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
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| 71 | #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
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| 72 | #define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
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| 73 | #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
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| 74 | #define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
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| 75 | #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
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| 76 | #define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
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| 77 | #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
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| 78 | #define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
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| 79 | #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
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| 80 | #define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
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| 81 | #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
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| 82 | #define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */
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| 83 |
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| 84 | /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
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| 85 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 86 | typedef union {
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| 87 | struct {
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| 88 | uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
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| 89 | uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
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| 90 | uint16_t :4; /*!< bit: 4.. 7 Reserved */
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| 91 | uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
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| 92 | uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */
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| 93 | } bit; /*!< Structure used for bit access */
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| 94 | uint16_t reg; /*!< Type used for register access */
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| 95 | } DMAC_CRCCTRL_Type;
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| 96 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 97 |
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| 98 | #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
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| 99 | #define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
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| 100 |
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| 101 | #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
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| 102 | #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 103 | #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
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| 104 | #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
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| 105 | #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
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| 106 | #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
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| 107 | #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 108 | #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 109 | #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 110 | #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
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| 111 | #define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
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| 112 | #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
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| 113 | #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
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| 114 | #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
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| 115 | #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
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| 116 | #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
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| 117 | #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
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| 118 | #define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
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| 119 | #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
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| 120 | #define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */
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| 121 | #define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */
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| 122 | #define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
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| 123 | #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
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| 124 | #define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
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| 125 | #define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
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| 126 | #define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
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| 127 | #define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */
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| 128 | #define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
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| 129 | #define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
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| 130 | #define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
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| 131 | #define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
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| 132 | #define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
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| 133 | #define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */
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| 134 |
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| 135 | /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
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| 136 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 137 | typedef union {
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| 138 | struct {
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| 139 | uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
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| 140 | } bit; /*!< Structure used for bit access */
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| 141 | uint32_t reg; /*!< Type used for register access */
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| 142 | } DMAC_CRCDATAIN_Type;
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| 143 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 144 |
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| 145 | #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
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| 146 | #define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
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| 147 |
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| 148 | #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
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| 149 | #define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
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| 150 | #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
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| 151 | #define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
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| 152 |
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| 153 | /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
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| 154 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 155 | typedef union {
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| 156 | struct {
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| 157 | uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
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| 158 | } bit; /*!< Structure used for bit access */
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| 159 | uint32_t reg; /*!< Type used for register access */
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| 160 | } DMAC_CRCCHKSUM_Type;
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| 161 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 162 |
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| 163 | #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
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| 164 | #define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
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| 165 |
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| 166 | #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
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| 167 | #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
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| 168 | #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
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| 169 | #define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
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| 170 |
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| 171 | /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
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| 172 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 173 | typedef union {
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| 174 | struct {
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| 175 | uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
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| 176 | uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
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| 177 | uint8_t CRCERR:1; /*!< bit: 2 CRC Error */
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| 178 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 179 | } bit; /*!< Structure used for bit access */
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| 180 | uint8_t reg; /*!< Type used for register access */
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| 181 | } DMAC_CRCSTATUS_Type;
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| 182 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 183 |
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| 184 | #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
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| 185 | #define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
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| 186 |
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| 187 | #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
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| 188 | #define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
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| 189 | #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
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| 190 | #define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
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| 191 | #define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */
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| 192 | #define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
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| 193 | #define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */
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| 194 |
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| 195 | /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
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| 196 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 197 | typedef union {
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| 198 | struct {
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| 199 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
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| 200 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 201 | } bit; /*!< Structure used for bit access */
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| 202 | uint8_t reg; /*!< Type used for register access */
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| 203 | } DMAC_DBGCTRL_Type;
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| 204 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 205 |
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| 206 | #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
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| 207 | #define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
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| 208 |
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| 209 | #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
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| 210 | #define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
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| 211 | #define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */
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| 212 |
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| 213 | /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
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| 214 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 215 | typedef union {
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| 216 | struct {
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| 217 | uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
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| 218 | uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
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| 219 | uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
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| 220 | uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
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| 221 | uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
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| 222 | uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
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| 223 | uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
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| 224 | uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
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| 225 | uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
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| 226 | uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
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| 227 | uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
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| 228 | uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
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| 229 | uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */
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| 230 | uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */
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| 231 | uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */
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| 232 | uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */
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| 233 | uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */
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| 234 | uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */
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| 235 | uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */
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| 236 | uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */
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| 237 | uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */
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| 238 | uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */
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| 239 | uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */
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| 240 | uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */
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| 241 | uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */
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| 242 | uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */
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| 243 | uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */
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| 244 | uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */
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| 245 | uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */
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| 246 | uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */
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| 247 | uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */
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| 248 | uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */
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| 249 | } bit; /*!< Structure used for bit access */
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| 250 | struct {
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| 251 | uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */
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| 252 | } vec; /*!< Structure used for vec access */
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| 253 | uint32_t reg; /*!< Type used for register access */
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| 254 | } DMAC_SWTRIGCTRL_Type;
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| 255 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 256 |
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| 257 | #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
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| 258 | #define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
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| 259 |
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| 260 | #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
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| 261 | #define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
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| 262 | #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
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| 263 | #define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
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| 264 | #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
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| 265 | #define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
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| 266 | #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
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| 267 | #define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
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| 268 | #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
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| 269 | #define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
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| 270 | #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
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| 271 | #define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
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| 272 | #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
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| 273 | #define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
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| 274 | #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
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| 275 | #define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
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| 276 | #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
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| 277 | #define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
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| 278 | #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
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| 279 | #define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
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| 280 | #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
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| 281 | #define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
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| 282 | #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
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| 283 | #define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
|
| 284 | #define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
|
| 285 | #define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
|
| 286 | #define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
|
| 287 | #define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
|
| 288 | #define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
|
| 289 | #define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
|
| 290 | #define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
|
| 291 | #define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
|
| 292 | #define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
|
| 293 | #define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
|
| 294 | #define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
|
| 295 | #define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
|
| 296 | #define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
|
| 297 | #define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
|
| 298 | #define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
|
| 299 | #define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
|
| 300 | #define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
|
| 301 | #define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
|
| 302 | #define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
|
| 303 | #define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
|
| 304 | #define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
|
| 305 | #define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
|
| 306 | #define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
|
| 307 | #define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
|
| 308 | #define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
|
| 309 | #define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
|
| 310 | #define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
|
| 311 | #define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
|
| 312 | #define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
|
| 313 | #define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
|
| 314 | #define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
|
| 315 | #define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
|
| 316 | #define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
|
| 317 | #define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
|
| 318 | #define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
|
| 319 | #define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
|
| 320 | #define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
|
| 321 | #define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
|
| 322 | #define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
|
| 323 | #define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
|
| 324 | #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
|
| 325 | #define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
|
| 326 | #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
|
| 327 | #define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
|
| 328 |
|
| 329 | /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
|
| 330 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 331 | typedef union {
|
| 332 | struct {
|
| 333 | uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */
|
| 334 | uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */
|
| 335 | uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
|
| 336 | uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */
|
| 337 | uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */
|
| 338 | uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
|
| 339 | uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */
|
| 340 | uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */
|
| 341 | uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
|
| 342 | uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */
|
| 343 | uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */
|
| 344 | uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
|
| 345 | } bit; /*!< Structure used for bit access */
|
| 346 | uint32_t reg; /*!< Type used for register access */
|
| 347 | } DMAC_PRICTRL0_Type;
|
| 348 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 349 |
|
| 350 | #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
|
| 351 | #define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
|
| 352 |
|
| 353 | #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
|
| 354 | #define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
|
| 355 | #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
|
| 356 | #define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
|
| 357 | #define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
|
| 358 | #define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
|
| 359 | #define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
|
| 360 | #define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
|
| 361 | #define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
|
| 362 | #define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
|
| 363 | #define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
|
| 364 | #define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
|
| 365 | #define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
|
| 366 | #define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
|
| 367 | #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
|
| 368 | #define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
|
| 369 | #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
|
| 370 | #define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
|
| 371 | #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
|
| 372 | #define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
|
| 373 | #define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
|
| 374 | #define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
|
| 375 | #define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
|
| 376 | #define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
|
| 377 | #define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
|
| 378 | #define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
|
| 379 | #define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
|
| 380 | #define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
|
| 381 | #define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
|
| 382 | #define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
|
| 383 | #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
|
| 384 | #define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
|
| 385 | #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
|
| 386 | #define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
|
| 387 | #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
|
| 388 | #define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
|
| 389 | #define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
|
| 390 | #define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
|
| 391 | #define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
|
| 392 | #define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
|
| 393 | #define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
|
| 394 | #define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
|
| 395 | #define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
|
| 396 | #define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
|
| 397 | #define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
|
| 398 | #define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
|
| 399 | #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
|
| 400 | #define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
|
| 401 | #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
|
| 402 | #define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
|
| 403 | #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
|
| 404 | #define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
|
| 405 | #define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
|
| 406 | #define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
|
| 407 | #define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */
|
| 408 | #define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
|
| 409 | #define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */
|
| 410 | #define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */
|
| 411 | #define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
|
| 412 | #define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
|
| 413 | #define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
|
| 414 | #define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
|
| 415 | #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
|
| 416 | #define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
|
| 417 | #define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
|
| 418 |
|
| 419 | /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
|
| 420 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 421 | typedef union {
|
| 422 | struct {
|
| 423 | uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */
|
| 424 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
| 425 | uint16_t TERR:1; /*!< bit: 8 Transfer Error */
|
| 426 | uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
|
| 427 | uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
|
| 428 | uint16_t :1; /*!< bit: 11 Reserved */
|
| 429 | uint16_t CRCERR:1; /*!< bit: 12 CRC Error */
|
| 430 | uint16_t FERR:1; /*!< bit: 13 Fetch Error */
|
| 431 | uint16_t BUSY:1; /*!< bit: 14 Busy */
|
| 432 | uint16_t PEND:1; /*!< bit: 15 Pending */
|
| 433 | } bit; /*!< Structure used for bit access */
|
| 434 | uint16_t reg; /*!< Type used for register access */
|
| 435 | } DMAC_INTPEND_Type;
|
| 436 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 437 |
|
| 438 | #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
|
| 439 | #define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
|
| 440 |
|
| 441 | #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
|
| 442 | #define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
|
| 443 | #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
|
| 444 | #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
|
| 445 | #define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
|
| 446 | #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
|
| 447 | #define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
|
| 448 | #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
|
| 449 | #define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
|
| 450 | #define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */
|
| 451 | #define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
|
| 452 | #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
|
| 453 | #define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
|
| 454 | #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
|
| 455 | #define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
|
| 456 | #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
|
| 457 | #define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
|
| 458 | #define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */
|
| 459 |
|
| 460 | /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
|
| 461 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 462 | typedef union {
|
| 463 | struct {
|
| 464 | uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
|
| 465 | uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
|
| 466 | uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
|
| 467 | uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
|
| 468 | uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
|
| 469 | uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
|
| 470 | uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
|
| 471 | uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
|
| 472 | uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
|
| 473 | uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
|
| 474 | uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
|
| 475 | uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
|
| 476 | uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */
|
| 477 | uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */
|
| 478 | uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */
|
| 479 | uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */
|
| 480 | uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */
|
| 481 | uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */
|
| 482 | uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */
|
| 483 | uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */
|
| 484 | uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */
|
| 485 | uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */
|
| 486 | uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */
|
| 487 | uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */
|
| 488 | uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */
|
| 489 | uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */
|
| 490 | uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */
|
| 491 | uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */
|
| 492 | uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */
|
| 493 | uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */
|
| 494 | uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */
|
| 495 | uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */
|
| 496 | } bit; /*!< Structure used for bit access */
|
| 497 | struct {
|
| 498 | uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */
|
| 499 | } vec; /*!< Structure used for vec access */
|
| 500 | uint32_t reg; /*!< Type used for register access */
|
| 501 | } DMAC_INTSTATUS_Type;
|
| 502 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 503 |
|
| 504 | #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
|
| 505 | #define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
|
| 506 |
|
| 507 | #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
|
| 508 | #define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
|
| 509 | #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
|
| 510 | #define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
|
| 511 | #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
|
| 512 | #define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
|
| 513 | #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
|
| 514 | #define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
|
| 515 | #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
|
| 516 | #define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
|
| 517 | #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
|
| 518 | #define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
|
| 519 | #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
|
| 520 | #define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
|
| 521 | #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
|
| 522 | #define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
|
| 523 | #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
|
| 524 | #define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
|
| 525 | #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
|
| 526 | #define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
|
| 527 | #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
|
| 528 | #define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
|
| 529 | #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
|
| 530 | #define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
|
| 531 | #define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
|
| 532 | #define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
|
| 533 | #define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
|
| 534 | #define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
|
| 535 | #define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
|
| 536 | #define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
|
| 537 | #define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
|
| 538 | #define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
|
| 539 | #define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
|
| 540 | #define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
|
| 541 | #define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
|
| 542 | #define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
|
| 543 | #define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
|
| 544 | #define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
|
| 545 | #define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
|
| 546 | #define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
|
| 547 | #define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
|
| 548 | #define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
|
| 549 | #define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
|
| 550 | #define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
|
| 551 | #define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
|
| 552 | #define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
|
| 553 | #define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
|
| 554 | #define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
|
| 555 | #define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
|
| 556 | #define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
|
| 557 | #define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
|
| 558 | #define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
|
| 559 | #define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
|
| 560 | #define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
|
| 561 | #define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
|
| 562 | #define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
|
| 563 | #define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
|
| 564 | #define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
|
| 565 | #define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
|
| 566 | #define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
|
| 567 | #define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
|
| 568 | #define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
|
| 569 | #define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
|
| 570 | #define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
|
| 571 | #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
|
| 572 | #define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
|
| 573 | #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
|
| 574 | #define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
|
| 575 |
|
| 576 | /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
|
| 577 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 578 | typedef union {
|
| 579 | struct {
|
| 580 | uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
|
| 581 | uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
|
| 582 | uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
|
| 583 | uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
|
| 584 | uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
|
| 585 | uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
|
| 586 | uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
|
| 587 | uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
|
| 588 | uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
|
| 589 | uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
|
| 590 | uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
|
| 591 | uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
|
| 592 | uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */
|
| 593 | uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */
|
| 594 | uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */
|
| 595 | uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */
|
| 596 | uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */
|
| 597 | uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */
|
| 598 | uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */
|
| 599 | uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */
|
| 600 | uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */
|
| 601 | uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */
|
| 602 | uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */
|
| 603 | uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */
|
| 604 | uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */
|
| 605 | uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */
|
| 606 | uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */
|
| 607 | uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */
|
| 608 | uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */
|
| 609 | uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */
|
| 610 | uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */
|
| 611 | uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */
|
| 612 | } bit; /*!< Structure used for bit access */
|
| 613 | struct {
|
| 614 | uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */
|
| 615 | } vec; /*!< Structure used for vec access */
|
| 616 | uint32_t reg; /*!< Type used for register access */
|
| 617 | } DMAC_BUSYCH_Type;
|
| 618 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 619 |
|
| 620 | #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
|
| 621 | #define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
|
| 622 |
|
| 623 | #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
|
| 624 | #define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
|
| 625 | #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
|
| 626 | #define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
|
| 627 | #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
|
| 628 | #define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
|
| 629 | #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
|
| 630 | #define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
|
| 631 | #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
|
| 632 | #define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
|
| 633 | #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
|
| 634 | #define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
|
| 635 | #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
|
| 636 | #define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
|
| 637 | #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
|
| 638 | #define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
|
| 639 | #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
|
| 640 | #define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
|
| 641 | #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
|
| 642 | #define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
|
| 643 | #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
|
| 644 | #define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
|
| 645 | #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
|
| 646 | #define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
|
| 647 | #define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
|
| 648 | #define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
|
| 649 | #define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
|
| 650 | #define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
|
| 651 | #define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
|
| 652 | #define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
|
| 653 | #define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
|
| 654 | #define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
|
| 655 | #define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
|
| 656 | #define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
|
| 657 | #define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
|
| 658 | #define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
|
| 659 | #define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
|
| 660 | #define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
|
| 661 | #define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
|
| 662 | #define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
|
| 663 | #define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
|
| 664 | #define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
|
| 665 | #define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
|
| 666 | #define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
|
| 667 | #define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
|
| 668 | #define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
|
| 669 | #define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
|
| 670 | #define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
|
| 671 | #define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
|
| 672 | #define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
|
| 673 | #define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
|
| 674 | #define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
|
| 675 | #define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
|
| 676 | #define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
|
| 677 | #define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
|
| 678 | #define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
|
| 679 | #define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
|
| 680 | #define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
|
| 681 | #define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
|
| 682 | #define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
|
| 683 | #define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
|
| 684 | #define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
|
| 685 | #define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
|
| 686 | #define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
|
| 687 | #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
|
| 688 | #define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
|
| 689 | #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
|
| 690 | #define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
|
| 691 |
|
| 692 | /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
|
| 693 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 694 | typedef union {
|
| 695 | struct {
|
| 696 | uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
|
| 697 | uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
|
| 698 | uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
|
| 699 | uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
|
| 700 | uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
|
| 701 | uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
|
| 702 | uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
|
| 703 | uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
|
| 704 | uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
|
| 705 | uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
|
| 706 | uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
|
| 707 | uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
|
| 708 | uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */
|
| 709 | uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */
|
| 710 | uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */
|
| 711 | uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */
|
| 712 | uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */
|
| 713 | uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */
|
| 714 | uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */
|
| 715 | uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */
|
| 716 | uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */
|
| 717 | uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */
|
| 718 | uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */
|
| 719 | uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */
|
| 720 | uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */
|
| 721 | uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */
|
| 722 | uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */
|
| 723 | uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */
|
| 724 | uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */
|
| 725 | uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */
|
| 726 | uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */
|
| 727 | uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */
|
| 728 | } bit; /*!< Structure used for bit access */
|
| 729 | struct {
|
| 730 | uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */
|
| 731 | } vec; /*!< Structure used for vec access */
|
| 732 | uint32_t reg; /*!< Type used for register access */
|
| 733 | } DMAC_PENDCH_Type;
|
| 734 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 735 |
|
| 736 | #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
|
| 737 | #define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
|
| 738 |
|
| 739 | #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
|
| 740 | #define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
|
| 741 | #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
|
| 742 | #define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
|
| 743 | #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
|
| 744 | #define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
|
| 745 | #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
|
| 746 | #define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
|
| 747 | #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
|
| 748 | #define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
|
| 749 | #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
|
| 750 | #define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
|
| 751 | #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
|
| 752 | #define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
|
| 753 | #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
|
| 754 | #define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
|
| 755 | #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
|
| 756 | #define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
|
| 757 | #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
|
| 758 | #define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
|
| 759 | #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
|
| 760 | #define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
|
| 761 | #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
|
| 762 | #define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
|
| 763 | #define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */
|
| 764 | #define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
|
| 765 | #define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */
|
| 766 | #define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
|
| 767 | #define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */
|
| 768 | #define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
|
| 769 | #define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */
|
| 770 | #define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
|
| 771 | #define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */
|
| 772 | #define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
|
| 773 | #define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */
|
| 774 | #define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
|
| 775 | #define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */
|
| 776 | #define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
|
| 777 | #define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */
|
| 778 | #define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
|
| 779 | #define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */
|
| 780 | #define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
|
| 781 | #define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */
|
| 782 | #define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
|
| 783 | #define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */
|
| 784 | #define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
|
| 785 | #define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */
|
| 786 | #define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
|
| 787 | #define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */
|
| 788 | #define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
|
| 789 | #define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */
|
| 790 | #define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
|
| 791 | #define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */
|
| 792 | #define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
|
| 793 | #define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */
|
| 794 | #define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
|
| 795 | #define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */
|
| 796 | #define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
|
| 797 | #define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */
|
| 798 | #define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
|
| 799 | #define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */
|
| 800 | #define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
|
| 801 | #define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */
|
| 802 | #define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
|
| 803 | #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
|
| 804 | #define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
|
| 805 | #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
|
| 806 | #define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
|
| 807 |
|
| 808 | /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
|
| 809 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 810 | typedef union {
|
| 811 | struct {
|
| 812 | uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
|
| 813 | uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
|
| 814 | uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
|
| 815 | uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
|
| 816 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
| 817 | uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
|
| 818 | uint32_t :2; /*!< bit: 13..14 Reserved */
|
| 819 | uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
|
| 820 | uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
|
| 821 | } bit; /*!< Structure used for bit access */
|
| 822 | struct {
|
| 823 | uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
|
| 824 | uint32_t :28; /*!< bit: 4..31 Reserved */
|
| 825 | } vec; /*!< Structure used for vec access */
|
| 826 | uint32_t reg; /*!< Type used for register access */
|
| 827 | } DMAC_ACTIVE_Type;
|
| 828 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 829 |
|
| 830 | #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
|
| 831 | #define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
|
| 832 |
|
| 833 | #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
|
| 834 | #define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
|
| 835 | #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
|
| 836 | #define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
|
| 837 | #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
|
| 838 | #define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
|
| 839 | #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
|
| 840 | #define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
|
| 841 | #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
|
| 842 | #define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
|
| 843 | #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
|
| 844 | #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
|
| 845 | #define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
|
| 846 | #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
|
| 847 | #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
|
| 848 | #define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
|
| 849 | #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
|
| 850 | #define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
|
| 851 | #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
|
| 852 | #define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
|
| 853 |
|
| 854 | /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
|
| 855 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 856 | typedef union {
|
| 857 | struct {
|
| 858 | uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
|
| 859 | } bit; /*!< Structure used for bit access */
|
| 860 | uint32_t reg; /*!< Type used for register access */
|
| 861 | } DMAC_BASEADDR_Type;
|
| 862 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 863 |
|
| 864 | #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
|
| 865 | #define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
|
| 866 |
|
| 867 | #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
|
| 868 | #define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
|
| 869 | #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
|
| 870 | #define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
|
| 871 |
|
| 872 | /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
|
| 873 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 874 | typedef union {
|
| 875 | struct {
|
| 876 | uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
|
| 877 | } bit; /*!< Structure used for bit access */
|
| 878 | uint32_t reg; /*!< Type used for register access */
|
| 879 | } DMAC_WRBADDR_Type;
|
| 880 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 881 |
|
| 882 | #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
|
| 883 | #define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
|
| 884 |
|
| 885 | #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
|
| 886 | #define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
|
| 887 | #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
|
| 888 | #define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
|
| 889 |
|
| 890 | /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
|
| 891 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 892 | typedef union {
|
| 893 | struct {
|
| 894 | uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */
|
| 895 | uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */
|
| 896 | uint32_t :4; /*!< bit: 2.. 5 Reserved */
|
| 897 | uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */
|
| 898 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 899 | uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */
|
| 900 | uint32_t :5; /*!< bit: 15..19 Reserved */
|
| 901 | uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */
|
| 902 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 903 | uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */
|
| 904 | uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */
|
| 905 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 906 | } bit; /*!< Structure used for bit access */
|
| 907 | uint32_t reg; /*!< Type used for register access */
|
| 908 | } DMAC_CHCTRLA_Type;
|
| 909 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 910 |
|
| 911 | #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
|
| 912 | #define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
|
| 913 |
|
| 914 | #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
|
| 915 | #define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
|
| 916 | #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
|
| 917 | #define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
|
| 918 | #define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
|
| 919 | #define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
|
| 920 | #define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */
|
| 921 | #define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
|
| 922 | #define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
|
| 923 | #define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
|
| 924 | #define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
|
| 925 | #define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */
|
| 926 | #define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
|
| 927 | #define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
|
| 928 | #define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
|
| 929 | #define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
|
| 930 | #define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
|
| 931 | #define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
|
| 932 | #define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
|
| 933 | #define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
|
| 934 | #define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */
|
| 935 | #define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 936 | #define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
|
| 937 | #define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
|
| 938 | #define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
|
| 939 | #define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
|
| 940 | #define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
|
| 941 | #define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
|
| 942 | #define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
|
| 943 | #define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
|
| 944 | #define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
|
| 945 | #define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
|
| 946 | #define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
|
| 947 | #define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
|
| 948 | #define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
|
| 949 | #define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
|
| 950 | #define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
|
| 951 | #define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
|
| 952 | #define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
|
| 953 | #define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 954 | #define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 955 | #define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 956 | #define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 957 | #define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 958 | #define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 959 | #define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 960 | #define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 961 | #define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 962 | #define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 963 | #define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 964 | #define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 965 | #define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 966 | #define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 967 | #define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 968 | #define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
|
| 969 | #define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
|
| 970 | #define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
|
| 971 | #define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
|
| 972 | #define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
|
| 973 | #define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
|
| 974 | #define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
|
| 975 | #define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
|
| 976 | #define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
|
| 977 | #define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
|
| 978 | #define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
|
| 979 | #define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
|
| 980 | #define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
|
| 981 |
|
| 982 | /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */
|
| 983 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 984 | typedef union {
|
| 985 | struct {
|
| 986 | uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */
|
| 987 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 988 | } bit; /*!< Structure used for bit access */
|
| 989 | uint8_t reg; /*!< Type used for register access */
|
| 990 | } DMAC_CHCTRLB_Type;
|
| 991 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 992 |
|
| 993 | #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
|
| 994 | #define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
|
| 995 |
|
| 996 | #define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */
|
| 997 | #define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
|
| 998 | #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
|
| 999 | #define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */
|
| 1000 | #define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
|
| 1001 | #define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
|
| 1002 | #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
|
| 1003 | #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
|
| 1004 | #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
|
| 1005 | #define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */
|
| 1006 |
|
| 1007 | /* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */
|
| 1008 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1009 | typedef union {
|
| 1010 | struct {
|
| 1011 | uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */
|
| 1012 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 1013 | } bit; /*!< Structure used for bit access */
|
| 1014 | uint8_t reg; /*!< Type used for register access */
|
| 1015 | } DMAC_CHPRILVL_Type;
|
| 1016 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1017 |
|
| 1018 | #define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
|
| 1019 | #define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
|
| 1020 |
|
| 1021 | #define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
|
| 1022 | #define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1023 | #define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
|
| 1024 | #define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
|
| 1025 | #define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
|
| 1026 | #define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
|
| 1027 | #define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
|
| 1028 | #define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
|
| 1029 | #define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
|
| 1030 | #define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
|
| 1031 | #define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
|
| 1032 | #define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1033 | #define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1034 | #define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1035 | #define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1036 | #define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1037 | #define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1038 | #define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1039 | #define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
|
| 1040 | #define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */
|
| 1041 |
|
| 1042 | /* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */
|
| 1043 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1044 | typedef union {
|
| 1045 | struct {
|
| 1046 | uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */
|
| 1047 | uint8_t :1; /*!< bit: 3 Reserved */
|
| 1048 | uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */
|
| 1049 | uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */
|
| 1050 | uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */
|
| 1051 | } bit; /*!< Structure used for bit access */
|
| 1052 | uint8_t reg; /*!< Type used for register access */
|
| 1053 | } DMAC_CHEVCTRL_Type;
|
| 1054 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1055 |
|
| 1056 | #define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
|
| 1057 | #define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
|
| 1058 |
|
| 1059 | #define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
|
| 1060 | #define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1061 | #define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
|
| 1062 | #define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */
|
| 1063 | #define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
|
| 1064 | #define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
|
| 1065 | #define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
|
| 1066 | #define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
|
| 1067 | #define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
|
| 1068 | #define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
|
| 1069 | #define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */
|
| 1070 | #define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1071 | #define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1072 | #define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1073 | #define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1074 | #define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1075 | #define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1076 | #define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1077 | #define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
|
| 1078 | #define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
|
| 1079 | #define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
|
| 1080 | #define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
|
| 1081 | #define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
|
| 1082 | #define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
|
| 1083 | #define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
|
| 1084 | #define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
|
| 1085 | #define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
|
| 1086 | #define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
|
| 1087 | #define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
|
| 1088 | #define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
|
| 1089 | #define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */
|
| 1090 |
|
| 1091 | /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
|
| 1092 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1093 | typedef union {
|
| 1094 | struct {
|
| 1095 | uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
|
| 1096 | uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
|
| 1097 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
|
| 1098 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
| 1099 | } bit; /*!< Structure used for bit access */
|
| 1100 | uint8_t reg; /*!< Type used for register access */
|
| 1101 | } DMAC_CHINTENCLR_Type;
|
| 1102 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1103 |
|
| 1104 | #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
|
| 1105 | #define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
|
| 1106 |
|
| 1107 | #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
|
| 1108 | #define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
|
| 1109 | #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
|
| 1110 | #define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
|
| 1111 | #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
|
| 1112 | #define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
|
| 1113 | #define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */
|
| 1114 |
|
| 1115 | /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
|
| 1116 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1117 | typedef union {
|
| 1118 | struct {
|
| 1119 | uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
|
| 1120 | uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
|
| 1121 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
|
| 1122 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
| 1123 | } bit; /*!< Structure used for bit access */
|
| 1124 | uint8_t reg; /*!< Type used for register access */
|
| 1125 | } DMAC_CHINTENSET_Type;
|
| 1126 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1127 |
|
| 1128 | #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
|
| 1129 | #define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
|
| 1130 |
|
| 1131 | #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
|
| 1132 | #define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
|
| 1133 | #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
|
| 1134 | #define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
|
| 1135 | #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
|
| 1136 | #define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
|
| 1137 | #define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */
|
| 1138 |
|
| 1139 | /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
|
| 1140 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1141 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 1142 | struct {
|
| 1143 | __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
|
| 1144 | __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
|
| 1145 | __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
|
| 1146 | __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
| 1147 | } bit; /*!< Structure used for bit access */
|
| 1148 | uint8_t reg; /*!< Type used for register access */
|
| 1149 | } DMAC_CHINTFLAG_Type;
|
| 1150 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1151 |
|
| 1152 | #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
|
| 1153 | #define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
|
| 1154 |
|
| 1155 | #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
|
| 1156 | #define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
|
| 1157 | #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
|
| 1158 | #define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
|
| 1159 | #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
|
| 1160 | #define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
|
| 1161 | #define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */
|
| 1162 |
|
| 1163 | /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */
|
| 1164 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1165 | typedef union {
|
| 1166 | struct {
|
| 1167 | uint8_t PEND:1; /*!< bit: 0 Channel Pending */
|
| 1168 | uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
|
| 1169 | uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
|
| 1170 | uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */
|
| 1171 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
| 1172 | } bit; /*!< Structure used for bit access */
|
| 1173 | uint8_t reg; /*!< Type used for register access */
|
| 1174 | } DMAC_CHSTATUS_Type;
|
| 1175 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1176 |
|
| 1177 | #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
|
| 1178 | #define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
|
| 1179 |
|
| 1180 | #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
|
| 1181 | #define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
|
| 1182 | #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
|
| 1183 | #define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
|
| 1184 | #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
|
| 1185 | #define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
|
| 1186 | #define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
|
| 1187 | #define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
|
| 1188 | #define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */
|
| 1189 |
|
| 1190 | /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
|
| 1191 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1192 | typedef union {
|
| 1193 | struct {
|
| 1194 | uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
|
| 1195 | uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */
|
| 1196 | uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
|
| 1197 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
| 1198 | uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
|
| 1199 | uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
|
| 1200 | uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
|
| 1201 | uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
|
| 1202 | uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
|
| 1203 | } bit; /*!< Structure used for bit access */
|
| 1204 | uint16_t reg; /*!< Type used for register access */
|
| 1205 | } DMAC_BTCTRL_Type;
|
| 1206 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1207 |
|
| 1208 | #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
|
| 1209 | #define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
|
| 1210 |
|
| 1211 | #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
|
| 1212 | #define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
|
| 1213 | #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
|
| 1214 | #define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
|
| 1215 | #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
|
| 1216 | #define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */
|
| 1217 | #define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */
|
| 1218 | #define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */
|
| 1219 | #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
| 1220 | #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
| 1221 | #define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
| 1222 | #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
|
| 1223 | #define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
|
| 1224 | #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
|
| 1225 | #define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
|
| 1226 | #define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
|
| 1227 | #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
|
| 1228 | #define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
|
| 1229 | #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
| 1230 | #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
| 1231 | #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
| 1232 | #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
| 1233 | #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
|
| 1234 | #define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
|
| 1235 | #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
|
| 1236 | #define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
|
| 1237 | #define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
|
| 1238 | #define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
|
| 1239 | #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
|
| 1240 | #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
|
| 1241 | #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
|
| 1242 | #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
|
| 1243 | #define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
|
| 1244 | #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
|
| 1245 | #define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
|
| 1246 | #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
|
| 1247 | #define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
|
| 1248 | #define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
|
| 1249 | #define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
|
| 1250 | #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
|
| 1251 | #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
|
| 1252 | #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
|
| 1253 | #define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1254 | #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
|
| 1255 | #define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
|
| 1256 | #define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
|
| 1257 | #define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
|
| 1258 | #define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
|
| 1259 | #define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
|
| 1260 | #define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
|
| 1261 | #define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
|
| 1262 | #define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
|
| 1263 | #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1264 | #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1265 | #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1266 | #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1267 | #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1268 | #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1269 | #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1270 | #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
| 1271 | #define DMAC_BTCTRL_MASK _U_(0xFF1F) /**< \brief (DMAC_BTCTRL) MASK Register */
|
| 1272 |
|
| 1273 | /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
|
| 1274 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1275 | typedef union {
|
| 1276 | struct {
|
| 1277 | uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
|
| 1278 | } bit; /*!< Structure used for bit access */
|
| 1279 | uint16_t reg; /*!< Type used for register access */
|
| 1280 | } DMAC_BTCNT_Type;
|
| 1281 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1282 |
|
| 1283 | #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
|
| 1284 | #define DMAC_BTCNT_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCNT reset_value) Block Transfer Count */
|
| 1285 |
|
| 1286 | #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
|
| 1287 | #define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
|
| 1288 | #define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
|
| 1289 | #define DMAC_BTCNT_MASK _U_(0xFFFF) /**< \brief (DMAC_BTCNT) MASK Register */
|
| 1290 |
|
| 1291 | /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
|
| 1292 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1293 | typedef union {
|
| 1294 | struct {
|
| 1295 | uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
|
| 1296 | } bit; /*!< Structure used for bit access */
|
| 1297 | uint32_t reg; /*!< Type used for register access */
|
| 1298 | } DMAC_SRCADDR_Type;
|
| 1299 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1300 |
|
| 1301 | #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
|
| 1302 | #define DMAC_SRCADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SRCADDR reset_value) Block Transfer Source Address */
|
| 1303 |
|
| 1304 | #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
|
| 1305 | #define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
|
| 1306 | #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
|
| 1307 | #define DMAC_SRCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
|
| 1308 |
|
| 1309 | /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
|
| 1310 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1311 | typedef union {
|
| 1312 | struct { // CRC mode
|
| 1313 | uint32_t CHKINIT:32; /*!< bit: 0..31 CRC Checksum Initial Value */
|
| 1314 | } CRC; /*!< Structure used for CRC */
|
| 1315 | struct {
|
| 1316 | uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
|
| 1317 | } bit; /*!< Structure used for bit access */
|
| 1318 | uint32_t reg; /*!< Type used for register access */
|
| 1319 | } DMAC_DSTADDR_Type;
|
| 1320 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1321 |
|
| 1322 | #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
|
| 1323 |
|
| 1324 | // CRC mode
|
| 1325 | #define DMAC_DSTADDR_CRC_CHKINIT_Pos 0 /**< \brief (DMAC_DSTADDR_CRC) CRC Checksum Initial Value */
|
| 1326 | #define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
|
| 1327 | #define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
|
| 1328 | #define DMAC_DSTADDR_CRC_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR_CRC) MASK Register */
|
| 1329 |
|
| 1330 | #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
|
| 1331 | #define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
|
| 1332 | #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
|
| 1333 | #define DMAC_DSTADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
|
| 1334 |
|
| 1335 | /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
|
| 1336 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1337 | typedef union {
|
| 1338 | struct {
|
| 1339 | uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
|
| 1340 | } bit; /*!< Structure used for bit access */
|
| 1341 | uint32_t reg; /*!< Type used for register access */
|
| 1342 | } DMAC_DESCADDR_Type;
|
| 1343 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1344 |
|
| 1345 | #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
|
| 1346 |
|
| 1347 | #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
|
| 1348 | #define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
|
| 1349 | #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
|
| 1350 | #define DMAC_DESCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
|
| 1351 |
|
| 1352 | /** \brief DmacChannel hardware registers */
|
| 1353 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1354 | typedef struct {
|
| 1355 | __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */
|
| 1356 | __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B */
|
| 1357 | __IO DMAC_CHPRILVL_Type CHPRILVL; /**< \brief Offset: 0x05 (R/W 8) Channel n Priority Level */
|
| 1358 | __IO DMAC_CHEVCTRL_Type CHEVCTRL; /**< \brief Offset: 0x06 (R/W 8) Channel n Event Control */
|
| 1359 | RoReg8 Reserved1[0x5];
|
| 1360 | __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear */
|
| 1361 | __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set */
|
| 1362 | __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear */
|
| 1363 | __IO DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0F (R/W 8) Channel n Status */
|
| 1364 | } DmacChannel;
|
| 1365 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1366 |
|
| 1367 | /** \brief DMAC APB hardware registers */
|
| 1368 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1369 | typedef struct {
|
| 1370 | __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
|
| 1371 | __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
|
| 1372 | __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
|
| 1373 | __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
|
| 1374 | __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
|
| 1375 | __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
|
| 1376 | RoReg8 Reserved1[0x2];
|
| 1377 | __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
|
| 1378 | __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
|
| 1379 | RoReg8 Reserved2[0x8];
|
| 1380 | __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
|
| 1381 | RoReg8 Reserved3[0x2];
|
| 1382 | __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
|
| 1383 | __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
|
| 1384 | __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
|
| 1385 | __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
|
| 1386 | __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
|
| 1387 | __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
|
| 1388 | RoReg8 Reserved4[0x4];
|
| 1389 | DmacChannel Channel[32]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */
|
| 1390 | } Dmac;
|
| 1391 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1392 |
|
| 1393 | /** \brief DMAC Descriptor SRAM registers */
|
| 1394 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1395 | typedef struct {
|
| 1396 | __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
|
| 1397 | __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
|
| 1398 | __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
|
| 1399 | __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
|
| 1400 | __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
|
| 1401 | } DmacDescriptor
|
| 1402 | #ifdef __GNUC__
|
| 1403 | __attribute__ ((aligned (8)))
|
| 1404 | #endif
|
| 1405 | ;
|
| 1406 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1407 |
|
| 1408 | #ifdef __GNUC__
|
| 1409 | #define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".hsram")))
|
| 1410 | #elif defined(__ICCARM__)
|
| 1411 | #define SECTION_DMAC_DESCRIPTOR @".hsram"
|
| 1412 | #endif
|
| 1413 |
|
| 1414 | /*@}*/
|
| 1415 |
|
| 1416 | #endif /* _SAME54_DMAC_COMPONENT_ */
|