| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for AC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_AC_COMPONENT_
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| 31 | #define _SAME54_AC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR AC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_AC Analog Comparators */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define AC_U2501
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| 40 | #define REV_AC 0x100
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| 41 |
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| 42 | /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 49 | } bit; /*!< Structure used for bit access */
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| 50 | uint8_t reg; /*!< Type used for register access */
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| 51 | } AC_CTRLA_Type;
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| 52 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 53 |
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| 54 | #define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
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| 55 | #define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
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| 56 |
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| 57 | #define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
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| 58 | #define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
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| 59 | #define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
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| 60 | #define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
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| 61 | #define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
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| 62 |
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| 63 | /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
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| 64 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 65 | typedef union {
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| 66 | struct {
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| 67 | uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
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| 68 | uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
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| 69 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 70 | } bit; /*!< Structure used for bit access */
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| 71 | struct {
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| 72 | uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
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| 73 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 74 | } vec; /*!< Structure used for vec access */
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| 75 | uint8_t reg; /*!< Type used for register access */
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| 76 | } AC_CTRLB_Type;
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| 77 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 78 |
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| 79 | #define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
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| 80 | #define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
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| 81 |
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| 82 | #define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
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| 83 | #define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
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| 84 | #define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
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| 85 | #define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
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| 86 | #define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
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| 87 | #define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
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| 88 | #define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
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| 89 | #define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
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| 90 |
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| 91 | /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
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| 92 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 93 | typedef union {
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| 94 | struct {
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| 95 | uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
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| 96 | uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
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| 97 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 98 | uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
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| 99 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
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| 100 | uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
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| 101 | uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
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| 102 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 103 | uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
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| 104 | uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
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| 105 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 106 | } bit; /*!< Structure used for bit access */
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| 107 | struct {
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| 108 | uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
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| 109 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 110 | uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
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| 111 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
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| 112 | uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
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| 113 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 114 | uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
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| 115 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 116 | } vec; /*!< Structure used for vec access */
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| 117 | uint16_t reg; /*!< Type used for register access */
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| 118 | } AC_EVCTRL_Type;
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| 119 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 120 |
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| 121 | #define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
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| 122 | #define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
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| 123 |
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| 124 | #define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
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| 125 | #define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
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| 126 | #define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
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| 127 | #define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
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| 128 | #define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
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| 129 | #define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
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| 130 | #define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
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| 131 | #define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
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| 132 | #define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
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| 133 | #define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
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| 134 | #define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
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| 135 | #define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
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| 136 | #define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
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| 137 | #define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
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| 138 | #define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
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| 139 | #define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
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| 140 | #define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
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| 141 | #define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
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| 142 | #define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
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| 143 | #define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
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| 144 | #define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
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| 145 | #define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
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| 146 | #define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
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| 147 | #define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
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| 148 | #define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
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| 149 | #define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
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| 150 | #define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
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| 151 |
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| 152 | /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
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| 153 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 154 | typedef union {
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| 155 | struct {
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| 156 | uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
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| 157 | uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
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| 158 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 159 | uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
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| 160 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 161 | } bit; /*!< Structure used for bit access */
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| 162 | struct {
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| 163 | uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
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| 164 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 165 | uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
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| 166 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 167 | } vec; /*!< Structure used for vec access */
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| 168 | uint8_t reg; /*!< Type used for register access */
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| 169 | } AC_INTENCLR_Type;
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| 170 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 171 |
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| 172 | #define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
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| 173 | #define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
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| 174 |
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| 175 | #define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
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| 176 | #define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
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| 177 | #define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
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| 178 | #define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
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| 179 | #define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
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| 180 | #define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
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| 181 | #define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
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| 182 | #define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
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| 183 | #define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
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| 184 | #define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
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| 185 | #define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
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| 186 | #define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
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| 187 | #define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
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| 188 |
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| 189 | /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
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| 190 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 191 | typedef union {
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| 192 | struct {
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| 193 | uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
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| 194 | uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
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| 195 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 196 | uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
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| 197 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 198 | } bit; /*!< Structure used for bit access */
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| 199 | struct {
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| 200 | uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
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| 201 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 202 | uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
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| 203 | uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 204 | } vec; /*!< Structure used for vec access */
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| 205 | uint8_t reg; /*!< Type used for register access */
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| 206 | } AC_INTENSET_Type;
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| 207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 208 |
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| 209 | #define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
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| 210 | #define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
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| 211 |
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| 212 | #define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
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| 213 | #define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
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| 214 | #define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
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| 215 | #define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
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| 216 | #define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
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| 217 | #define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
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| 218 | #define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
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| 219 | #define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
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| 220 | #define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
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| 221 | #define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
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| 222 | #define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
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| 223 | #define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
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| 224 | #define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
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| 225 |
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| 226 | /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 227 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 228 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 229 | struct {
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| 230 | __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
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| 231 | __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
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| 232 | __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 233 | __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
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| 234 | __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 235 | } bit; /*!< Structure used for bit access */
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| 236 | struct {
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| 237 | __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
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| 238 | __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 239 | __I uint8_t WIN:1; /*!< bit: 4 Window x */
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| 240 | __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
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| 241 | } vec; /*!< Structure used for vec access */
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| 242 | uint8_t reg; /*!< Type used for register access */
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| 243 | } AC_INTFLAG_Type;
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| 244 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 245 |
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| 246 | #define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
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| 247 | #define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 248 |
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| 249 | #define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
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| 250 | #define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
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| 251 | #define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
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| 252 | #define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
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| 253 | #define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
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| 254 | #define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
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| 255 | #define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
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| 256 | #define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
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| 257 | #define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
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| 258 | #define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
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| 259 | #define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
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| 260 | #define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
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| 261 | #define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
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| 262 |
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| 263 | /* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
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| 264 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 265 | typedef union {
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| 266 | struct {
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| 267 | uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
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| 268 | uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
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| 269 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 270 | uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
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| 271 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 272 | } bit; /*!< Structure used for bit access */
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| 273 | struct {
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| 274 | uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
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| 275 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 276 | } vec; /*!< Structure used for vec access */
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| 277 | uint8_t reg; /*!< Type used for register access */
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| 278 | } AC_STATUSA_Type;
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| 279 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 280 |
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| 281 | #define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
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| 282 | #define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
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| 283 |
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| 284 | #define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
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| 285 | #define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
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| 286 | #define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
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| 287 | #define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
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| 288 | #define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
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| 289 | #define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
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| 290 | #define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
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| 291 | #define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
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| 292 | #define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
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| 293 | #define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
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| 294 | #define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
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| 295 | #define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
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| 296 | #define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
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| 297 | #define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
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| 298 | #define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
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| 299 | #define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
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| 300 | #define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
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| 301 |
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| 302 | /* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
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| 303 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 304 | typedef union {
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| 305 | struct {
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| 306 | uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
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| 307 | uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
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| 308 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 309 | } bit; /*!< Structure used for bit access */
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| 310 | struct {
|
| 311 | uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
|
| 312 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
| 313 | } vec; /*!< Structure used for vec access */
|
| 314 | uint8_t reg; /*!< Type used for register access */
|
| 315 | } AC_STATUSB_Type;
|
| 316 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 317 |
|
| 318 | #define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
|
| 319 | #define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
|
| 320 |
|
| 321 | #define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
|
| 322 | #define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
|
| 323 | #define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
|
| 324 | #define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
|
| 325 | #define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
|
| 326 | #define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
|
| 327 | #define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
|
| 328 | #define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
|
| 329 |
|
| 330 | /* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
|
| 331 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 332 | typedef union {
|
| 333 | struct {
|
| 334 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
| 335 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
| 336 | } bit; /*!< Structure used for bit access */
|
| 337 | uint8_t reg; /*!< Type used for register access */
|
| 338 | } AC_DBGCTRL_Type;
|
| 339 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 340 |
|
| 341 | #define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
|
| 342 | #define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
|
| 343 |
|
| 344 | #define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
|
| 345 | #define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
|
| 346 | #define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
|
| 347 |
|
| 348 | /* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
|
| 349 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 350 | typedef union {
|
| 351 | struct {
|
| 352 | uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
|
| 353 | uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
|
| 354 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
| 355 | } bit; /*!< Structure used for bit access */
|
| 356 | uint8_t reg; /*!< Type used for register access */
|
| 357 | } AC_WINCTRL_Type;
|
| 358 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 359 |
|
| 360 | #define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
|
| 361 | #define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
|
| 362 |
|
| 363 | #define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
|
| 364 | #define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
|
| 365 | #define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
|
| 366 | #define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
|
| 367 | #define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
|
| 368 | #define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
|
| 369 | #define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
|
| 370 | #define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
|
| 371 | #define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
|
| 372 | #define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
| 373 | #define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
| 374 | #define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
|
| 375 | #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
| 376 | #define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
|
| 377 |
|
| 378 | /* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
|
| 379 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 380 | typedef union {
|
| 381 | struct {
|
| 382 | uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
|
| 383 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
| 384 | } bit; /*!< Structure used for bit access */
|
| 385 | uint8_t reg; /*!< Type used for register access */
|
| 386 | } AC_SCALER_Type;
|
| 387 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 388 |
|
| 389 | #define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
|
| 390 | #define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
|
| 391 |
|
| 392 | #define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
|
| 393 | #define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
|
| 394 | #define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
|
| 395 | #define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
|
| 396 |
|
| 397 | /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
|
| 398 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 399 | typedef union {
|
| 400 | struct {
|
| 401 | uint32_t :1; /*!< bit: 0 Reserved */
|
| 402 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
| 403 | uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
|
| 404 | uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
|
| 405 | uint32_t :1; /*!< bit: 5 Reserved */
|
| 406 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
|
| 407 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 408 | uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
|
| 409 | uint32_t :1; /*!< bit: 11 Reserved */
|
| 410 | uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
|
| 411 | uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
|
| 412 | uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
|
| 413 | uint32_t :1; /*!< bit: 18 Reserved */
|
| 414 | uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
|
| 415 | uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
|
| 416 | uint32_t :2; /*!< bit: 22..23 Reserved */
|
| 417 | uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
|
| 418 | uint32_t :1; /*!< bit: 27 Reserved */
|
| 419 | uint32_t OUT:2; /*!< bit: 28..29 Output */
|
| 420 | uint32_t :2; /*!< bit: 30..31 Reserved */
|
| 421 | } bit; /*!< Structure used for bit access */
|
| 422 | uint32_t reg; /*!< Type used for register access */
|
| 423 | } AC_COMPCTRL_Type;
|
| 424 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 425 |
|
| 426 | #define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
|
| 427 | #define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
|
| 428 |
|
| 429 | #define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
|
| 430 | #define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
|
| 431 | #define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
|
| 432 | #define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
|
| 433 | #define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
|
| 434 | #define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
|
| 435 | #define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
|
| 436 | #define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
|
| 437 | #define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
|
| 438 | #define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
|
| 439 | #define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
|
| 440 | #define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
|
| 441 | #define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
|
| 442 | #define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
|
| 443 | #define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
|
| 444 | #define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
|
| 445 | #define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
|
| 446 | #define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
|
| 447 | #define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
|
| 448 | #define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
|
| 449 | #define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
| 450 | #define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
| 451 | #define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
| 452 | #define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
| 453 | #define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
|
| 454 | #define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
|
| 455 | #define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
|
| 456 | #define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
|
| 457 | #define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 458 | #define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 459 | #define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 460 | #define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 461 | #define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 462 | #define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 463 | #define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 464 | #define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
|
| 465 | #define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
|
| 466 | #define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
|
| 467 | #define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
|
| 468 | #define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
| 469 | #define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
| 470 | #define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
| 471 | #define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
| 472 | #define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
|
| 473 | #define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
|
| 474 | #define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
|
| 475 | #define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
|
| 476 | #define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
|
| 477 | #define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
|
| 478 | #define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
|
| 479 | #define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
|
| 480 | #define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
|
| 481 | #define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
|
| 482 | #define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
|
| 483 | #define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
|
| 484 | #define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
|
| 485 | #define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
|
| 486 | #define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
|
| 487 | #define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
|
| 488 | #define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
|
| 489 | #define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
|
| 490 | #define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
|
| 491 | #define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
|
| 492 | #define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
|
| 493 | #define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
|
| 494 | #define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
|
| 495 | #define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
|
| 496 | #define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
|
| 497 | #define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
|
| 498 | #define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
|
| 499 | #define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
|
| 500 | #define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
|
| 501 | #define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
|
| 502 | #define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
|
| 503 | #define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
|
| 504 | #define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
|
| 505 | #define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
|
| 506 | #define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
|
| 507 | #define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
|
| 508 | #define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
|
| 509 | #define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
|
| 510 | #define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
|
| 511 | #define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
|
| 512 | #define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
|
| 513 | #define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
|
| 514 | #define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
|
| 515 |
|
| 516 | /* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
|
| 517 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 518 | typedef union {
|
| 519 | struct {
|
| 520 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
| 521 | uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
|
| 522 | uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
|
| 523 | uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
|
| 524 | uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
|
| 525 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 526 | } bit; /*!< Structure used for bit access */
|
| 527 | struct {
|
| 528 | uint32_t :3; /*!< bit: 0.. 2 Reserved */
|
| 529 | uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
|
| 530 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 531 | } vec; /*!< Structure used for vec access */
|
| 532 | uint32_t reg; /*!< Type used for register access */
|
| 533 | } AC_SYNCBUSY_Type;
|
| 534 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 535 |
|
| 536 | #define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
|
| 537 | #define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
|
| 538 |
|
| 539 | #define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
|
| 540 | #define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
|
| 541 | #define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
|
| 542 | #define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
|
| 543 | #define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
|
| 544 | #define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
|
| 545 | #define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
|
| 546 | #define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
|
| 547 | #define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
|
| 548 | #define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
|
| 549 | #define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
|
| 550 | #define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
|
| 551 | #define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
|
| 552 | #define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
|
| 553 |
|
| 554 | /* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
|
| 555 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 556 | typedef union {
|
| 557 | struct {
|
| 558 | uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
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| 559 | uint16_t :14; /*!< bit: 2..15 Reserved */
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| 560 | } bit; /*!< Structure used for bit access */
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| 561 | uint16_t reg; /*!< Type used for register access */
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| 562 | } AC_CALIB_Type;
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| 563 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 564 |
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| 565 | #define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
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| 566 | #define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
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| 567 |
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| 568 | #define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
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| 569 | #define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
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| 570 | #define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
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| 571 | #define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
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| 572 |
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| 573 | /** \brief AC hardware registers */
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| 574 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 575 | typedef struct {
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| 576 | __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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| 577 | __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
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| 578 | __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
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| 579 | __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
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| 580 | __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
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| 581 | __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
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| 582 | __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
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| 583 | __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
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| 584 | __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
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| 585 | __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
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| 586 | RoReg8 Reserved1[0x1];
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| 587 | __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
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| 588 | RoReg8 Reserved2[0x2];
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| 589 | __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
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| 590 | RoReg8 Reserved3[0x8];
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| 591 | __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
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| 592 | __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
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| 593 | } Ac;
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| 594 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 595 |
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| 596 | /*@}*/
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| 597 |
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| 598 | #endif /* _SAME54_AC_COMPONENT_ */
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