Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for SERCOM
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_SERCOM_COMPONENT_
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| 31 | #define _SAME54_SERCOM_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR SERCOM */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_SERCOM Serial Communication Interface */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define SERCOM_U2201
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| 40 | #define REV_SERCOM 0x500
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| 41 |
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| 42 | /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
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| 49 | uint32_t :2; /*!< bit: 5.. 6 Reserved */
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| 50 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
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| 51 | uint32_t :8; /*!< bit: 8..15 Reserved */
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| 52 | uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
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| 53 | uint32_t :3; /*!< bit: 17..19 Reserved */
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| 54 | uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
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| 55 | uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
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| 56 | uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
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| 57 | uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
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| 58 | uint32_t :1; /*!< bit: 26 Reserved */
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| 59 | uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
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| 60 | uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
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| 61 | uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
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| 62 | uint32_t :1; /*!< bit: 31 Reserved */
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| 63 | } bit; /*!< Structure used for bit access */
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| 64 | uint32_t reg; /*!< Type used for register access */
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| 65 | } SERCOM_I2CM_CTRLA_Type;
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| 66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 67 |
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| 68 | #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
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| 69 | #define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
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| 70 |
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| 71 | #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
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| 72 | #define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
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| 73 | #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
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| 74 | #define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
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| 75 | #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
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| 76 | #define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
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| 77 | #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
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| 78 | #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
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| 79 | #define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
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| 80 | #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
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| 81 | #define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
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| 82 | #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
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| 83 | #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
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| 84 | #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
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| 85 | #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
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| 86 | #define SERCOM_I2CM_CTRLA_MEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
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| 87 | #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
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| 88 | #define SERCOM_I2CM_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
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| 89 | #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
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| 90 | #define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
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| 91 | #define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
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| 92 | #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
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| 93 | #define SERCOM_I2CM_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
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| 94 | #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
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| 95 | #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
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| 96 | #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
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| 97 | #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
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| 98 | #define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
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| 99 | #define SERCOM_I2CM_CTRLA_MASK _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
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| 100 |
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| 101 | /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
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| 102 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 103 | typedef union {
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| 104 | struct {
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| 105 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 106 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 107 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
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| 108 | uint32_t :2; /*!< bit: 5.. 6 Reserved */
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| 109 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
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| 110 | uint32_t :8; /*!< bit: 8..15 Reserved */
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| 111 | uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
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| 112 | uint32_t :3; /*!< bit: 17..19 Reserved */
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| 113 | uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
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| 114 | uint32_t :1; /*!< bit: 22 Reserved */
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| 115 | uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
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| 116 | uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
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| 117 | uint32_t :1; /*!< bit: 26 Reserved */
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| 118 | uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
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| 119 | uint32_t :2; /*!< bit: 28..29 Reserved */
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| 120 | uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
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| 121 | uint32_t :1; /*!< bit: 31 Reserved */
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| 122 | } bit; /*!< Structure used for bit access */
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| 123 | uint32_t reg; /*!< Type used for register access */
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| 124 | } SERCOM_I2CS_CTRLA_Type;
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| 125 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 126 |
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| 127 | #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
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| 128 | #define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
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| 129 |
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| 130 | #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
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| 131 | #define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
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| 132 | #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
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| 133 | #define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
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| 134 | #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
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| 135 | #define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
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| 136 | #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
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| 137 | #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
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| 138 | #define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
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| 139 | #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
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| 140 | #define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
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| 141 | #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
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| 142 | #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
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| 143 | #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
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| 144 | #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
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| 145 | #define SERCOM_I2CS_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
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| 146 | #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
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| 147 | #define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
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| 148 | #define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
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| 149 | #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
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| 150 | #define SERCOM_I2CS_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
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| 151 | #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
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| 152 | #define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
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| 153 | #define SERCOM_I2CS_CTRLA_MASK _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
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| 154 |
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| 155 | /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
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| 156 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 157 | typedef union {
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| 158 | struct {
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| 159 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 160 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 161 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
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| 162 | uint32_t :2; /*!< bit: 5.. 6 Reserved */
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| 163 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
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| 164 | uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
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| 165 | uint32_t :7; /*!< bit: 9..15 Reserved */
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| 166 | uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
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| 167 | uint32_t :2; /*!< bit: 18..19 Reserved */
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| 168 | uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
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| 169 | uint32_t :2; /*!< bit: 22..23 Reserved */
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| 170 | uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
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| 171 | uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
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| 172 | uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
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| 173 | uint32_t DORD:1; /*!< bit: 30 Data Order */
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| 174 | uint32_t :1; /*!< bit: 31 Reserved */
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| 175 | } bit; /*!< Structure used for bit access */
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| 176 | uint32_t reg; /*!< Type used for register access */
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| 177 | } SERCOM_SPI_CTRLA_Type;
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| 178 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 179 |
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| 180 | #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
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| 181 | #define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
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| 182 |
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| 183 | #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
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| 184 | #define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
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| 185 | #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
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| 186 | #define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
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| 187 | #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
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| 188 | #define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
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| 189 | #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
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| 190 | #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
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| 191 | #define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
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| 192 | #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
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| 193 | #define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
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| 194 | #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
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| 195 | #define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
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| 196 | #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
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| 197 | #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
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| 198 | #define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
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| 199 | #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
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| 200 | #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
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| 201 | #define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
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| 202 | #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
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| 203 | #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
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| 204 | #define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
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| 205 | #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
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| 206 | #define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
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| 207 | #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
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| 208 | #define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
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| 209 | #define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
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| 210 |
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| 211 | /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
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| 212 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 213 | typedef union {
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| 214 | struct {
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| 215 | uint32_t SWRST:1; /*!< bit: 0 Software Reset */
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| 216 | uint32_t ENABLE:1; /*!< bit: 1 Enable */
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| 217 | uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
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| 218 | uint32_t :2; /*!< bit: 5.. 6 Reserved */
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| 219 | uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
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| 220 | uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
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| 221 | uint32_t TXINV:1; /*!< bit: 9 Transmit Data Invert */
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| 222 | uint32_t RXINV:1; /*!< bit: 10 Receive Data Invert */
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| 223 | uint32_t :2; /*!< bit: 11..12 Reserved */
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| 224 | uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
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| 225 | uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
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| 226 | uint32_t :2; /*!< bit: 18..19 Reserved */
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| 227 | uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
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| 228 | uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
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| 229 | uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
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| 230 | uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
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| 231 | uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
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| 232 | uint32_t DORD:1; /*!< bit: 30 Data Order */
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| 233 | uint32_t :1; /*!< bit: 31 Reserved */
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| 234 | } bit; /*!< Structure used for bit access */
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| 235 | uint32_t reg; /*!< Type used for register access */
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| 236 | } SERCOM_USART_CTRLA_Type;
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| 237 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 238 |
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| 239 | #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
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| 240 | #define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
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| 241 |
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| 242 | #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
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| 243 | #define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
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| 244 | #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
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| 245 | #define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
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| 246 | #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
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| 247 | #define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
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| 248 | #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
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| 249 | #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
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| 250 | #define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
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| 251 | #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
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| 252 | #define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
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| 253 | #define SERCOM_USART_CTRLA_TXINV_Pos 9 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
|
| 254 | #define SERCOM_USART_CTRLA_TXINV (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
|
| 255 | #define SERCOM_USART_CTRLA_RXINV_Pos 10 /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
|
| 256 | #define SERCOM_USART_CTRLA_RXINV (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
|
| 257 | #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
|
| 258 | #define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
|
| 259 | #define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
|
| 260 | #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
|
| 261 | #define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
|
| 262 | #define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
|
| 263 | #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
|
| 264 | #define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
|
| 265 | #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
|
| 266 | #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
|
| 267 | #define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
|
| 268 | #define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
|
| 269 | #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
|
| 270 | #define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
|
| 271 | #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
|
| 272 | #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
|
| 273 | #define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
|
| 274 | #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
|
| 275 | #define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
|
| 276 | #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
|
| 277 | #define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
|
| 278 | #define SERCOM_USART_CTRLA_MASK _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
|
| 279 |
|
| 280 | /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
|
| 281 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 282 | typedef union {
|
| 283 | struct {
|
| 284 | uint32_t :8; /*!< bit: 0.. 7 Reserved */
|
| 285 | uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
|
| 286 | uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
|
| 287 | uint32_t :6; /*!< bit: 10..15 Reserved */
|
| 288 | uint32_t CMD:2; /*!< bit: 16..17 Command */
|
| 289 | uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
|
| 290 | uint32_t :13; /*!< bit: 19..31 Reserved */
|
| 291 | } bit; /*!< Structure used for bit access */
|
| 292 | uint32_t reg; /*!< Type used for register access */
|
| 293 | } SERCOM_I2CM_CTRLB_Type;
|
| 294 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 295 |
|
| 296 | #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
|
| 297 | #define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
|
| 298 |
|
| 299 | #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
|
| 300 | #define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
|
| 301 | #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
|
| 302 | #define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
|
| 303 | #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
|
| 304 | #define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
|
| 305 | #define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
|
| 306 | #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
|
| 307 | #define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
|
| 308 | #define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
|
| 309 |
|
| 310 | /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
|
| 311 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 312 | typedef union {
|
| 313 | struct {
|
| 314 | uint32_t :8; /*!< bit: 0.. 7 Reserved */
|
| 315 | uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
|
| 316 | uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
|
| 317 | uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
|
| 318 | uint32_t :3; /*!< bit: 11..13 Reserved */
|
| 319 | uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
|
| 320 | uint32_t CMD:2; /*!< bit: 16..17 Command */
|
| 321 | uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
|
| 322 | uint32_t :13; /*!< bit: 19..31 Reserved */
|
| 323 | } bit; /*!< Structure used for bit access */
|
| 324 | uint32_t reg; /*!< Type used for register access */
|
| 325 | } SERCOM_I2CS_CTRLB_Type;
|
| 326 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 327 |
|
| 328 | #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
|
| 329 | #define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
|
| 330 |
|
| 331 | #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
|
| 332 | #define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
|
| 333 | #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
|
| 334 | #define SERCOM_I2CS_CTRLB_GCMD (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
|
| 335 | #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
|
| 336 | #define SERCOM_I2CS_CTRLB_AACKEN (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
|
| 337 | #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
|
| 338 | #define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
|
| 339 | #define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
|
| 340 | #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
|
| 341 | #define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
|
| 342 | #define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
|
| 343 | #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
|
| 344 | #define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
|
| 345 | #define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
|
| 346 |
|
| 347 | /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
|
| 348 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 349 | typedef union {
|
| 350 | struct {
|
| 351 | uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
|
| 352 | uint32_t :3; /*!< bit: 3.. 5 Reserved */
|
| 353 | uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
|
| 354 | uint32_t :2; /*!< bit: 7.. 8 Reserved */
|
| 355 | uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
|
| 356 | uint32_t :3; /*!< bit: 10..12 Reserved */
|
| 357 | uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
|
| 358 | uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
|
| 359 | uint32_t :1; /*!< bit: 16 Reserved */
|
| 360 | uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
|
| 361 | uint32_t :14; /*!< bit: 18..31 Reserved */
|
| 362 | } bit; /*!< Structure used for bit access */
|
| 363 | uint32_t reg; /*!< Type used for register access */
|
| 364 | } SERCOM_SPI_CTRLB_Type;
|
| 365 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 366 |
|
| 367 | #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
|
| 368 | #define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
|
| 369 |
|
| 370 | #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
|
| 371 | #define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
|
| 372 | #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
|
| 373 | #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
|
| 374 | #define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
|
| 375 | #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
|
| 376 | #define SERCOM_SPI_CTRLB_SSDE (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
|
| 377 | #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
|
| 378 | #define SERCOM_SPI_CTRLB_MSSEN (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
|
| 379 | #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
|
| 380 | #define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
|
| 381 | #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
|
| 382 | #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
|
| 383 | #define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
|
| 384 | #define SERCOM_SPI_CTRLB_MASK _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
|
| 385 |
|
| 386 | /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
|
| 387 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 388 | typedef union {
|
| 389 | struct {
|
| 390 | uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
|
| 391 | uint32_t :3; /*!< bit: 3.. 5 Reserved */
|
| 392 | uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
|
| 393 | uint32_t :1; /*!< bit: 7 Reserved */
|
| 394 | uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
|
| 395 | uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
|
| 396 | uint32_t ENC:1; /*!< bit: 10 Encoding Format */
|
| 397 | uint32_t :2; /*!< bit: 11..12 Reserved */
|
| 398 | uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
|
| 399 | uint32_t :2; /*!< bit: 14..15 Reserved */
|
| 400 | uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
|
| 401 | uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
|
| 402 | uint32_t :6; /*!< bit: 18..23 Reserved */
|
| 403 | uint32_t LINCMD:2; /*!< bit: 24..25 LIN Command */
|
| 404 | uint32_t :6; /*!< bit: 26..31 Reserved */
|
| 405 | } bit; /*!< Structure used for bit access */
|
| 406 | uint32_t reg; /*!< Type used for register access */
|
| 407 | } SERCOM_USART_CTRLB_Type;
|
| 408 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 409 |
|
| 410 | #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
|
| 411 | #define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
|
| 412 |
|
| 413 | #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
|
| 414 | #define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
|
| 415 | #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
|
| 416 | #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
|
| 417 | #define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
|
| 418 | #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
|
| 419 | #define SERCOM_USART_CTRLB_COLDEN (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
|
| 420 | #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
|
| 421 | #define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
|
| 422 | #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
|
| 423 | #define SERCOM_USART_CTRLB_ENC (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
|
| 424 | #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
|
| 425 | #define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
|
| 426 | #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
|
| 427 | #define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
|
| 428 | #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
|
| 429 | #define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
|
| 430 | #define SERCOM_USART_CTRLB_LINCMD_Pos 24 /**< \brief (SERCOM_USART_CTRLB) LIN Command */
|
| 431 | #define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
|
| 432 | #define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
|
| 433 | #define SERCOM_USART_CTRLB_MASK _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
|
| 434 |
|
| 435 | /* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM I2CM Control C -------- */
|
| 436 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 437 | typedef union {
|
| 438 | struct {
|
| 439 | uint32_t :24; /*!< bit: 0..23 Reserved */
|
| 440 | uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
|
| 441 | uint32_t :7; /*!< bit: 25..31 Reserved */
|
| 442 | } bit; /*!< Structure used for bit access */
|
| 443 | uint32_t reg; /*!< Type used for register access */
|
| 444 | } SERCOM_I2CM_CTRLC_Type;
|
| 445 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 446 |
|
| 447 | #define SERCOM_I2CM_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CM_CTRLC offset) I2CM Control C */
|
| 448 | #define SERCOM_I2CM_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLC reset_value) I2CM Control C */
|
| 449 |
|
| 450 | #define SERCOM_I2CM_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CM_CTRLC) Data 32 Bit */
|
| 451 | #define SERCOM_I2CM_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)
|
| 452 | #define SERCOM_I2CM_CTRLC_MASK _U_(0x01000000) /**< \brief (SERCOM_I2CM_CTRLC) MASK Register */
|
| 453 |
|
| 454 | /* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS I2CS Control C -------- */
|
| 455 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 456 | typedef union {
|
| 457 | struct {
|
| 458 | uint32_t SDASETUP:4; /*!< bit: 0.. 3 SDA Setup Time */
|
| 459 | uint32_t :20; /*!< bit: 4..23 Reserved */
|
| 460 | uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
|
| 461 | uint32_t :7; /*!< bit: 25..31 Reserved */
|
| 462 | } bit; /*!< Structure used for bit access */
|
| 463 | uint32_t reg; /*!< Type used for register access */
|
| 464 | } SERCOM_I2CS_CTRLC_Type;
|
| 465 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 466 |
|
| 467 | #define SERCOM_I2CS_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_I2CS_CTRLC offset) I2CS Control C */
|
| 468 | #define SERCOM_I2CS_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLC reset_value) I2CS Control C */
|
| 469 |
|
| 470 | #define SERCOM_I2CS_CTRLC_SDASETUP_Pos 0 /**< \brief (SERCOM_I2CS_CTRLC) SDA Setup Time */
|
| 471 | #define SERCOM_I2CS_CTRLC_SDASETUP_Msk (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)
|
| 472 | #define SERCOM_I2CS_CTRLC_SDASETUP(value) (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
|
| 473 | #define SERCOM_I2CS_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_I2CS_CTRLC) Data 32 Bit */
|
| 474 | #define SERCOM_I2CS_CTRLC_DATA32B (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)
|
| 475 | #define SERCOM_I2CS_CTRLC_MASK _U_(0x0100000F) /**< \brief (SERCOM_I2CS_CTRLC) MASK Register */
|
| 476 |
|
| 477 | /* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
|
| 478 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 479 | typedef union {
|
| 480 | struct {
|
| 481 | uint32_t ICSPACE:6; /*!< bit: 0.. 5 Inter-Character Spacing */
|
| 482 | uint32_t :18; /*!< bit: 6..23 Reserved */
|
| 483 | uint32_t DATA32B:1; /*!< bit: 24 Data 32 Bit */
|
| 484 | uint32_t :7; /*!< bit: 25..31 Reserved */
|
| 485 | } bit; /*!< Structure used for bit access */
|
| 486 | uint32_t reg; /*!< Type used for register access */
|
| 487 | } SERCOM_SPI_CTRLC_Type;
|
| 488 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 489 |
|
| 490 | #define SERCOM_SPI_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
|
| 491 | #define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
|
| 492 |
|
| 493 | #define SERCOM_SPI_CTRLC_ICSPACE_Pos 0 /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
|
| 494 | #define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
|
| 495 | #define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
|
| 496 | #define SERCOM_SPI_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
|
| 497 | #define SERCOM_SPI_CTRLC_DATA32B (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
|
| 498 | #define SERCOM_SPI_CTRLC_MASK _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
|
| 499 |
|
| 500 | /* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
|
| 501 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 502 | typedef union {
|
| 503 | struct {
|
| 504 | uint32_t GTIME:3; /*!< bit: 0.. 2 Guard Time */
|
| 505 | uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
| 506 | uint32_t BRKLEN:2; /*!< bit: 8.. 9 LIN Master Break Length */
|
| 507 | uint32_t HDRDLY:2; /*!< bit: 10..11 LIN Master Header Delay */
|
| 508 | uint32_t :4; /*!< bit: 12..15 Reserved */
|
| 509 | uint32_t INACK:1; /*!< bit: 16 Inhibit Not Acknowledge */
|
| 510 | uint32_t DSNACK:1; /*!< bit: 17 Disable Successive NACK */
|
| 511 | uint32_t :2; /*!< bit: 18..19 Reserved */
|
| 512 | uint32_t MAXITER:3; /*!< bit: 20..22 Maximum Iterations */
|
| 513 | uint32_t :1; /*!< bit: 23 Reserved */
|
| 514 | uint32_t DATA32B:2; /*!< bit: 24..25 Data 32 Bit */
|
| 515 | uint32_t :6; /*!< bit: 26..31 Reserved */
|
| 516 | } bit; /*!< Structure used for bit access */
|
| 517 | uint32_t reg; /*!< Type used for register access */
|
| 518 | } SERCOM_USART_CTRLC_Type;
|
| 519 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 520 |
|
| 521 | #define SERCOM_USART_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
|
| 522 | #define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
|
| 523 |
|
| 524 | #define SERCOM_USART_CTRLC_GTIME_Pos 0 /**< \brief (SERCOM_USART_CTRLC) Guard Time */
|
| 525 | #define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
|
| 526 | #define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
|
| 527 | #define SERCOM_USART_CTRLC_BRKLEN_Pos 8 /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
|
| 528 | #define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
|
| 529 | #define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
|
| 530 | #define SERCOM_USART_CTRLC_HDRDLY_Pos 10 /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
|
| 531 | #define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
|
| 532 | #define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
|
| 533 | #define SERCOM_USART_CTRLC_INACK_Pos 16 /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
|
| 534 | #define SERCOM_USART_CTRLC_INACK (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
|
| 535 | #define SERCOM_USART_CTRLC_DSNACK_Pos 17 /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
|
| 536 | #define SERCOM_USART_CTRLC_DSNACK (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
|
| 537 | #define SERCOM_USART_CTRLC_MAXITER_Pos 20 /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
|
| 538 | #define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
|
| 539 | #define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
|
| 540 | #define SERCOM_USART_CTRLC_DATA32B_Pos 24 /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
|
| 541 | #define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
|
| 542 | #define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
|
| 543 | #define SERCOM_USART_CTRLC_MASK _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
|
| 544 |
|
| 545 | /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
|
| 546 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 547 | typedef union {
|
| 548 | struct {
|
| 549 | uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
|
| 550 | uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
|
| 551 | uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
|
| 552 | uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
|
| 553 | } bit; /*!< Structure used for bit access */
|
| 554 | uint32_t reg; /*!< Type used for register access */
|
| 555 | } SERCOM_I2CM_BAUD_Type;
|
| 556 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 557 |
|
| 558 | #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
|
| 559 | #define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
|
| 560 |
|
| 561 | #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
|
| 562 | #define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
|
| 563 | #define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
|
| 564 | #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
|
| 565 | #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
|
| 566 | #define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
|
| 567 | #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
|
| 568 | #define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
|
| 569 | #define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
|
| 570 | #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
|
| 571 | #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
|
| 572 | #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
|
| 573 | #define SERCOM_I2CM_BAUD_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
|
| 574 |
|
| 575 | /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
|
| 576 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 577 | typedef union {
|
| 578 | struct {
|
| 579 | uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
|
| 580 | } bit; /*!< Structure used for bit access */
|
| 581 | uint8_t reg; /*!< Type used for register access */
|
| 582 | } SERCOM_SPI_BAUD_Type;
|
| 583 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 584 |
|
| 585 | #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
|
| 586 | #define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
|
| 587 |
|
| 588 | #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
|
| 589 | #define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
|
| 590 | #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
|
| 591 | #define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */
|
| 592 |
|
| 593 | /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
|
| 594 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 595 | typedef union {
|
| 596 | struct {
|
| 597 | uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
|
| 598 | } bit; /*!< Structure used for bit access */
|
| 599 | struct { // FRAC mode
|
| 600 | uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
|
| 601 | uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
|
| 602 | } FRAC; /*!< Structure used for FRAC */
|
| 603 | struct { // FRACFP mode
|
| 604 | uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
|
| 605 | uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
|
| 606 | } FRACFP; /*!< Structure used for FRACFP */
|
| 607 | struct { // USARTFP mode
|
| 608 | uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
|
| 609 | } USARTFP; /*!< Structure used for USARTFP */
|
| 610 | uint16_t reg; /*!< Type used for register access */
|
| 611 | } SERCOM_USART_BAUD_Type;
|
| 612 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 613 |
|
| 614 | #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
|
| 615 | #define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
|
| 616 |
|
| 617 | #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
|
| 618 | #define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
|
| 619 | #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
|
| 620 | #define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */
|
| 621 |
|
| 622 | // FRAC mode
|
| 623 | #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
|
| 624 | #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
|
| 625 | #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
|
| 626 | #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
|
| 627 | #define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
|
| 628 | #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
|
| 629 | #define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
|
| 630 |
|
| 631 | // FRACFP mode
|
| 632 | #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
|
| 633 | #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
|
| 634 | #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
|
| 635 | #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
|
| 636 | #define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
|
| 637 | #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
|
| 638 | #define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
|
| 639 |
|
| 640 | // USARTFP mode
|
| 641 | #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
|
| 642 | #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
|
| 643 | #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
|
| 644 | #define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
|
| 645 |
|
| 646 | /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
|
| 647 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 648 | typedef union {
|
| 649 | struct {
|
| 650 | uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
|
| 651 | } bit; /*!< Structure used for bit access */
|
| 652 | uint8_t reg; /*!< Type used for register access */
|
| 653 | } SERCOM_USART_RXPL_Type;
|
| 654 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 655 |
|
| 656 | #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
|
| 657 | #define SERCOM_USART_RXPL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
|
| 658 |
|
| 659 | #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
|
| 660 | #define SERCOM_USART_RXPL_RXPL_Msk (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
|
| 661 | #define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
|
| 662 | #define SERCOM_USART_RXPL_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */
|
| 663 |
|
| 664 | /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
|
| 665 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 666 | typedef union {
|
| 667 | struct {
|
| 668 | uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
|
| 669 | uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
|
| 670 | uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
| 671 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
|
| 672 | } bit; /*!< Structure used for bit access */
|
| 673 | uint8_t reg; /*!< Type used for register access */
|
| 674 | } SERCOM_I2CM_INTENCLR_Type;
|
| 675 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 676 |
|
| 677 | #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
|
| 678 | #define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
|
| 679 |
|
| 680 | #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
|
| 681 | #define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
|
| 682 | #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
|
| 683 | #define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
|
| 684 | #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
|
| 685 | #define SERCOM_I2CM_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
|
| 686 | #define SERCOM_I2CM_INTENCLR_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
|
| 687 |
|
| 688 | /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
|
| 689 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 690 | typedef union {
|
| 691 | struct {
|
| 692 | uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
|
| 693 | uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
|
| 694 | uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
|
| 695 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
| 696 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
|
| 697 | } bit; /*!< Structure used for bit access */
|
| 698 | uint8_t reg; /*!< Type used for register access */
|
| 699 | } SERCOM_I2CS_INTENCLR_Type;
|
| 700 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 701 |
|
| 702 | #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
|
| 703 | #define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
|
| 704 |
|
| 705 | #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
|
| 706 | #define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
|
| 707 | #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
|
| 708 | #define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
|
| 709 | #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
|
| 710 | #define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
|
| 711 | #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
|
| 712 | #define SERCOM_I2CS_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
|
| 713 | #define SERCOM_I2CS_INTENCLR_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
|
| 714 |
|
| 715 | /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
|
| 716 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 717 | typedef union {
|
| 718 | struct {
|
| 719 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
|
| 720 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
|
| 721 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
|
| 722 | uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
|
| 723 | uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
| 724 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
|
| 725 | } bit; /*!< Structure used for bit access */
|
| 726 | uint8_t reg; /*!< Type used for register access */
|
| 727 | } SERCOM_SPI_INTENCLR_Type;
|
| 728 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 729 |
|
| 730 | #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
|
| 731 | #define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
|
| 732 |
|
| 733 | #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
|
| 734 | #define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
|
| 735 | #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
|
| 736 | #define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
|
| 737 | #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
|
| 738 | #define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
|
| 739 | #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
|
| 740 | #define SERCOM_SPI_INTENCLR_SSL (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
|
| 741 | #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
|
| 742 | #define SERCOM_SPI_INTENCLR_ERROR (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
|
| 743 | #define SERCOM_SPI_INTENCLR_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
|
| 744 |
|
| 745 | /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
|
| 746 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 747 | typedef union {
|
| 748 | struct {
|
| 749 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
|
| 750 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
|
| 751 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
|
| 752 | uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
|
| 753 | uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
|
| 754 | uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
|
| 755 | uint8_t :1; /*!< bit: 6 Reserved */
|
| 756 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
|
| 757 | } bit; /*!< Structure used for bit access */
|
| 758 | uint8_t reg; /*!< Type used for register access */
|
| 759 | } SERCOM_USART_INTENCLR_Type;
|
| 760 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 761 |
|
| 762 | #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
|
| 763 | #define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
|
| 764 |
|
| 765 | #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
|
| 766 | #define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
|
| 767 | #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
|
| 768 | #define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
|
| 769 | #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
|
| 770 | #define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
|
| 771 | #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
|
| 772 | #define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
|
| 773 | #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
|
| 774 | #define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
|
| 775 | #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
|
| 776 | #define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
|
| 777 | #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
|
| 778 | #define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
|
| 779 | #define SERCOM_USART_INTENCLR_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
|
| 780 |
|
| 781 | /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
|
| 782 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 783 | typedef union {
|
| 784 | struct {
|
| 785 | uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
|
| 786 | uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
|
| 787 | uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
| 788 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
|
| 789 | } bit; /*!< Structure used for bit access */
|
| 790 | uint8_t reg; /*!< Type used for register access */
|
| 791 | } SERCOM_I2CM_INTENSET_Type;
|
| 792 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 793 |
|
| 794 | #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
|
| 795 | #define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
|
| 796 |
|
| 797 | #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
|
| 798 | #define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
|
| 799 | #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
|
| 800 | #define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
|
| 801 | #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
|
| 802 | #define SERCOM_I2CM_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
|
| 803 | #define SERCOM_I2CM_INTENSET_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
|
| 804 |
|
| 805 | /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
|
| 806 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 807 | typedef union {
|
| 808 | struct {
|
| 809 | uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
|
| 810 | uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
|
| 811 | uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
|
| 812 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
| 813 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
|
| 814 | } bit; /*!< Structure used for bit access */
|
| 815 | uint8_t reg; /*!< Type used for register access */
|
| 816 | } SERCOM_I2CS_INTENSET_Type;
|
| 817 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 818 |
|
| 819 | #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
|
| 820 | #define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
|
| 821 |
|
| 822 | #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
|
| 823 | #define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
|
| 824 | #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
|
| 825 | #define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
|
| 826 | #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
|
| 827 | #define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
|
| 828 | #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
|
| 829 | #define SERCOM_I2CS_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
|
| 830 | #define SERCOM_I2CS_INTENSET_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
|
| 831 |
|
| 832 | /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
|
| 833 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 834 | typedef union {
|
| 835 | struct {
|
| 836 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
|
| 837 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
|
| 838 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
|
| 839 | uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
|
| 840 | uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
| 841 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
|
| 842 | } bit; /*!< Structure used for bit access */
|
| 843 | uint8_t reg; /*!< Type used for register access */
|
| 844 | } SERCOM_SPI_INTENSET_Type;
|
| 845 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 846 |
|
| 847 | #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
|
| 848 | #define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
|
| 849 |
|
| 850 | #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
|
| 851 | #define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
|
| 852 | #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
|
| 853 | #define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
|
| 854 | #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
|
| 855 | #define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
|
| 856 | #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
|
| 857 | #define SERCOM_SPI_INTENSET_SSL (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
|
| 858 | #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
|
| 859 | #define SERCOM_SPI_INTENSET_ERROR (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
|
| 860 | #define SERCOM_SPI_INTENSET_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
|
| 861 |
|
| 862 | /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
|
| 863 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 864 | typedef union {
|
| 865 | struct {
|
| 866 | uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
|
| 867 | uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
|
| 868 | uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
|
| 869 | uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
|
| 870 | uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
|
| 871 | uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
|
| 872 | uint8_t :1; /*!< bit: 6 Reserved */
|
| 873 | uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
|
| 874 | } bit; /*!< Structure used for bit access */
|
| 875 | uint8_t reg; /*!< Type used for register access */
|
| 876 | } SERCOM_USART_INTENSET_Type;
|
| 877 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 878 |
|
| 879 | #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
|
| 880 | #define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
|
| 881 |
|
| 882 | #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
|
| 883 | #define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
|
| 884 | #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
|
| 885 | #define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
|
| 886 | #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
|
| 887 | #define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
|
| 888 | #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
|
| 889 | #define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
|
| 890 | #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
|
| 891 | #define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
|
| 892 | #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
|
| 893 | #define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
|
| 894 | #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
|
| 895 | #define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
|
| 896 | #define SERCOM_USART_INTENSET_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */
|
| 897 |
|
| 898 | /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
|
| 899 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 900 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 901 | struct {
|
| 902 | __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
|
| 903 | __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
|
| 904 | __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
| 905 | __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
| 906 | } bit; /*!< Structure used for bit access */
|
| 907 | uint8_t reg; /*!< Type used for register access */
|
| 908 | } SERCOM_I2CM_INTFLAG_Type;
|
| 909 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 910 |
|
| 911 | #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
|
| 912 | #define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
|
| 913 |
|
| 914 | #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
|
| 915 | #define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
|
| 916 | #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
|
| 917 | #define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
|
| 918 | #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
|
| 919 | #define SERCOM_I2CM_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
|
| 920 | #define SERCOM_I2CM_INTFLAG_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
|
| 921 |
|
| 922 | /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
|
| 923 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 924 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 925 | struct {
|
| 926 | __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
|
| 927 | __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
|
| 928 | __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
|
| 929 | __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
| 930 | __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
| 931 | } bit; /*!< Structure used for bit access */
|
| 932 | uint8_t reg; /*!< Type used for register access */
|
| 933 | } SERCOM_I2CS_INTFLAG_Type;
|
| 934 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 935 |
|
| 936 | #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
|
| 937 | #define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
|
| 938 |
|
| 939 | #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
|
| 940 | #define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
|
| 941 | #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
|
| 942 | #define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
|
| 943 | #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
|
| 944 | #define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
|
| 945 | #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
|
| 946 | #define SERCOM_I2CS_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
|
| 947 | #define SERCOM_I2CS_INTFLAG_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
|
| 948 |
|
| 949 | /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
|
| 950 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 951 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 952 | struct {
|
| 953 | __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
| 954 | __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
| 955 | __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
| 956 | __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
|
| 957 | __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
| 958 | __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
| 959 | } bit; /*!< Structure used for bit access */
|
| 960 | uint8_t reg; /*!< Type used for register access */
|
| 961 | } SERCOM_SPI_INTFLAG_Type;
|
| 962 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 963 |
|
| 964 | #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
|
| 965 | #define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
|
| 966 |
|
| 967 | #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
|
| 968 | #define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
|
| 969 | #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
|
| 970 | #define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
|
| 971 | #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
|
| 972 | #define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
|
| 973 | #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
|
| 974 | #define SERCOM_SPI_INTFLAG_SSL (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
|
| 975 | #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
|
| 976 | #define SERCOM_SPI_INTFLAG_ERROR (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
|
| 977 | #define SERCOM_SPI_INTFLAG_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
|
| 978 |
|
| 979 | /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
|
| 980 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 981 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 982 | struct {
|
| 983 | __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
| 984 | __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
| 985 | __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
| 986 | __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
|
| 987 | __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
|
| 988 | __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
|
| 989 | __I uint8_t :1; /*!< bit: 6 Reserved */
|
| 990 | __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
| 991 | } bit; /*!< Structure used for bit access */
|
| 992 | uint8_t reg; /*!< Type used for register access */
|
| 993 | } SERCOM_USART_INTFLAG_Type;
|
| 994 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 995 |
|
| 996 | #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
|
| 997 | #define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
|
| 998 |
|
| 999 | #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
|
| 1000 | #define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
|
| 1001 | #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
|
| 1002 | #define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
|
| 1003 | #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
|
| 1004 | #define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
|
| 1005 | #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
|
| 1006 | #define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
|
| 1007 | #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
|
| 1008 | #define SERCOM_USART_INTFLAG_CTSIC (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
|
| 1009 | #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
|
| 1010 | #define SERCOM_USART_INTFLAG_RXBRK (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
|
| 1011 | #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
|
| 1012 | #define SERCOM_USART_INTFLAG_ERROR (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
|
| 1013 | #define SERCOM_USART_INTFLAG_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
|
| 1014 |
|
| 1015 | /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
|
| 1016 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1017 | typedef union {
|
| 1018 | struct {
|
| 1019 | uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
|
| 1020 | uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
|
| 1021 | uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
|
| 1022 | uint16_t :1; /*!< bit: 3 Reserved */
|
| 1023 | uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
|
| 1024 | uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
|
| 1025 | uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
|
| 1026 | uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
|
| 1027 | uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
|
| 1028 | uint16_t LENERR:1; /*!< bit: 10 Length Error */
|
| 1029 | uint16_t :5; /*!< bit: 11..15 Reserved */
|
| 1030 | } bit; /*!< Structure used for bit access */
|
| 1031 | uint16_t reg; /*!< Type used for register access */
|
| 1032 | } SERCOM_I2CM_STATUS_Type;
|
| 1033 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1034 |
|
| 1035 | #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
|
| 1036 | #define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
|
| 1037 |
|
| 1038 | #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
|
| 1039 | #define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
|
| 1040 | #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
|
| 1041 | #define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
|
| 1042 | #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
|
| 1043 | #define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
|
| 1044 | #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
|
| 1045 | #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
|
| 1046 | #define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
|
| 1047 | #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
|
| 1048 | #define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
|
| 1049 | #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
|
| 1050 | #define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
|
| 1051 | #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
|
| 1052 | #define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
|
| 1053 | #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
|
| 1054 | #define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
|
| 1055 | #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
|
| 1056 | #define SERCOM_I2CM_STATUS_LENERR (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
|
| 1057 | #define SERCOM_I2CM_STATUS_MASK _U_(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
|
| 1058 |
|
| 1059 | /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
|
| 1060 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1061 | typedef union {
|
| 1062 | struct {
|
| 1063 | uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
|
| 1064 | uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
|
| 1065 | uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
|
| 1066 | uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
|
| 1067 | uint16_t SR:1; /*!< bit: 4 Repeated Start */
|
| 1068 | uint16_t :1; /*!< bit: 5 Reserved */
|
| 1069 | uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
|
| 1070 | uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
|
| 1071 | uint16_t :1; /*!< bit: 8 Reserved */
|
| 1072 | uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
|
| 1073 | uint16_t HS:1; /*!< bit: 10 High Speed */
|
| 1074 | uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
|
| 1075 | uint16_t :4; /*!< bit: 12..15 Reserved */
|
| 1076 | } bit; /*!< Structure used for bit access */
|
| 1077 | uint16_t reg; /*!< Type used for register access */
|
| 1078 | } SERCOM_I2CS_STATUS_Type;
|
| 1079 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1080 |
|
| 1081 | #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
|
| 1082 | #define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
|
| 1083 |
|
| 1084 | #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
|
| 1085 | #define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
|
| 1086 | #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
|
| 1087 | #define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
|
| 1088 | #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
|
| 1089 | #define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
|
| 1090 | #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
|
| 1091 | #define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
|
| 1092 | #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
|
| 1093 | #define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
|
| 1094 | #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
|
| 1095 | #define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
|
| 1096 | #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
|
| 1097 | #define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
|
| 1098 | #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
|
| 1099 | #define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
|
| 1100 | #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
|
| 1101 | #define SERCOM_I2CS_STATUS_HS (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
|
| 1102 | #define SERCOM_I2CS_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_I2CS_STATUS) Transaction Length Error */
|
| 1103 | #define SERCOM_I2CS_STATUS_LENERR (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)
|
| 1104 | #define SERCOM_I2CS_STATUS_MASK _U_(0x0EDF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
|
| 1105 |
|
| 1106 | /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
|
| 1107 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1108 | typedef union {
|
| 1109 | struct {
|
| 1110 | uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
| 1111 | uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
|
| 1112 | uint16_t :8; /*!< bit: 3..10 Reserved */
|
| 1113 | uint16_t LENERR:1; /*!< bit: 11 Transaction Length Error */
|
| 1114 | uint16_t :4; /*!< bit: 12..15 Reserved */
|
| 1115 | } bit; /*!< Structure used for bit access */
|
| 1116 | uint16_t reg; /*!< Type used for register access */
|
| 1117 | } SERCOM_SPI_STATUS_Type;
|
| 1118 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1119 |
|
| 1120 | #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
|
| 1121 | #define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
|
| 1122 |
|
| 1123 | #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
|
| 1124 | #define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
|
| 1125 | #define SERCOM_SPI_STATUS_LENERR_Pos 11 /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
|
| 1126 | #define SERCOM_SPI_STATUS_LENERR (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
|
| 1127 | #define SERCOM_SPI_STATUS_MASK _U_(0x0804) /**< \brief (SERCOM_SPI_STATUS) MASK Register */
|
| 1128 |
|
| 1129 | /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
|
| 1130 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1131 | typedef union {
|
| 1132 | struct {
|
| 1133 | uint16_t PERR:1; /*!< bit: 0 Parity Error */
|
| 1134 | uint16_t FERR:1; /*!< bit: 1 Frame Error */
|
| 1135 | uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
|
| 1136 | uint16_t CTS:1; /*!< bit: 3 Clear To Send */
|
| 1137 | uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
|
| 1138 | uint16_t COLL:1; /*!< bit: 5 Collision Detected */
|
| 1139 | uint16_t TXE:1; /*!< bit: 6 Transmitter Empty */
|
| 1140 | uint16_t ITER:1; /*!< bit: 7 Maximum Number of Repetitions Reached */
|
| 1141 | uint16_t :8; /*!< bit: 8..15 Reserved */
|
| 1142 | } bit; /*!< Structure used for bit access */
|
| 1143 | uint16_t reg; /*!< Type used for register access */
|
| 1144 | } SERCOM_USART_STATUS_Type;
|
| 1145 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1146 |
|
| 1147 | #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
|
| 1148 | #define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
|
| 1149 |
|
| 1150 | #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
|
| 1151 | #define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
|
| 1152 | #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
|
| 1153 | #define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
|
| 1154 | #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
|
| 1155 | #define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
|
| 1156 | #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
|
| 1157 | #define SERCOM_USART_STATUS_CTS (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
|
| 1158 | #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
|
| 1159 | #define SERCOM_USART_STATUS_ISF (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
|
| 1160 | #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
|
| 1161 | #define SERCOM_USART_STATUS_COLL (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
|
| 1162 | #define SERCOM_USART_STATUS_TXE_Pos 6 /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
|
| 1163 | #define SERCOM_USART_STATUS_TXE (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
|
| 1164 | #define SERCOM_USART_STATUS_ITER_Pos 7 /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
|
| 1165 | #define SERCOM_USART_STATUS_ITER (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
|
| 1166 | #define SERCOM_USART_STATUS_MASK _U_(0x00FF) /**< \brief (SERCOM_USART_STATUS) MASK Register */
|
| 1167 |
|
| 1168 | /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */
|
| 1169 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1170 | typedef union {
|
| 1171 | struct {
|
| 1172 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
| 1173 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
|
| 1174 | uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
|
| 1175 | uint32_t :1; /*!< bit: 3 Reserved */
|
| 1176 | uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
|
| 1177 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 1178 | } bit; /*!< Structure used for bit access */
|
| 1179 | uint32_t reg; /*!< Type used for register access */
|
| 1180 | } SERCOM_I2CM_SYNCBUSY_Type;
|
| 1181 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1182 |
|
| 1183 | #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
|
| 1184 | #define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
|
| 1185 |
|
| 1186 | #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
|
| 1187 | #define SERCOM_I2CM_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
|
| 1188 | #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
|
| 1189 | #define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
|
| 1190 | #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
|
| 1191 | #define SERCOM_I2CM_SYNCBUSY_SYSOP (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
|
| 1192 | #define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy */
|
| 1193 | #define SERCOM_I2CM_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)
|
| 1194 | #define SERCOM_I2CM_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
|
| 1195 |
|
| 1196 | /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */
|
| 1197 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1198 | typedef union {
|
| 1199 | struct {
|
| 1200 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
| 1201 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
|
| 1202 | uint32_t :2; /*!< bit: 2.. 3 Reserved */
|
| 1203 | uint32_t LENGTH:1; /*!< bit: 4 Length Synchronization Busy */
|
| 1204 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 1205 | } bit; /*!< Structure used for bit access */
|
| 1206 | uint32_t reg; /*!< Type used for register access */
|
| 1207 | } SERCOM_I2CS_SYNCBUSY_Type;
|
| 1208 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1209 |
|
| 1210 | #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
|
| 1211 | #define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
|
| 1212 |
|
| 1213 | #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
|
| 1214 | #define SERCOM_I2CS_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
|
| 1215 | #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
|
| 1216 | #define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
|
| 1217 | #define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy */
|
| 1218 | #define SERCOM_I2CS_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)
|
| 1219 | #define SERCOM_I2CS_SYNCBUSY_MASK _U_(0x00000013) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
|
| 1220 |
|
| 1221 | /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */
|
| 1222 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1223 | typedef union {
|
| 1224 | struct {
|
| 1225 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
| 1226 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
|
| 1227 | uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
|
| 1228 | uint32_t :1; /*!< bit: 3 Reserved */
|
| 1229 | uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
|
| 1230 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 1231 | } bit; /*!< Structure used for bit access */
|
| 1232 | uint32_t reg; /*!< Type used for register access */
|
| 1233 | } SERCOM_SPI_SYNCBUSY_Type;
|
| 1234 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1235 |
|
| 1236 | #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
|
| 1237 | #define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
|
| 1238 |
|
| 1239 | #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
|
| 1240 | #define SERCOM_SPI_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
|
| 1241 | #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
|
| 1242 | #define SERCOM_SPI_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
|
| 1243 | #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
|
| 1244 | #define SERCOM_SPI_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
|
| 1245 | #define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
|
| 1246 | #define SERCOM_SPI_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
|
| 1247 | #define SERCOM_SPI_SYNCBUSY_MASK _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
|
| 1248 |
|
| 1249 | /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */
|
| 1250 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1251 | typedef union {
|
| 1252 | struct {
|
| 1253 | uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
| 1254 | uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
|
| 1255 | uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
|
| 1256 | uint32_t RXERRCNT:1; /*!< bit: 3 RXERRCNT Synchronization Busy */
|
| 1257 | uint32_t LENGTH:1; /*!< bit: 4 LENGTH Synchronization Busy */
|
| 1258 | uint32_t :27; /*!< bit: 5..31 Reserved */
|
| 1259 | } bit; /*!< Structure used for bit access */
|
| 1260 | uint32_t reg; /*!< Type used for register access */
|
| 1261 | } SERCOM_USART_SYNCBUSY_Type;
|
| 1262 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1263 |
|
| 1264 | #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
|
| 1265 | #define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
|
| 1266 |
|
| 1267 | #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
|
| 1268 | #define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
|
| 1269 | #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
|
| 1270 | #define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
|
| 1271 | #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
|
| 1272 | #define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
|
| 1273 | #define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3 /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
|
| 1274 | #define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
|
| 1275 | #define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4 /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
|
| 1276 | #define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
|
| 1277 | #define SERCOM_USART_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
|
| 1278 |
|
| 1279 | /* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/ 8) USART USART Receive Error Count -------- */
|
| 1280 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1281 | typedef union {
|
| 1282 | uint8_t reg; /*!< Type used for register access */
|
| 1283 | } SERCOM_USART_RXERRCNT_Type;
|
| 1284 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1285 |
|
| 1286 | #define SERCOM_USART_RXERRCNT_OFFSET 0x20 /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
|
| 1287 | #define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
|
| 1288 | #define SERCOM_USART_RXERRCNT_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
|
| 1289 |
|
| 1290 | /* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS I2CS Length -------- */
|
| 1291 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1292 | typedef union {
|
| 1293 | struct {
|
| 1294 | uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
|
| 1295 | uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
|
| 1296 | uint16_t :7; /*!< bit: 9..15 Reserved */
|
| 1297 | } bit; /*!< Structure used for bit access */
|
| 1298 | uint16_t reg; /*!< Type used for register access */
|
| 1299 | } SERCOM_I2CS_LENGTH_Type;
|
| 1300 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1301 |
|
| 1302 | #define SERCOM_I2CS_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_I2CS_LENGTH offset) I2CS Length */
|
| 1303 | #define SERCOM_I2CS_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_LENGTH reset_value) I2CS Length */
|
| 1304 |
|
| 1305 | #define SERCOM_I2CS_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_I2CS_LENGTH) Data Length */
|
| 1306 | #define SERCOM_I2CS_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)
|
| 1307 | #define SERCOM_I2CS_LENGTH_LEN(value) (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
|
| 1308 | #define SERCOM_I2CS_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_I2CS_LENGTH) Data Length Enable */
|
| 1309 | #define SERCOM_I2CS_LENGTH_LENEN (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)
|
| 1310 | #define SERCOM_I2CS_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_I2CS_LENGTH) MASK Register */
|
| 1311 |
|
| 1312 | /* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
|
| 1313 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1314 | typedef union {
|
| 1315 | struct {
|
| 1316 | uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
|
| 1317 | uint16_t LENEN:1; /*!< bit: 8 Data Length Enable */
|
| 1318 | uint16_t :7; /*!< bit: 9..15 Reserved */
|
| 1319 | } bit; /*!< Structure used for bit access */
|
| 1320 | uint16_t reg; /*!< Type used for register access */
|
| 1321 | } SERCOM_SPI_LENGTH_Type;
|
| 1322 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1323 |
|
| 1324 | #define SERCOM_SPI_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
|
| 1325 | #define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
|
| 1326 |
|
| 1327 | #define SERCOM_SPI_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_SPI_LENGTH) Data Length */
|
| 1328 | #define SERCOM_SPI_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
|
| 1329 | #define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
|
| 1330 | #define SERCOM_SPI_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
|
| 1331 | #define SERCOM_SPI_LENGTH_LENEN (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
|
| 1332 | #define SERCOM_SPI_LENGTH_MASK _U_(0x01FF) /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
|
| 1333 |
|
| 1334 | /* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
|
| 1335 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1336 | typedef union {
|
| 1337 | struct {
|
| 1338 | uint16_t LEN:8; /*!< bit: 0.. 7 Data Length */
|
| 1339 | uint16_t LENEN:2; /*!< bit: 8.. 9 Data Length Enable */
|
| 1340 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 1341 | } bit; /*!< Structure used for bit access */
|
| 1342 | uint16_t reg; /*!< Type used for register access */
|
| 1343 | } SERCOM_USART_LENGTH_Type;
|
| 1344 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1345 |
|
| 1346 | #define SERCOM_USART_LENGTH_OFFSET 0x22 /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
|
| 1347 | #define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
|
| 1348 |
|
| 1349 | #define SERCOM_USART_LENGTH_LEN_Pos 0 /**< \brief (SERCOM_USART_LENGTH) Data Length */
|
| 1350 | #define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
|
| 1351 | #define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
|
| 1352 | #define SERCOM_USART_LENGTH_LENEN_Pos 8 /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
|
| 1353 | #define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
|
| 1354 | #define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
|
| 1355 | #define SERCOM_USART_LENGTH_MASK _U_(0x03FF) /**< \brief (SERCOM_USART_LENGTH) MASK Register */
|
| 1356 |
|
| 1357 | /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
|
| 1358 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1359 | typedef union {
|
| 1360 | struct {
|
| 1361 | uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
|
| 1362 | uint32_t :2; /*!< bit: 11..12 Reserved */
|
| 1363 | uint32_t LENEN:1; /*!< bit: 13 Length Enable */
|
| 1364 | uint32_t HS:1; /*!< bit: 14 High Speed Mode */
|
| 1365 | uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
|
| 1366 | uint32_t LEN:8; /*!< bit: 16..23 Length */
|
| 1367 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 1368 | } bit; /*!< Structure used for bit access */
|
| 1369 | uint32_t reg; /*!< Type used for register access */
|
| 1370 | } SERCOM_I2CM_ADDR_Type;
|
| 1371 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1372 |
|
| 1373 | #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
|
| 1374 | #define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
|
| 1375 |
|
| 1376 | #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
|
| 1377 | #define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
|
| 1378 | #define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
|
| 1379 | #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
|
| 1380 | #define SERCOM_I2CM_ADDR_LENEN (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
|
| 1381 | #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
|
| 1382 | #define SERCOM_I2CM_ADDR_HS (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
|
| 1383 | #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
|
| 1384 | #define SERCOM_I2CM_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
|
| 1385 | #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
|
| 1386 | #define SERCOM_I2CM_ADDR_LEN_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
|
| 1387 | #define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
|
| 1388 | #define SERCOM_I2CM_ADDR_MASK _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
|
| 1389 |
|
| 1390 | /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
|
| 1391 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1392 | typedef union {
|
| 1393 | struct {
|
| 1394 | uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
|
| 1395 | uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
|
| 1396 | uint32_t :4; /*!< bit: 11..14 Reserved */
|
| 1397 | uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
|
| 1398 | uint32_t :1; /*!< bit: 16 Reserved */
|
| 1399 | uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
|
| 1400 | uint32_t :5; /*!< bit: 27..31 Reserved */
|
| 1401 | } bit; /*!< Structure used for bit access */
|
| 1402 | uint32_t reg; /*!< Type used for register access */
|
| 1403 | } SERCOM_I2CS_ADDR_Type;
|
| 1404 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1405 |
|
| 1406 | #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
|
| 1407 | #define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
|
| 1408 |
|
| 1409 | #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
|
| 1410 | #define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
|
| 1411 | #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
|
| 1412 | #define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
|
| 1413 | #define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
|
| 1414 | #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
|
| 1415 | #define SERCOM_I2CS_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
|
| 1416 | #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
|
| 1417 | #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
|
| 1418 | #define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
|
| 1419 | #define SERCOM_I2CS_ADDR_MASK _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
|
| 1420 |
|
| 1421 | /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
|
| 1422 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1423 | typedef union {
|
| 1424 | struct {
|
| 1425 | uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
|
| 1426 | uint32_t :8; /*!< bit: 8..15 Reserved */
|
| 1427 | uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
|
| 1428 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 1429 | } bit; /*!< Structure used for bit access */
|
| 1430 | uint32_t reg; /*!< Type used for register access */
|
| 1431 | } SERCOM_SPI_ADDR_Type;
|
| 1432 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1433 |
|
| 1434 | #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
|
| 1435 | #define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
|
| 1436 |
|
| 1437 | #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
|
| 1438 | #define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
|
| 1439 | #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
|
| 1440 | #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
|
| 1441 | #define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
|
| 1442 | #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
|
| 1443 | #define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
|
| 1444 |
|
| 1445 | /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM I2CM Data -------- */
|
| 1446 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1447 | typedef union {
|
| 1448 | struct {
|
| 1449 | uint32_t DATA:32; /*!< bit: 0..31 Data Value */
|
| 1450 | } bit; /*!< Structure used for bit access */
|
| 1451 | uint32_t reg; /*!< Type used for register access */
|
| 1452 | } SERCOM_I2CM_DATA_Type;
|
| 1453 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1454 |
|
| 1455 | #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
|
| 1456 | #define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
|
| 1457 |
|
| 1458 | #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
|
| 1459 | #define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)
|
| 1460 | #define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
|
| 1461 | #define SERCOM_I2CM_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */
|
| 1462 |
|
| 1463 | /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS I2CS Data -------- */
|
| 1464 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1465 | typedef union {
|
| 1466 | struct {
|
| 1467 | uint32_t DATA:32; /*!< bit: 0..31 Data Value */
|
| 1468 | } bit; /*!< Structure used for bit access */
|
| 1469 | uint32_t reg; /*!< Type used for register access */
|
| 1470 | } SERCOM_I2CS_DATA_Type;
|
| 1471 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1472 |
|
| 1473 | #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
|
| 1474 | #define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
|
| 1475 |
|
| 1476 | #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
|
| 1477 | #define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)
|
| 1478 | #define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
|
| 1479 | #define SERCOM_I2CS_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */
|
| 1480 |
|
| 1481 | /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
|
| 1482 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1483 | typedef union {
|
| 1484 | struct {
|
| 1485 | uint32_t DATA:32; /*!< bit: 0..31 Data Value */
|
| 1486 | } bit; /*!< Structure used for bit access */
|
| 1487 | uint32_t reg; /*!< Type used for register access */
|
| 1488 | } SERCOM_SPI_DATA_Type;
|
| 1489 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1490 |
|
| 1491 | #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
|
| 1492 | #define SERCOM_SPI_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
|
| 1493 |
|
| 1494 | #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
|
| 1495 | #define SERCOM_SPI_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
|
| 1496 | #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
|
| 1497 | #define SERCOM_SPI_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
|
| 1498 |
|
| 1499 | /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
|
| 1500 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1501 | typedef union {
|
| 1502 | struct {
|
| 1503 | uint32_t DATA:32; /*!< bit: 0..31 Data Value */
|
| 1504 | } bit; /*!< Structure used for bit access */
|
| 1505 | uint32_t reg; /*!< Type used for register access */
|
| 1506 | } SERCOM_USART_DATA_Type;
|
| 1507 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1508 |
|
| 1509 | #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
|
| 1510 | #define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
|
| 1511 |
|
| 1512 | #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
|
| 1513 | #define SERCOM_USART_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
|
| 1514 | #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
|
| 1515 | #define SERCOM_USART_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
|
| 1516 |
|
| 1517 | /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
|
| 1518 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1519 | typedef union {
|
| 1520 | struct {
|
| 1521 | uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
|
| 1522 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
| 1523 | } bit; /*!< Structure used for bit access */
|
| 1524 | uint8_t reg; /*!< Type used for register access */
|
| 1525 | } SERCOM_I2CM_DBGCTRL_Type;
|
| 1526 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1527 |
|
| 1528 | #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
|
| 1529 | #define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
|
| 1530 |
|
| 1531 | #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
|
| 1532 | #define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
|
| 1533 | #define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
|
| 1534 |
|
| 1535 | /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
|
| 1536 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1537 | typedef union {
|
| 1538 | struct {
|
| 1539 | uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
|
| 1540 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
| 1541 | } bit; /*!< Structure used for bit access */
|
| 1542 | uint8_t reg; /*!< Type used for register access */
|
| 1543 | } SERCOM_SPI_DBGCTRL_Type;
|
| 1544 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1545 |
|
| 1546 | #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
|
| 1547 | #define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
|
| 1548 |
|
| 1549 | #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
|
| 1550 | #define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
|
| 1551 | #define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
|
| 1552 |
|
| 1553 | /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
|
| 1554 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1555 | typedef union {
|
| 1556 | struct {
|
| 1557 | uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
|
| 1558 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
| 1559 | } bit; /*!< Structure used for bit access */
|
| 1560 | uint8_t reg; /*!< Type used for register access */
|
| 1561 | } SERCOM_USART_DBGCTRL_Type;
|
| 1562 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1563 |
|
| 1564 | #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
|
| 1565 | #define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
|
| 1566 |
|
| 1567 | #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
|
| 1568 | #define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
|
| 1569 | #define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
|
| 1570 |
|
| 1571 | /** \brief SERCOM_I2CM hardware registers */
|
| 1572 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1573 | typedef struct { /* I2C Master Mode */
|
| 1574 | __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
|
| 1575 | __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
|
| 1576 | __IO SERCOM_I2CM_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
|
| 1577 | __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
|
| 1578 | RoReg8 Reserved1[0x4];
|
| 1579 | __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
|
| 1580 | RoReg8 Reserved2[0x1];
|
| 1581 | __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
|
| 1582 | RoReg8 Reserved3[0x1];
|
| 1583 | __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
|
| 1584 | RoReg8 Reserved4[0x1];
|
| 1585 | __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
|
| 1586 | __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */
|
| 1587 | RoReg8 Reserved5[0x4];
|
| 1588 | __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
|
| 1589 | __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
|
| 1590 | RoReg8 Reserved6[0x4];
|
| 1591 | __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
|
| 1592 | } SercomI2cm;
|
| 1593 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1594 |
|
| 1595 | /** \brief SERCOM_I2CS hardware registers */
|
| 1596 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1597 | typedef struct { /* I2C Slave Mode */
|
| 1598 | __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
|
| 1599 | __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
|
| 1600 | __IO SERCOM_I2CS_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
|
| 1601 | RoReg8 Reserved1[0x8];
|
| 1602 | __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
|
| 1603 | RoReg8 Reserved2[0x1];
|
| 1604 | __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
|
| 1605 | RoReg8 Reserved3[0x1];
|
| 1606 | __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
|
| 1607 | RoReg8 Reserved4[0x1];
|
| 1608 | __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
|
| 1609 | __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */
|
| 1610 | RoReg8 Reserved5[0x2];
|
| 1611 | __IO SERCOM_I2CS_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
|
| 1612 | __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
|
| 1613 | __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
|
| 1614 | } SercomI2cs;
|
| 1615 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1616 |
|
| 1617 | /** \brief SERCOM_SPI hardware registers */
|
| 1618 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1619 | typedef struct { /* SPI Mode */
|
| 1620 | __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
|
| 1621 | __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
|
| 1622 | __IO SERCOM_SPI_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
|
| 1623 | __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
|
| 1624 | RoReg8 Reserved1[0x7];
|
| 1625 | __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
|
| 1626 | RoReg8 Reserved2[0x1];
|
| 1627 | __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
|
| 1628 | RoReg8 Reserved3[0x1];
|
| 1629 | __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
|
| 1630 | RoReg8 Reserved4[0x1];
|
| 1631 | __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
|
| 1632 | __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */
|
| 1633 | RoReg8 Reserved5[0x2];
|
| 1634 | __IO SERCOM_SPI_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) SPI Length */
|
| 1635 | __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
|
| 1636 | __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
|
| 1637 | RoReg8 Reserved6[0x4];
|
| 1638 | __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
|
| 1639 | } SercomSpi;
|
| 1640 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1641 |
|
| 1642 | /** \brief SERCOM_USART hardware registers */
|
| 1643 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1644 | typedef struct { /* USART Mode */
|
| 1645 | __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
|
| 1646 | __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
|
| 1647 | __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */
|
| 1648 | __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
|
| 1649 | __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
|
| 1650 | RoReg8 Reserved1[0x5];
|
| 1651 | __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
|
| 1652 | RoReg8 Reserved2[0x1];
|
| 1653 | __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
|
| 1654 | RoReg8 Reserved3[0x1];
|
| 1655 | __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
|
| 1656 | RoReg8 Reserved4[0x1];
|
| 1657 | __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
|
| 1658 | __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */
|
| 1659 | __I SERCOM_USART_RXERRCNT_Type RXERRCNT; /**< \brief Offset: 0x20 (R/ 8) USART Receive Error Count */
|
| 1660 | RoReg8 Reserved5[0x1];
|
| 1661 | __IO SERCOM_USART_LENGTH_Type LENGTH; /**< \brief Offset: 0x22 (R/W 16) USART Length */
|
| 1662 | RoReg8 Reserved6[0x4];
|
| 1663 | __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) USART Data */
|
| 1664 | RoReg8 Reserved7[0x4];
|
| 1665 | __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
|
| 1666 | } SercomUsart;
|
| 1667 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1668 |
|
| 1669 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 1670 | typedef union {
|
| 1671 | SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
|
| 1672 | SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
|
| 1673 | SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
|
| 1674 | SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
|
| 1675 | } Sercom;
|
| 1676 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 1677 |
|
| 1678 | /*@}*/
|
| 1679 |
|
| 1680 | #endif /* _SAME54_SERCOM_COMPONENT_ */
|