Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for PORT |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_PORT_COMPONENT_ |
| 31 | #define _SAME54_PORT_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR PORT */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_PORT Port Module */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define PORT_U2210 |
| 40 | #define REV_PORT 0x220 |
| 41 | |
| 42 | /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ |
| 47 | } bit; /*!< Structure used for bit access */ |
| 48 | uint32_t reg; /*!< Type used for register access */ |
| 49 | } PORT_DIR_Type; |
| 50 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 51 | |
| 52 | #define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ |
| 53 | #define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */ |
| 54 | |
| 55 | #define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */ |
| 56 | #define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos) |
| 57 | #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)) |
| 58 | #define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */ |
| 59 | |
| 60 | /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ |
| 61 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 62 | typedef union { |
| 63 | struct { |
| 64 | uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ |
| 65 | } bit; /*!< Structure used for bit access */ |
| 66 | uint32_t reg; /*!< Type used for register access */ |
| 67 | } PORT_DIRCLR_Type; |
| 68 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 69 | |
| 70 | #define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ |
| 71 | #define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ |
| 72 | |
| 73 | #define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */ |
| 74 | #define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) |
| 75 | #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)) |
| 76 | #define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */ |
| 77 | |
| 78 | /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ |
| 79 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 80 | typedef union { |
| 81 | struct { |
| 82 | uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ |
| 83 | } bit; /*!< Structure used for bit access */ |
| 84 | uint32_t reg; /*!< Type used for register access */ |
| 85 | } PORT_DIRSET_Type; |
| 86 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 87 | |
| 88 | #define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ |
| 89 | #define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ |
| 90 | |
| 91 | #define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */ |
| 92 | #define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) |
| 93 | #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)) |
| 94 | #define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */ |
| 95 | |
| 96 | /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ |
| 97 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 98 | typedef union { |
| 99 | struct { |
| 100 | uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ |
| 101 | } bit; /*!< Structure used for bit access */ |
| 102 | uint32_t reg; /*!< Type used for register access */ |
| 103 | } PORT_DIRTGL_Type; |
| 104 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 105 | |
| 106 | #define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ |
| 107 | #define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ |
| 108 | |
| 109 | #define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */ |
| 110 | #define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) |
| 111 | #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)) |
| 112 | #define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */ |
| 113 | |
| 114 | /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ |
| 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 116 | typedef union { |
| 117 | struct { |
| 118 | uint32_t OUT:32; /*!< bit: 0..31 PORT Data Output Value */ |
| 119 | } bit; /*!< Structure used for bit access */ |
| 120 | uint32_t reg; /*!< Type used for register access */ |
| 121 | } PORT_OUT_Type; |
| 122 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 123 | |
| 124 | #define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ |
| 125 | #define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */ |
| 126 | |
| 127 | #define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) PORT Data Output Value */ |
| 128 | #define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos) |
| 129 | #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)) |
| 130 | #define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */ |
| 131 | |
| 132 | /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ |
| 133 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 134 | typedef union { |
| 135 | struct { |
| 136 | uint32_t OUTCLR:32; /*!< bit: 0..31 PORT Data Output Value Clear */ |
| 137 | } bit; /*!< Structure used for bit access */ |
| 138 | uint32_t reg; /*!< Type used for register access */ |
| 139 | } PORT_OUTCLR_Type; |
| 140 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 141 | |
| 142 | #define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ |
| 143 | #define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ |
| 144 | |
| 145 | #define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */ |
| 146 | #define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) |
| 147 | #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)) |
| 148 | #define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */ |
| 149 | |
| 150 | /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ |
| 151 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 152 | typedef union { |
| 153 | struct { |
| 154 | uint32_t OUTSET:32; /*!< bit: 0..31 PORT Data Output Value Set */ |
| 155 | } bit; /*!< Structure used for bit access */ |
| 156 | uint32_t reg; /*!< Type used for register access */ |
| 157 | } PORT_OUTSET_Type; |
| 158 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 159 | |
| 160 | #define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ |
| 161 | #define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ |
| 162 | |
| 163 | #define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) PORT Data Output Value Set */ |
| 164 | #define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) |
| 165 | #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)) |
| 166 | #define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */ |
| 167 | |
| 168 | /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ |
| 169 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 170 | typedef union { |
| 171 | struct { |
| 172 | uint32_t OUTTGL:32; /*!< bit: 0..31 PORT Data Output Value Toggle */ |
| 173 | } bit; /*!< Structure used for bit access */ |
| 174 | uint32_t reg; /*!< Type used for register access */ |
| 175 | } PORT_OUTTGL_Type; |
| 176 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 177 | |
| 178 | #define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ |
| 179 | #define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ |
| 180 | |
| 181 | #define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */ |
| 182 | #define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) |
| 183 | #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)) |
| 184 | #define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */ |
| 185 | |
| 186 | /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ |
| 187 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 188 | typedef union { |
| 189 | struct { |
| 190 | uint32_t IN:32; /*!< bit: 0..31 PORT Data Input Value */ |
| 191 | } bit; /*!< Structure used for bit access */ |
| 192 | uint32_t reg; /*!< Type used for register access */ |
| 193 | } PORT_IN_Type; |
| 194 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 195 | |
| 196 | #define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ |
| 197 | #define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */ |
| 198 | |
| 199 | #define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) PORT Data Input Value */ |
| 200 | #define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos) |
| 201 | #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)) |
| 202 | #define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */ |
| 203 | |
| 204 | /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ |
| 205 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 206 | typedef union { |
| 207 | struct { |
| 208 | uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ |
| 209 | } bit; /*!< Structure used for bit access */ |
| 210 | uint32_t reg; /*!< Type used for register access */ |
| 211 | } PORT_CTRL_Type; |
| 212 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 213 | |
| 214 | #define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ |
| 215 | #define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */ |
| 216 | |
| 217 | #define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ |
| 218 | #define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) |
| 219 | #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)) |
| 220 | #define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */ |
| 221 | |
| 222 | /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ |
| 223 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 224 | typedef union { |
| 225 | struct { |
| 226 | uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ |
| 227 | uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ |
| 228 | uint32_t INEN:1; /*!< bit: 17 Input Enable */ |
| 229 | uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ |
| 230 | uint32_t :3; /*!< bit: 19..21 Reserved */ |
| 231 | uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ |
| 232 | uint32_t :1; /*!< bit: 23 Reserved */ |
| 233 | uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ |
| 234 | uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ |
| 235 | uint32_t :1; /*!< bit: 29 Reserved */ |
| 236 | uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ |
| 237 | uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ |
| 238 | } bit; /*!< Structure used for bit access */ |
| 239 | uint32_t reg; /*!< Type used for register access */ |
| 240 | } PORT_WRCONFIG_Type; |
| 241 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 242 | |
| 243 | #define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ |
| 244 | #define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ |
| 245 | |
| 246 | #define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ |
| 247 | #define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) |
| 248 | #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)) |
| 249 | #define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */ |
| 250 | #define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) |
| 251 | #define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ |
| 252 | #define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos) |
| 253 | #define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ |
| 254 | #define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos) |
| 255 | #define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ |
| 256 | #define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) |
| 257 | #define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */ |
| 258 | #define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos) |
| 259 | #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)) |
| 260 | #define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */ |
| 261 | #define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) |
| 262 | #define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */ |
| 263 | #define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) |
| 264 | #define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ |
| 265 | #define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos) |
| 266 | #define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */ |
| 267 | |
| 268 | /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */ |
| 269 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 270 | typedef union { |
| 271 | struct { |
| 272 | uint32_t PID0:5; /*!< bit: 0.. 4 PORT Event Pin Identifier 0 */ |
| 273 | uint32_t EVACT0:2; /*!< bit: 5.. 6 PORT Event Action 0 */ |
| 274 | uint32_t PORTEI0:1; /*!< bit: 7 PORT Event Input Enable 0 */ |
| 275 | uint32_t PID1:5; /*!< bit: 8..12 PORT Event Pin Identifier 1 */ |
| 276 | uint32_t EVACT1:2; /*!< bit: 13..14 PORT Event Action 1 */ |
| 277 | uint32_t PORTEI1:1; /*!< bit: 15 PORT Event Input Enable 1 */ |
| 278 | uint32_t PID2:5; /*!< bit: 16..20 PORT Event Pin Identifier 2 */ |
| 279 | uint32_t EVACT2:2; /*!< bit: 21..22 PORT Event Action 2 */ |
| 280 | uint32_t PORTEI2:1; /*!< bit: 23 PORT Event Input Enable 2 */ |
| 281 | uint32_t PID3:5; /*!< bit: 24..28 PORT Event Pin Identifier 3 */ |
| 282 | uint32_t EVACT3:2; /*!< bit: 29..30 PORT Event Action 3 */ |
| 283 | uint32_t PORTEI3:1; /*!< bit: 31 PORT Event Input Enable 3 */ |
| 284 | } bit; /*!< Structure used for bit access */ |
| 285 | uint32_t reg; /*!< Type used for register access */ |
| 286 | } PORT_EVCTRL_Type; |
| 287 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 288 | |
| 289 | #define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */ |
| 290 | #define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */ |
| 291 | |
| 292 | #define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */ |
| 293 | #define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos) |
| 294 | #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos)) |
| 295 | #define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) PORT Event Action 0 */ |
| 296 | #define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos) |
| 297 | #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos)) |
| 298 | #define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */ |
| 299 | #define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */ |
| 300 | #define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */ |
| 301 | #define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */ |
| 302 | #define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) |
| 303 | #define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) |
| 304 | #define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) |
| 305 | #define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) |
| 306 | #define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */ |
| 307 | #define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos) |
| 308 | #define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */ |
| 309 | #define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos) |
| 310 | #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos)) |
| 311 | #define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) PORT Event Action 1 */ |
| 312 | #define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos) |
| 313 | #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos)) |
| 314 | #define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */ |
| 315 | #define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos) |
| 316 | #define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */ |
| 317 | #define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos) |
| 318 | #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos)) |
| 319 | #define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) PORT Event Action 2 */ |
| 320 | #define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos) |
| 321 | #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos)) |
| 322 | #define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */ |
| 323 | #define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos) |
| 324 | #define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */ |
| 325 | #define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos) |
| 326 | #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos)) |
| 327 | #define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) PORT Event Action 3 */ |
| 328 | #define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos) |
| 329 | #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos)) |
| 330 | #define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */ |
| 331 | #define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos) |
| 332 | #define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */ |
| 333 | |
| 334 | /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing -------- */ |
| 335 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 336 | typedef union { |
| 337 | struct { |
| 338 | uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */ |
| 339 | uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */ |
| 340 | } bit; /*!< Structure used for bit access */ |
| 341 | uint8_t reg; /*!< Type used for register access */ |
| 342 | } PORT_PMUX_Type; |
| 343 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 344 | |
| 345 | #define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */ |
| 346 | #define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */ |
| 347 | |
| 348 | #define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */ |
| 349 | #define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos) |
| 350 | #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)) |
| 351 | #define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */ |
| 352 | #define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos) |
| 353 | #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)) |
| 354 | #define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */ |
| 355 | |
| 356 | /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration -------- */ |
| 357 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 358 | typedef union { |
| 359 | struct { |
| 360 | uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ |
| 361 | uint8_t INEN:1; /*!< bit: 1 Input Enable */ |
| 362 | uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ |
| 363 | uint8_t :3; /*!< bit: 3.. 5 Reserved */ |
| 364 | uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ |
| 365 | uint8_t :1; /*!< bit: 7 Reserved */ |
| 366 | } bit; /*!< Structure used for bit access */ |
| 367 | uint8_t reg; /*!< Type used for register access */ |
| 368 | } PORT_PINCFG_Type; |
| 369 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 370 | |
| 371 | #define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration */ |
| 372 | #define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration */ |
| 373 | |
| 374 | #define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */ |
| 375 | #define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos) |
| 376 | #define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ |
| 377 | #define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos) |
| 378 | #define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ |
| 379 | #define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos) |
| 380 | #define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ |
| 381 | #define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos) |
| 382 | #define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */ |
| 383 | |
| 384 | /** \brief PortGroup hardware registers */ |
| 385 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 386 | typedef struct { |
| 387 | __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ |
| 388 | __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ |
| 389 | __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ |
| 390 | __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ |
| 391 | __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ |
| 392 | __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ |
| 393 | __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ |
| 394 | __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ |
| 395 | __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ |
| 396 | __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ |
| 397 | __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ |
| 398 | __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */ |
| 399 | __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing */ |
| 400 | __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration */ |
| 401 | RoReg8 Reserved1[0x20]; |
| 402 | } PortGroup; |
| 403 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 404 | |
| 405 | /** \brief PORT hardware registers */ |
| 406 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 407 | typedef struct { |
| 408 | PortGroup Group[4]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ |
| 409 | } Port; |
| 410 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 411 | |
| 412 | /*@}*/ |
| 413 | |
| 414 | #endif /* _SAME54_PORT_COMPONENT_ */ |