Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for DSU |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_DSU_COMPONENT_ |
| 31 | #define _SAME54_DSU_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR DSU */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_DSU Device Service Unit */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define DSU_U2410 |
| 40 | #define REV_DSU 0x100 |
| 41 | |
| 42 | /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
| 47 | uint8_t :1; /*!< bit: 1 Reserved */ |
| 48 | uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ |
| 49 | uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ |
| 50 | uint8_t CE:1; /*!< bit: 4 Chip-Erase */ |
| 51 | uint8_t :1; /*!< bit: 5 Reserved */ |
| 52 | uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ |
| 53 | uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ |
| 54 | } bit; /*!< Structure used for bit access */ |
| 55 | uint8_t reg; /*!< Type used for register access */ |
| 56 | } DSU_CTRL_Type; |
| 57 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 58 | |
| 59 | #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ |
| 60 | #define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */ |
| 61 | |
| 62 | #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ |
| 63 | #define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos) |
| 64 | #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ |
| 65 | #define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos) |
| 66 | #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ |
| 67 | #define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos) |
| 68 | #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ |
| 69 | #define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos) |
| 70 | #define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ |
| 71 | #define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos) |
| 72 | #define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ |
| 73 | #define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos) |
| 74 | #define DSU_CTRL_MASK _U_(0xDD) /**< \brief (DSU_CTRL) MASK Register */ |
| 75 | |
| 76 | /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ |
| 77 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 78 | typedef union { |
| 79 | struct { |
| 80 | uint8_t DONE:1; /*!< bit: 0 Done */ |
| 81 | uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ |
| 82 | uint8_t BERR:1; /*!< bit: 2 Bus Error */ |
| 83 | uint8_t FAIL:1; /*!< bit: 3 Failure */ |
| 84 | uint8_t PERR:1; /*!< bit: 4 Protection Error */ |
| 85 | uint8_t :3; /*!< bit: 5.. 7 Reserved */ |
| 86 | } bit; /*!< Structure used for bit access */ |
| 87 | uint8_t reg; /*!< Type used for register access */ |
| 88 | } DSU_STATUSA_Type; |
| 89 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 90 | |
| 91 | #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ |
| 92 | #define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */ |
| 93 | |
| 94 | #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ |
| 95 | #define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos) |
| 96 | #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ |
| 97 | #define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos) |
| 98 | #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ |
| 99 | #define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos) |
| 100 | #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ |
| 101 | #define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos) |
| 102 | #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ |
| 103 | #define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos) |
| 104 | #define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */ |
| 105 | |
| 106 | /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ |
| 107 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 108 | typedef union { |
| 109 | struct { |
| 110 | uint8_t PROT:1; /*!< bit: 0 Protected */ |
| 111 | uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ |
| 112 | uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ |
| 113 | uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ |
| 114 | uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ |
| 115 | uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */ |
| 116 | uint8_t TDCCD0:1; /*!< bit: 6 Test Debug Communication Channel 0 Dirty */ |
| 117 | uint8_t TDCCD1:1; /*!< bit: 7 Test Debug Communication Channel 1 Dirty */ |
| 118 | } bit; /*!< Structure used for bit access */ |
| 119 | struct { |
| 120 | uint8_t :2; /*!< bit: 0.. 1 Reserved */ |
| 121 | uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ |
| 122 | uint8_t :2; /*!< bit: 4.. 5 Reserved */ |
| 123 | uint8_t TDCCD:2; /*!< bit: 6.. 7 Test Debug Communication Channel x Dirty */ |
| 124 | } vec; /*!< Structure used for vec access */ |
| 125 | uint8_t reg; /*!< Type used for register access */ |
| 126 | } DSU_STATUSB_Type; |
| 127 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 128 | |
| 129 | #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ |
| 130 | #define DSU_STATUSB_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */ |
| 131 | |
| 132 | #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ |
| 133 | #define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos) |
| 134 | #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ |
| 135 | #define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos) |
| 136 | #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ |
| 137 | #define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos) |
| 138 | #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ |
| 139 | #define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos) |
| 140 | #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ |
| 141 | #define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos) |
| 142 | #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) |
| 143 | #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ |
| 144 | #define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos) |
| 145 | #define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */ |
| 146 | #define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos) |
| 147 | #define DSU_STATUSB_TDCCD0_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */ |
| 148 | #define DSU_STATUSB_TDCCD0 (_U_(1) << DSU_STATUSB_TDCCD0_Pos) |
| 149 | #define DSU_STATUSB_TDCCD1_Pos 7 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */ |
| 150 | #define DSU_STATUSB_TDCCD1 (_U_(1) << DSU_STATUSB_TDCCD1_Pos) |
| 151 | #define DSU_STATUSB_TDCCD_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */ |
| 152 | #define DSU_STATUSB_TDCCD_Msk (_U_(0x3) << DSU_STATUSB_TDCCD_Pos) |
| 153 | #define DSU_STATUSB_TDCCD(value) (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos)) |
| 154 | #define DSU_STATUSB_MASK _U_(0xFF) /**< \brief (DSU_STATUSB) MASK Register */ |
| 155 | |
| 156 | /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ |
| 157 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 158 | typedef union { |
| 159 | struct { |
| 160 | uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ |
| 161 | uint32_t ADDR:30; /*!< bit: 2..31 Address */ |
| 162 | } bit; /*!< Structure used for bit access */ |
| 163 | uint32_t reg; /*!< Type used for register access */ |
| 164 | } DSU_ADDR_Type; |
| 165 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 166 | |
| 167 | #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ |
| 168 | #define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */ |
| 169 | |
| 170 | #define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ |
| 171 | #define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos) |
| 172 | #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)) |
| 173 | #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ |
| 174 | #define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) |
| 175 | #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) |
| 176 | #define DSU_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */ |
| 177 | |
| 178 | /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ |
| 179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 180 | typedef union { |
| 181 | struct { |
| 182 | uint32_t :2; /*!< bit: 0.. 1 Reserved */ |
| 183 | uint32_t LENGTH:30; /*!< bit: 2..31 Length */ |
| 184 | } bit; /*!< Structure used for bit access */ |
| 185 | uint32_t reg; /*!< Type used for register access */ |
| 186 | } DSU_LENGTH_Type; |
| 187 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 188 | |
| 189 | #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ |
| 190 | #define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */ |
| 191 | |
| 192 | #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ |
| 193 | #define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) |
| 194 | #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) |
| 195 | #define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */ |
| 196 | |
| 197 | /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ |
| 198 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 199 | typedef union { |
| 200 | struct { |
| 201 | uint32_t DATA:32; /*!< bit: 0..31 Data */ |
| 202 | } bit; /*!< Structure used for bit access */ |
| 203 | uint32_t reg; /*!< Type used for register access */ |
| 204 | } DSU_DATA_Type; |
| 205 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 206 | |
| 207 | #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ |
| 208 | #define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */ |
| 209 | |
| 210 | #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ |
| 211 | #define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) |
| 212 | #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) |
| 213 | #define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */ |
| 214 | |
| 215 | /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ |
| 216 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 217 | typedef union { |
| 218 | struct { |
| 219 | uint32_t DATA:32; /*!< bit: 0..31 Data */ |
| 220 | } bit; /*!< Structure used for bit access */ |
| 221 | uint32_t reg; /*!< Type used for register access */ |
| 222 | } DSU_DCC_Type; |
| 223 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 224 | |
| 225 | #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ |
| 226 | #define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ |
| 227 | |
| 228 | #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ |
| 229 | #define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) |
| 230 | #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) |
| 231 | #define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */ |
| 232 | |
| 233 | /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ |
| 234 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 235 | typedef union { |
| 236 | struct { |
| 237 | uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ |
| 238 | uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ |
| 239 | uint32_t DIE:4; /*!< bit: 12..15 Die Number */ |
| 240 | uint32_t SERIES:6; /*!< bit: 16..21 Series */ |
| 241 | uint32_t :1; /*!< bit: 22 Reserved */ |
| 242 | uint32_t FAMILY:5; /*!< bit: 23..27 Family */ |
| 243 | uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ |
| 244 | } bit; /*!< Structure used for bit access */ |
| 245 | uint32_t reg; /*!< Type used for register access */ |
| 246 | } DSU_DID_Type; |
| 247 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 248 | |
| 249 | #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ |
| 250 | |
| 251 | #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ |
| 252 | #define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos) |
| 253 | #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) |
| 254 | #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ |
| 255 | #define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos) |
| 256 | #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) |
| 257 | #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ |
| 258 | #define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos) |
| 259 | #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) |
| 260 | #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ |
| 261 | #define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos) |
| 262 | #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) |
| 263 | #define DSU_DID_SERIES_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ |
| 264 | #define DSU_DID_SERIES_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, USB */ |
| 265 | #define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) |
| 266 | #define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) |
| 267 | #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ |
| 268 | #define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos) |
| 269 | #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) |
| 270 | #define DSU_DID_FAMILY_0_Val _U_(0x0) /**< \brief (DSU_DID) General purpose microcontroller */ |
| 271 | #define DSU_DID_FAMILY_1_Val _U_(0x1) /**< \brief (DSU_DID) PicoPower */ |
| 272 | #define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) |
| 273 | #define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) |
| 274 | #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ |
| 275 | #define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos) |
| 276 | #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) |
| 277 | #define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ */ |
| 278 | #define DSU_DID_PROCESSOR_CM23_Val _U_(0x2) /**< \brief (DSU_DID) Cortex-M23 */ |
| 279 | #define DSU_DID_PROCESSOR_CM3_Val _U_(0x3) /**< \brief (DSU_DID) Cortex-M3 */ |
| 280 | #define DSU_DID_PROCESSOR_CM4_Val _U_(0x5) /**< \brief (DSU_DID) Cortex-M4 */ |
| 281 | #define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6) /**< \brief (DSU_DID) Cortex-M4 with FPU */ |
| 282 | #define DSU_DID_PROCESSOR_CM33_Val _U_(0x7) /**< \brief (DSU_DID) Cortex-M33 */ |
| 283 | #define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos) |
| 284 | #define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos) |
| 285 | #define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos) |
| 286 | #define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos) |
| 287 | #define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos) |
| 288 | #define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos) |
| 289 | #define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */ |
| 290 | |
| 291 | /* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */ |
| 292 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 293 | typedef union { |
| 294 | struct { |
| 295 | uint32_t LQOS:2; /*!< bit: 0.. 1 Latency Quality Of Service */ |
| 296 | uint32_t DCCDMALEVEL:2; /*!< bit: 2.. 3 DMA Trigger Level */ |
| 297 | uint32_t ETBRAMEN:1; /*!< bit: 4 Trace Control */ |
| 298 | uint32_t :27; /*!< bit: 5..31 Reserved */ |
| 299 | } bit; /*!< Structure used for bit access */ |
| 300 | uint32_t reg; /*!< Type used for register access */ |
| 301 | } DSU_CFG_Type; |
| 302 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 303 | |
| 304 | #define DSU_CFG_OFFSET 0x001C /**< \brief (DSU_CFG offset) Configuration */ |
| 305 | #define DSU_CFG_RESETVALUE _U_(0x00000002) /**< \brief (DSU_CFG reset_value) Configuration */ |
| 306 | |
| 307 | #define DSU_CFG_LQOS_Pos 0 /**< \brief (DSU_CFG) Latency Quality Of Service */ |
| 308 | #define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos) |
| 309 | #define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos)) |
| 310 | #define DSU_CFG_DCCDMALEVEL_Pos 2 /**< \brief (DSU_CFG) DMA Trigger Level */ |
| 311 | #define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos) |
| 312 | #define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos)) |
| 313 | #define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0) /**< \brief (DSU_CFG) Trigger rises when DCC is empty */ |
| 314 | #define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1) /**< \brief (DSU_CFG) Trigger rises when DCC is full */ |
| 315 | #define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos) |
| 316 | #define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos) |
| 317 | #define DSU_CFG_ETBRAMEN_Pos 4 /**< \brief (DSU_CFG) Trace Control */ |
| 318 | #define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos) |
| 319 | #define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */ |
| 320 | |
| 321 | /* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */ |
| 322 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 323 | typedef union { |
| 324 | struct { |
| 325 | uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */ |
| 326 | } bit; /*!< Structure used for bit access */ |
| 327 | uint32_t reg; /*!< Type used for register access */ |
| 328 | } DSU_DCFG_Type; |
| 329 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 330 | |
| 331 | #define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */ |
| 332 | #define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */ |
| 333 | |
| 334 | #define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */ |
| 335 | #define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos) |
| 336 | #define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos)) |
| 337 | #define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */ |
| 338 | |
| 339 | /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */ |
| 340 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 341 | typedef union { |
| 342 | struct { |
| 343 | uint32_t EPRES:1; /*!< bit: 0 Entry Present */ |
| 344 | uint32_t FMT:1; /*!< bit: 1 Format */ |
| 345 | uint32_t :10; /*!< bit: 2..11 Reserved */ |
| 346 | uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ |
| 347 | } bit; /*!< Structure used for bit access */ |
| 348 | uint32_t reg; /*!< Type used for register access */ |
| 349 | } DSU_ENTRY0_Type; |
| 350 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 351 | |
| 352 | #define DSU_ENTRY0_OFFSET 0x1000 /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */ |
| 353 | #define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */ |
| 354 | |
| 355 | #define DSU_ENTRY0_EPRES_Pos 0 /**< \brief (DSU_ENTRY0) Entry Present */ |
| 356 | #define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos) |
| 357 | #define DSU_ENTRY0_FMT_Pos 1 /**< \brief (DSU_ENTRY0) Format */ |
| 358 | #define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos) |
| 359 | #define DSU_ENTRY0_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY0) Address Offset */ |
| 360 | #define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos) |
| 361 | #define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos)) |
| 362 | #define DSU_ENTRY0_MASK _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */ |
| 363 | |
| 364 | /* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/ 32) CoreSight ROM Table Entry 1 -------- */ |
| 365 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 366 | typedef union { |
| 367 | uint32_t reg; /*!< Type used for register access */ |
| 368 | } DSU_ENTRY1_Type; |
| 369 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 370 | |
| 371 | #define DSU_ENTRY1_OFFSET 0x1004 /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */ |
| 372 | #define DSU_ENTRY1_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */ |
| 373 | #define DSU_ENTRY1_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */ |
| 374 | |
| 375 | /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End -------- */ |
| 376 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 377 | typedef union { |
| 378 | struct { |
| 379 | uint32_t END:32; /*!< bit: 0..31 End Marker */ |
| 380 | } bit; /*!< Structure used for bit access */ |
| 381 | uint32_t reg; /*!< Type used for register access */ |
| 382 | } DSU_END_Type; |
| 383 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 384 | |
| 385 | #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) CoreSight ROM Table End */ |
| 386 | #define DSU_END_RESETVALUE _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */ |
| 387 | |
| 388 | #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ |
| 389 | #define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos) |
| 390 | #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos)) |
| 391 | #define DSU_END_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */ |
| 392 | |
| 393 | /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type -------- */ |
| 394 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 395 | typedef union { |
| 396 | struct { |
| 397 | uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ |
| 398 | uint32_t :31; /*!< bit: 1..31 Reserved */ |
| 399 | } bit; /*!< Structure used for bit access */ |
| 400 | uint32_t reg; /*!< Type used for register access */ |
| 401 | } DSU_MEMTYPE_Type; |
| 402 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 403 | |
| 404 | #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */ |
| 405 | #define DSU_MEMTYPE_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */ |
| 406 | |
| 407 | #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ |
| 408 | #define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos) |
| 409 | #define DSU_MEMTYPE_MASK _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */ |
| 410 | |
| 411 | /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ |
| 412 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 413 | typedef union { |
| 414 | struct { |
| 415 | uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ |
| 416 | uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ |
| 417 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 418 | } bit; /*!< Structure used for bit access */ |
| 419 | uint32_t reg; /*!< Type used for register access */ |
| 420 | } DSU_PID4_Type; |
| 421 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 422 | |
| 423 | #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ |
| 424 | #define DSU_PID4_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ |
| 425 | |
| 426 | #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ |
| 427 | #define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos) |
| 428 | #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)) |
| 429 | #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */ |
| 430 | #define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos) |
| 431 | #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)) |
| 432 | #define DSU_PID4_MASK _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */ |
| 433 | |
| 434 | /* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */ |
| 435 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 436 | typedef union { |
| 437 | uint32_t reg; /*!< Type used for register access */ |
| 438 | } DSU_PID5_Type; |
| 439 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 440 | |
| 441 | #define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */ |
| 442 | #define DSU_PID5_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */ |
| 443 | #define DSU_PID5_MASK _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */ |
| 444 | |
| 445 | /* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */ |
| 446 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 447 | typedef union { |
| 448 | uint32_t reg; /*!< Type used for register access */ |
| 449 | } DSU_PID6_Type; |
| 450 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 451 | |
| 452 | #define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */ |
| 453 | #define DSU_PID6_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */ |
| 454 | #define DSU_PID6_MASK _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */ |
| 455 | |
| 456 | /* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */ |
| 457 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 458 | typedef union { |
| 459 | uint32_t reg; /*!< Type used for register access */ |
| 460 | } DSU_PID7_Type; |
| 461 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 462 | |
| 463 | #define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */ |
| 464 | #define DSU_PID7_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */ |
| 465 | #define DSU_PID7_MASK _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */ |
| 466 | |
| 467 | /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ |
| 468 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 469 | typedef union { |
| 470 | struct { |
| 471 | uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ |
| 472 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 473 | } bit; /*!< Structure used for bit access */ |
| 474 | uint32_t reg; /*!< Type used for register access */ |
| 475 | } DSU_PID0_Type; |
| 476 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 477 | |
| 478 | #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ |
| 479 | #define DSU_PID0_RESETVALUE _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ |
| 480 | |
| 481 | #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ |
| 482 | #define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos) |
| 483 | #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)) |
| 484 | #define DSU_PID0_MASK _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */ |
| 485 | |
| 486 | /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ |
| 487 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 488 | typedef union { |
| 489 | struct { |
| 490 | uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ |
| 491 | uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ |
| 492 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 493 | } bit; /*!< Structure used for bit access */ |
| 494 | uint32_t reg; /*!< Type used for register access */ |
| 495 | } DSU_PID1_Type; |
| 496 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 497 | |
| 498 | #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ |
| 499 | #define DSU_PID1_RESETVALUE _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ |
| 500 | |
| 501 | #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ |
| 502 | #define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos) |
| 503 | #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)) |
| 504 | #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ |
| 505 | #define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos) |
| 506 | #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)) |
| 507 | #define DSU_PID1_MASK _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */ |
| 508 | |
| 509 | /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ |
| 510 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 511 | typedef union { |
| 512 | struct { |
| 513 | uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ |
| 514 | uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ |
| 515 | uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ |
| 516 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 517 | } bit; /*!< Structure used for bit access */ |
| 518 | uint32_t reg; /*!< Type used for register access */ |
| 519 | } DSU_PID2_Type; |
| 520 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 521 | |
| 522 | #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ |
| 523 | #define DSU_PID2_RESETVALUE _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ |
| 524 | |
| 525 | #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ |
| 526 | #define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos) |
| 527 | #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)) |
| 528 | #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ |
| 529 | #define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos) |
| 530 | #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ |
| 531 | #define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos) |
| 532 | #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)) |
| 533 | #define DSU_PID2_MASK _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */ |
| 534 | |
| 535 | /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ |
| 536 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 537 | typedef union { |
| 538 | struct { |
| 539 | uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ |
| 540 | uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ |
| 541 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 542 | } bit; /*!< Structure used for bit access */ |
| 543 | uint32_t reg; /*!< Type used for register access */ |
| 544 | } DSU_PID3_Type; |
| 545 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 546 | |
| 547 | #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ |
| 548 | #define DSU_PID3_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ |
| 549 | |
| 550 | #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ |
| 551 | #define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos) |
| 552 | #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)) |
| 553 | #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ |
| 554 | #define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos) |
| 555 | #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)) |
| 556 | #define DSU_PID3_MASK _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */ |
| 557 | |
| 558 | /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ |
| 559 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 560 | typedef union { |
| 561 | struct { |
| 562 | uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ |
| 563 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 564 | } bit; /*!< Structure used for bit access */ |
| 565 | uint32_t reg; /*!< Type used for register access */ |
| 566 | } DSU_CID0_Type; |
| 567 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 568 | |
| 569 | #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ |
| 570 | #define DSU_CID0_RESETVALUE _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ |
| 571 | |
| 572 | #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ |
| 573 | #define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos) |
| 574 | #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)) |
| 575 | #define DSU_CID0_MASK _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */ |
| 576 | |
| 577 | /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ |
| 578 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 579 | typedef union { |
| 580 | struct { |
| 581 | uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ |
| 582 | uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ |
| 583 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 584 | } bit; /*!< Structure used for bit access */ |
| 585 | uint32_t reg; /*!< Type used for register access */ |
| 586 | } DSU_CID1_Type; |
| 587 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 588 | |
| 589 | #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ |
| 590 | #define DSU_CID1_RESETVALUE _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ |
| 591 | |
| 592 | #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ |
| 593 | #define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos) |
| 594 | #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)) |
| 595 | #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ |
| 596 | #define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos) |
| 597 | #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)) |
| 598 | #define DSU_CID1_MASK _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */ |
| 599 | |
| 600 | /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ |
| 601 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 602 | typedef union { |
| 603 | struct { |
| 604 | uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ |
| 605 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 606 | } bit; /*!< Structure used for bit access */ |
| 607 | uint32_t reg; /*!< Type used for register access */ |
| 608 | } DSU_CID2_Type; |
| 609 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 610 | |
| 611 | #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ |
| 612 | #define DSU_CID2_RESETVALUE _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ |
| 613 | |
| 614 | #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ |
| 615 | #define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos) |
| 616 | #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)) |
| 617 | #define DSU_CID2_MASK _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */ |
| 618 | |
| 619 | /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ |
| 620 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 621 | typedef union { |
| 622 | struct { |
| 623 | uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ |
| 624 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 625 | } bit; /*!< Structure used for bit access */ |
| 626 | uint32_t reg; /*!< Type used for register access */ |
| 627 | } DSU_CID3_Type; |
| 628 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 629 | |
| 630 | #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ |
| 631 | #define DSU_CID3_RESETVALUE _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ |
| 632 | |
| 633 | #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ |
| 634 | #define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos) |
| 635 | #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)) |
| 636 | #define DSU_CID3_MASK _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */ |
| 637 | |
| 638 | /** \brief DSU hardware registers */ |
| 639 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 640 | typedef struct { |
| 641 | __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ |
| 642 | __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ |
| 643 | __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ |
| 644 | RoReg8 Reserved1[0x1]; |
| 645 | __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ |
| 646 | __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ |
| 647 | __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ |
| 648 | __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ |
| 649 | __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ |
| 650 | __IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */ |
| 651 | RoReg8 Reserved2[0xD0]; |
| 652 | __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */ |
| 653 | RoReg8 Reserved3[0xF08]; |
| 654 | __I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */ |
| 655 | __I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */ |
| 656 | __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */ |
| 657 | RoReg8 Reserved4[0xFC0]; |
| 658 | __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */ |
| 659 | __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ |
| 660 | __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ |
| 661 | __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ |
| 662 | __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ |
| 663 | __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ |
| 664 | __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ |
| 665 | __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ |
| 666 | __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ |
| 667 | __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ |
| 668 | __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ |
| 669 | __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ |
| 670 | __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ |
| 671 | } Dsu; |
| 672 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 673 | |
| 674 | /*@}*/ |
| 675 | |
| 676 | #endif /* _SAME54_DSU_COMPONENT_ */ |