Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for CMCC |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_CMCC_COMPONENT_ |
| 31 | #define _SAME54_CMCC_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR CMCC */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_CMCC Cortex M Cache Controller */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define CMCC_U2015 |
| 40 | #define REV_CMCC 0x600 |
| 41 | |
| 42 | /* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 47 | uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ |
| 48 | uint32_t :2; /*!< bit: 2.. 3 Reserved */ |
| 49 | uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ |
| 50 | uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ |
| 51 | uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ |
| 52 | uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ |
| 53 | uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ |
| 54 | uint32_t :18; /*!< bit: 14..31 Reserved */ |
| 55 | } bit; /*!< Structure used for bit access */ |
| 56 | uint32_t reg; /*!< Type used for register access */ |
| 57 | } CMCC_TYPE_Type; |
| 58 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 59 | |
| 60 | #define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ |
| 61 | #define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ |
| 62 | |
| 63 | #define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ |
| 64 | #define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) |
| 65 | #define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ |
| 66 | #define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) |
| 67 | #define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ |
| 68 | #define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) |
| 69 | #define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) |
| 70 | #define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ |
| 71 | #define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ |
| 72 | #define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ |
| 73 | #define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) |
| 74 | #define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) |
| 75 | #define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) |
| 76 | #define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ |
| 77 | #define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) |
| 78 | #define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ |
| 79 | #define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) |
| 80 | #define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) |
| 81 | #define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ |
| 82 | #define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ |
| 83 | #define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ |
| 84 | #define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ |
| 85 | #define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ |
| 86 | #define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ |
| 87 | #define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ |
| 88 | #define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 89 | #define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 90 | #define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 91 | #define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 92 | #define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 93 | #define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 94 | #define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) |
| 95 | #define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ |
| 96 | #define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) |
| 97 | #define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) |
| 98 | #define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ |
| 99 | #define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ |
| 100 | #define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ |
| 101 | #define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ |
| 102 | #define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ |
| 103 | #define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ |
| 104 | #define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) |
| 105 | #define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) |
| 106 | #define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) |
| 107 | #define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) |
| 108 | #define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) |
| 109 | #define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) |
| 110 | #define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ |
| 111 | |
| 112 | /* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ |
| 113 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 114 | typedef union { |
| 115 | struct { |
| 116 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 117 | uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ |
| 118 | uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ |
| 119 | uint32_t :1; /*!< bit: 3 Reserved */ |
| 120 | uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ |
| 121 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
| 122 | } bit; /*!< Structure used for bit access */ |
| 123 | uint32_t reg; /*!< Type used for register access */ |
| 124 | } CMCC_CFG_Type; |
| 125 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 126 | |
| 127 | #define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ |
| 128 | #define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ |
| 129 | |
| 130 | #define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ |
| 131 | #define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) |
| 132 | #define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ |
| 133 | #define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) |
| 134 | #define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ |
| 135 | #define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) |
| 136 | #define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) |
| 137 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ |
| 138 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ |
| 139 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ |
| 140 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ |
| 141 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ |
| 142 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ |
| 143 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ |
| 144 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 145 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 146 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 147 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 148 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 149 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 150 | #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) |
| 151 | #define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ |
| 152 | |
| 153 | /* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ |
| 154 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 155 | typedef union { |
| 156 | struct { |
| 157 | uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ |
| 158 | uint32_t :31; /*!< bit: 1..31 Reserved */ |
| 159 | } bit; /*!< Structure used for bit access */ |
| 160 | uint32_t reg; /*!< Type used for register access */ |
| 161 | } CMCC_CTRL_Type; |
| 162 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 163 | |
| 164 | #define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ |
| 165 | #define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ |
| 166 | |
| 167 | #define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ |
| 168 | #define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) |
| 169 | #define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ |
| 170 | |
| 171 | /* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ |
| 172 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 173 | typedef union { |
| 174 | struct { |
| 175 | uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ |
| 176 | uint32_t :31; /*!< bit: 1..31 Reserved */ |
| 177 | } bit; /*!< Structure used for bit access */ |
| 178 | uint32_t reg; /*!< Type used for register access */ |
| 179 | } CMCC_SR_Type; |
| 180 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 181 | |
| 182 | #define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ |
| 183 | #define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ |
| 184 | |
| 185 | #define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ |
| 186 | #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) |
| 187 | #define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ |
| 188 | |
| 189 | /* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ |
| 190 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 191 | typedef union { |
| 192 | struct { |
| 193 | uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ |
| 194 | uint32_t :28; /*!< bit: 4..31 Reserved */ |
| 195 | } bit; /*!< Structure used for bit access */ |
| 196 | uint32_t reg; /*!< Type used for register access */ |
| 197 | } CMCC_LCKWAY_Type; |
| 198 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 199 | |
| 200 | #define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ |
| 201 | #define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ |
| 202 | |
| 203 | #define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ |
| 204 | #define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) |
| 205 | #define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) |
| 206 | #define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ |
| 207 | |
| 208 | /* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ |
| 209 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 210 | typedef union { |
| 211 | struct { |
| 212 | uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ |
| 213 | uint32_t :31; /*!< bit: 1..31 Reserved */ |
| 214 | } bit; /*!< Structure used for bit access */ |
| 215 | uint32_t reg; /*!< Type used for register access */ |
| 216 | } CMCC_MAINT0_Type; |
| 217 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 218 | |
| 219 | #define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ |
| 220 | #define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ |
| 221 | |
| 222 | #define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ |
| 223 | #define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) |
| 224 | #define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ |
| 225 | |
| 226 | /* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ |
| 227 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 228 | typedef union { |
| 229 | struct { |
| 230 | uint32_t :4; /*!< bit: 0.. 3 Reserved */ |
| 231 | uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ |
| 232 | uint32_t :16; /*!< bit: 12..27 Reserved */ |
| 233 | uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ |
| 234 | } bit; /*!< Structure used for bit access */ |
| 235 | uint32_t reg; /*!< Type used for register access */ |
| 236 | } CMCC_MAINT1_Type; |
| 237 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 238 | |
| 239 | #define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ |
| 240 | #define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ |
| 241 | |
| 242 | #define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ |
| 243 | #define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) |
| 244 | #define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) |
| 245 | #define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ |
| 246 | #define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) |
| 247 | #define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) |
| 248 | #define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ |
| 249 | #define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ |
| 250 | #define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ |
| 251 | #define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ |
| 252 | #define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) |
| 253 | #define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) |
| 254 | #define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) |
| 255 | #define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) |
| 256 | #define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ |
| 257 | |
| 258 | /* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ |
| 259 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 260 | typedef union { |
| 261 | struct { |
| 262 | uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ |
| 263 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| 264 | } bit; /*!< Structure used for bit access */ |
| 265 | uint32_t reg; /*!< Type used for register access */ |
| 266 | } CMCC_MCFG_Type; |
| 267 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 268 | |
| 269 | #define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ |
| 270 | #define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ |
| 271 | |
| 272 | #define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ |
| 273 | #define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) |
| 274 | #define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) |
| 275 | #define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ |
| 276 | #define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ |
| 277 | #define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ |
| 278 | #define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) |
| 279 | #define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) |
| 280 | #define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) |
| 281 | #define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ |
| 282 | |
| 283 | /* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ |
| 284 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 285 | typedef union { |
| 286 | struct { |
| 287 | uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ |
| 288 | uint32_t :31; /*!< bit: 1..31 Reserved */ |
| 289 | } bit; /*!< Structure used for bit access */ |
| 290 | uint32_t reg; /*!< Type used for register access */ |
| 291 | } CMCC_MEN_Type; |
| 292 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 293 | |
| 294 | #define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ |
| 295 | #define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ |
| 296 | |
| 297 | #define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ |
| 298 | #define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) |
| 299 | #define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ |
| 300 | |
| 301 | /* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ |
| 302 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 303 | typedef union { |
| 304 | struct { |
| 305 | uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ |
| 306 | uint32_t :31; /*!< bit: 1..31 Reserved */ |
| 307 | } bit; /*!< Structure used for bit access */ |
| 308 | uint32_t reg; /*!< Type used for register access */ |
| 309 | } CMCC_MCTRL_Type; |
| 310 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 311 | |
| 312 | #define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ |
| 313 | #define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ |
| 314 | |
| 315 | #define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ |
| 316 | #define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) |
| 317 | #define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ |
| 318 | |
| 319 | /* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ |
| 320 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 321 | typedef union { |
| 322 | struct { |
| 323 | uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ |
| 324 | } bit; /*!< Structure used for bit access */ |
| 325 | uint32_t reg; /*!< Type used for register access */ |
| 326 | } CMCC_MSR_Type; |
| 327 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 328 | |
| 329 | #define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ |
| 330 | #define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ |
| 331 | |
| 332 | #define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ |
| 333 | #define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) |
| 334 | #define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) |
| 335 | #define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ |
| 336 | |
| 337 | /** \brief CMCC APB hardware registers */ |
| 338 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 339 | typedef struct { |
| 340 | __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ |
| 341 | __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ |
| 342 | __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ |
| 343 | __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ |
| 344 | __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ |
| 345 | RoReg8 Reserved1[0xC]; |
| 346 | __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ |
| 347 | __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ |
| 348 | __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ |
| 349 | __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ |
| 350 | __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ |
| 351 | __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ |
| 352 | } Cmcc; |
| 353 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 354 | |
| 355 | /*@}*/ |
| 356 | |
| 357 | #endif /* _SAME54_CMCC_COMPONENT_ */ |