| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame^] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for TCC2
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_TCC2_INSTANCE_
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| 31 | #define _SAME54_TCC2_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for TCC2 peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_TCC2_CTRLA (0x42000C00) /**< \brief (TCC2) Control A */
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| 36 | #define REG_TCC2_CTRLBCLR (0x42000C04) /**< \brief (TCC2) Control B Clear */
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| 37 | #define REG_TCC2_CTRLBSET (0x42000C05) /**< \brief (TCC2) Control B Set */
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| 38 | #define REG_TCC2_SYNCBUSY (0x42000C08) /**< \brief (TCC2) Synchronization Busy */
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| 39 | #define REG_TCC2_FCTRLA (0x42000C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
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| 40 | #define REG_TCC2_FCTRLB (0x42000C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
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| 41 | #define REG_TCC2_WEXCTRL (0x42000C14) /**< \brief (TCC2) Waveform Extension Configuration */
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| 42 | #define REG_TCC2_DRVCTRL (0x42000C18) /**< \brief (TCC2) Driver Control */
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| 43 | #define REG_TCC2_DBGCTRL (0x42000C1E) /**< \brief (TCC2) Debug Control */
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| 44 | #define REG_TCC2_EVCTRL (0x42000C20) /**< \brief (TCC2) Event Control */
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| 45 | #define REG_TCC2_INTENCLR (0x42000C24) /**< \brief (TCC2) Interrupt Enable Clear */
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| 46 | #define REG_TCC2_INTENSET (0x42000C28) /**< \brief (TCC2) Interrupt Enable Set */
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| 47 | #define REG_TCC2_INTFLAG (0x42000C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
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| 48 | #define REG_TCC2_STATUS (0x42000C30) /**< \brief (TCC2) Status */
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| 49 | #define REG_TCC2_COUNT (0x42000C34) /**< \brief (TCC2) Count */
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| 50 | #define REG_TCC2_WAVE (0x42000C3C) /**< \brief (TCC2) Waveform Control */
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| 51 | #define REG_TCC2_PER (0x42000C40) /**< \brief (TCC2) Period */
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| 52 | #define REG_TCC2_CC0 (0x42000C44) /**< \brief (TCC2) Compare and Capture 0 */
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| 53 | #define REG_TCC2_CC1 (0x42000C48) /**< \brief (TCC2) Compare and Capture 1 */
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| 54 | #define REG_TCC2_CC2 (0x42000C4C) /**< \brief (TCC2) Compare and Capture 2 */
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| 55 | #define REG_TCC2_PERBUF (0x42000C6C) /**< \brief (TCC2) Period Buffer */
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| 56 | #define REG_TCC2_CCBUF0 (0x42000C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
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| 57 | #define REG_TCC2_CCBUF1 (0x42000C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
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| 58 | #define REG_TCC2_CCBUF2 (0x42000C78) /**< \brief (TCC2) Compare and Capture Buffer 2 */
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| 59 | #else
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| 60 | #define REG_TCC2_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (TCC2) Control A */
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| 61 | #define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42000C04UL) /**< \brief (TCC2) Control B Clear */
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| 62 | #define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42000C05UL) /**< \brief (TCC2) Control B Set */
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| 63 | #define REG_TCC2_SYNCBUSY (*(RoReg *)0x42000C08UL) /**< \brief (TCC2) Synchronization Busy */
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| 64 | #define REG_TCC2_FCTRLA (*(RwReg *)0x42000C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
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| 65 | #define REG_TCC2_FCTRLB (*(RwReg *)0x42000C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
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| 66 | #define REG_TCC2_WEXCTRL (*(RwReg *)0x42000C14UL) /**< \brief (TCC2) Waveform Extension Configuration */
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| 67 | #define REG_TCC2_DRVCTRL (*(RwReg *)0x42000C18UL) /**< \brief (TCC2) Driver Control */
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| 68 | #define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42000C1EUL) /**< \brief (TCC2) Debug Control */
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| 69 | #define REG_TCC2_EVCTRL (*(RwReg *)0x42000C20UL) /**< \brief (TCC2) Event Control */
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| 70 | #define REG_TCC2_INTENCLR (*(RwReg *)0x42000C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
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| 71 | #define REG_TCC2_INTENSET (*(RwReg *)0x42000C28UL) /**< \brief (TCC2) Interrupt Enable Set */
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| 72 | #define REG_TCC2_INTFLAG (*(RwReg *)0x42000C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
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| 73 | #define REG_TCC2_STATUS (*(RwReg *)0x42000C30UL) /**< \brief (TCC2) Status */
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| 74 | #define REG_TCC2_COUNT (*(RwReg *)0x42000C34UL) /**< \brief (TCC2) Count */
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| 75 | #define REG_TCC2_WAVE (*(RwReg *)0x42000C3CUL) /**< \brief (TCC2) Waveform Control */
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| 76 | #define REG_TCC2_PER (*(RwReg *)0x42000C40UL) /**< \brief (TCC2) Period */
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| 77 | #define REG_TCC2_CC0 (*(RwReg *)0x42000C44UL) /**< \brief (TCC2) Compare and Capture 0 */
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| 78 | #define REG_TCC2_CC1 (*(RwReg *)0x42000C48UL) /**< \brief (TCC2) Compare and Capture 1 */
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| 79 | #define REG_TCC2_CC2 (*(RwReg *)0x42000C4CUL) /**< \brief (TCC2) Compare and Capture 2 */
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| 80 | #define REG_TCC2_PERBUF (*(RwReg *)0x42000C6CUL) /**< \brief (TCC2) Period Buffer */
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| 81 | #define REG_TCC2_CCBUF0 (*(RwReg *)0x42000C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
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| 82 | #define REG_TCC2_CCBUF1 (*(RwReg *)0x42000C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
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| 83 | #define REG_TCC2_CCBUF2 (*(RwReg *)0x42000C78UL) /**< \brief (TCC2) Compare and Capture Buffer 2 */
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| 84 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 85 |
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| 86 | /* ========== Instance parameters for TCC2 peripheral ========== */
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| 87 | #define TCC2_CC_NUM 3 // Number of Compare/Capture units
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| 88 | #define TCC2_DITHERING 0 // Dithering feature implemented
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| 89 | #define TCC2_DMAC_ID_MC_0 35
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| 90 | #define TCC2_DMAC_ID_MC_1 36
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| 91 | #define TCC2_DMAC_ID_MC_2 37
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| 92 | #define TCC2_DMAC_ID_MC_LSB 35
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| 93 | #define TCC2_DMAC_ID_MC_MSB 37
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| 94 | #define TCC2_DMAC_ID_MC_SIZE 3
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| 95 | #define TCC2_DMAC_ID_OVF 34 // DMA overflow/underflow/retrigger trigger
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| 96 | #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
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| 97 | #define TCC2_EXT 1 // Coding of implemented extended features
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| 98 | #define TCC2_GCLK_ID 29 // Index of Generic Clock
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| 99 | #define TCC2_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
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| 100 | #define TCC2_OTMX 1 // Output Matrix feature implemented
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| 101 | #define TCC2_OW_NUM 3 // Number of Output Waveforms
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| 102 | #define TCC2_PG 0 // Pattern Generation feature implemented
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| 103 | #define TCC2_SIZE 16
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| 104 | #define TCC2_SWAP 0 // DTI outputs swap feature implemented
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| 105 |
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| 106 | #endif /* _SAME54_TCC2_INSTANCE_ */
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