| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame^] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for SDHC1
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_SDHC1_INSTANCE_
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| 31 | #define _SAME54_SDHC1_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for SDHC1 peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_SDHC1_SSAR (0x46000000) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
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| 36 | #define REG_SDHC1_BSR (0x46000004) /**< \brief (SDHC1) Block Size */
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| 37 | #define REG_SDHC1_BCR (0x46000006) /**< \brief (SDHC1) Block Count */
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| 38 | #define REG_SDHC1_ARG1R (0x46000008) /**< \brief (SDHC1) Argument 1 */
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| 39 | #define REG_SDHC1_TMR (0x4600000C) /**< \brief (SDHC1) Transfer Mode */
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| 40 | #define REG_SDHC1_CR (0x4600000E) /**< \brief (SDHC1) Command */
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| 41 | #define REG_SDHC1_RR0 (0x46000010) /**< \brief (SDHC1) Response 0 */
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| 42 | #define REG_SDHC1_RR1 (0x46000014) /**< \brief (SDHC1) Response 1 */
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| 43 | #define REG_SDHC1_RR2 (0x46000018) /**< \brief (SDHC1) Response 2 */
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| 44 | #define REG_SDHC1_RR3 (0x4600001C) /**< \brief (SDHC1) Response 3 */
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| 45 | #define REG_SDHC1_BDPR (0x46000020) /**< \brief (SDHC1) Buffer Data Port */
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| 46 | #define REG_SDHC1_PSR (0x46000024) /**< \brief (SDHC1) Present State */
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| 47 | #define REG_SDHC1_HC1R (0x46000028) /**< \brief (SDHC1) Host Control 1 */
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| 48 | #define REG_SDHC1_PCR (0x46000029) /**< \brief (SDHC1) Power Control */
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| 49 | #define REG_SDHC1_BGCR (0x4600002A) /**< \brief (SDHC1) Block Gap Control */
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| 50 | #define REG_SDHC1_WCR (0x4600002B) /**< \brief (SDHC1) Wakeup Control */
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| 51 | #define REG_SDHC1_CCR (0x4600002C) /**< \brief (SDHC1) Clock Control */
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| 52 | #define REG_SDHC1_TCR (0x4600002E) /**< \brief (SDHC1) Timeout Control */
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| 53 | #define REG_SDHC1_SRR (0x4600002F) /**< \brief (SDHC1) Software Reset */
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| 54 | #define REG_SDHC1_NISTR (0x46000030) /**< \brief (SDHC1) Normal Interrupt Status */
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| 55 | #define REG_SDHC1_EISTR (0x46000032) /**< \brief (SDHC1) Error Interrupt Status */
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| 56 | #define REG_SDHC1_NISTER (0x46000034) /**< \brief (SDHC1) Normal Interrupt Status Enable */
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| 57 | #define REG_SDHC1_EISTER (0x46000036) /**< \brief (SDHC1) Error Interrupt Status Enable */
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| 58 | #define REG_SDHC1_NISIER (0x46000038) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
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| 59 | #define REG_SDHC1_EISIER (0x4600003A) /**< \brief (SDHC1) Error Interrupt Signal Enable */
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| 60 | #define REG_SDHC1_ACESR (0x4600003C) /**< \brief (SDHC1) Auto CMD Error Status */
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| 61 | #define REG_SDHC1_HC2R (0x4600003E) /**< \brief (SDHC1) Host Control 2 */
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| 62 | #define REG_SDHC1_CA0R (0x46000040) /**< \brief (SDHC1) Capabilities 0 */
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| 63 | #define REG_SDHC1_CA1R (0x46000044) /**< \brief (SDHC1) Capabilities 1 */
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| 64 | #define REG_SDHC1_MCCAR (0x46000048) /**< \brief (SDHC1) Maximum Current Capabilities */
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| 65 | #define REG_SDHC1_FERACES (0x46000050) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
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| 66 | #define REG_SDHC1_FEREIS (0x46000052) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
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| 67 | #define REG_SDHC1_AESR (0x46000054) /**< \brief (SDHC1) ADMA Error Status */
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| 68 | #define REG_SDHC1_ASAR0 (0x46000058) /**< \brief (SDHC1) ADMA System Address 0 */
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| 69 | #define REG_SDHC1_PVR0 (0x46000060) /**< \brief (SDHC1) Preset Value 0 */
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| 70 | #define REG_SDHC1_PVR1 (0x46000062) /**< \brief (SDHC1) Preset Value 1 */
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| 71 | #define REG_SDHC1_PVR2 (0x46000064) /**< \brief (SDHC1) Preset Value 2 */
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| 72 | #define REG_SDHC1_PVR3 (0x46000066) /**< \brief (SDHC1) Preset Value 3 */
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| 73 | #define REG_SDHC1_PVR4 (0x46000068) /**< \brief (SDHC1) Preset Value 4 */
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| 74 | #define REG_SDHC1_PVR5 (0x4600006A) /**< \brief (SDHC1) Preset Value 5 */
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| 75 | #define REG_SDHC1_PVR6 (0x4600006C) /**< \brief (SDHC1) Preset Value 6 */
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| 76 | #define REG_SDHC1_PVR7 (0x4600006E) /**< \brief (SDHC1) Preset Value 7 */
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| 77 | #define REG_SDHC1_SISR (0x460000FC) /**< \brief (SDHC1) Slot Interrupt Status */
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| 78 | #define REG_SDHC1_HCVR (0x460000FE) /**< \brief (SDHC1) Host Controller Version */
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| 79 | #define REG_SDHC1_MC1R (0x46000204) /**< \brief (SDHC1) MMC Control 1 */
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| 80 | #define REG_SDHC1_MC2R (0x46000205) /**< \brief (SDHC1) MMC Control 2 */
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| 81 | #define REG_SDHC1_ACR (0x46000208) /**< \brief (SDHC1) AHB Control */
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| 82 | #define REG_SDHC1_CC2R (0x4600020C) /**< \brief (SDHC1) Clock Control 2 */
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| 83 | #define REG_SDHC1_CACR (0x46000230) /**< \brief (SDHC1) Capabilities Control */
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| 84 | #define REG_SDHC1_DBGR (0x46000234) /**< \brief (SDHC1) Debug */
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| 85 | #else
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| 86 | #define REG_SDHC1_SSAR (*(RwReg *)0x46000000UL) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
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| 87 | #define REG_SDHC1_BSR (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */
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| 88 | #define REG_SDHC1_BCR (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */
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| 89 | #define REG_SDHC1_ARG1R (*(RwReg *)0x46000008UL) /**< \brief (SDHC1) Argument 1 */
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| 90 | #define REG_SDHC1_TMR (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */
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| 91 | #define REG_SDHC1_CR (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */
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| 92 | #define REG_SDHC1_RR0 (*(RoReg *)0x46000010UL) /**< \brief (SDHC1) Response 0 */
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| 93 | #define REG_SDHC1_RR1 (*(RoReg *)0x46000014UL) /**< \brief (SDHC1) Response 1 */
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| 94 | #define REG_SDHC1_RR2 (*(RoReg *)0x46000018UL) /**< \brief (SDHC1) Response 2 */
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| 95 | #define REG_SDHC1_RR3 (*(RoReg *)0x4600001CUL) /**< \brief (SDHC1) Response 3 */
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| 96 | #define REG_SDHC1_BDPR (*(RwReg *)0x46000020UL) /**< \brief (SDHC1) Buffer Data Port */
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| 97 | #define REG_SDHC1_PSR (*(RoReg *)0x46000024UL) /**< \brief (SDHC1) Present State */
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| 98 | #define REG_SDHC1_HC1R (*(RwReg8 *)0x46000028UL) /**< \brief (SDHC1) Host Control 1 */
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| 99 | #define REG_SDHC1_PCR (*(RwReg8 *)0x46000029UL) /**< \brief (SDHC1) Power Control */
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| 100 | #define REG_SDHC1_BGCR (*(RwReg8 *)0x4600002AUL) /**< \brief (SDHC1) Block Gap Control */
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| 101 | #define REG_SDHC1_WCR (*(RwReg8 *)0x4600002BUL) /**< \brief (SDHC1) Wakeup Control */
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| 102 | #define REG_SDHC1_CCR (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */
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| 103 | #define REG_SDHC1_TCR (*(RwReg8 *)0x4600002EUL) /**< \brief (SDHC1) Timeout Control */
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| 104 | #define REG_SDHC1_SRR (*(RwReg8 *)0x4600002FUL) /**< \brief (SDHC1) Software Reset */
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| 105 | #define REG_SDHC1_NISTR (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt Status */
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| 106 | #define REG_SDHC1_EISTR (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt Status */
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| 107 | #define REG_SDHC1_NISTER (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt Status Enable */
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| 108 | #define REG_SDHC1_EISTER (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt Status Enable */
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| 109 | #define REG_SDHC1_NISIER (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
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| 110 | #define REG_SDHC1_EISIER (*(RwReg16*)0x4600003AUL) /**< \brief (SDHC1) Error Interrupt Signal Enable */
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| 111 | #define REG_SDHC1_ACESR (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Status */
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| 112 | #define REG_SDHC1_HC2R (*(RwReg16*)0x4600003EUL) /**< \brief (SDHC1) Host Control 2 */
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| 113 | #define REG_SDHC1_CA0R (*(RoReg *)0x46000040UL) /**< \brief (SDHC1) Capabilities 0 */
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| 114 | #define REG_SDHC1_CA1R (*(RoReg *)0x46000044UL) /**< \brief (SDHC1) Capabilities 1 */
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| 115 | #define REG_SDHC1_MCCAR (*(RoReg *)0x46000048UL) /**< \brief (SDHC1) Maximum Current Capabilities */
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| 116 | #define REG_SDHC1_FERACES (*(WoReg16*)0x46000050UL) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
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| 117 | #define REG_SDHC1_FEREIS (*(WoReg16*)0x46000052UL) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
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| 118 | #define REG_SDHC1_AESR (*(RoReg8 *)0x46000054UL) /**< \brief (SDHC1) ADMA Error Status */
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| 119 | #define REG_SDHC1_ASAR0 (*(RwReg *)0x46000058UL) /**< \brief (SDHC1) ADMA System Address 0 */
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| 120 | #define REG_SDHC1_PVR0 (*(RwReg16*)0x46000060UL) /**< \brief (SDHC1) Preset Value 0 */
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| 121 | #define REG_SDHC1_PVR1 (*(RwReg16*)0x46000062UL) /**< \brief (SDHC1) Preset Value 1 */
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| 122 | #define REG_SDHC1_PVR2 (*(RwReg16*)0x46000064UL) /**< \brief (SDHC1) Preset Value 2 */
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| 123 | #define REG_SDHC1_PVR3 (*(RwReg16*)0x46000066UL) /**< \brief (SDHC1) Preset Value 3 */
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| 124 | #define REG_SDHC1_PVR4 (*(RwReg16*)0x46000068UL) /**< \brief (SDHC1) Preset Value 4 */
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| 125 | #define REG_SDHC1_PVR5 (*(RwReg16*)0x4600006AUL) /**< \brief (SDHC1) Preset Value 5 */
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| 126 | #define REG_SDHC1_PVR6 (*(RwReg16*)0x4600006CUL) /**< \brief (SDHC1) Preset Value 6 */
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| 127 | #define REG_SDHC1_PVR7 (*(RwReg16*)0x4600006EUL) /**< \brief (SDHC1) Preset Value 7 */
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| 128 | #define REG_SDHC1_SISR (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Status */
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| 129 | #define REG_SDHC1_HCVR (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Version */
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| 130 | #define REG_SDHC1_MC1R (*(RwReg8 *)0x46000204UL) /**< \brief (SDHC1) MMC Control 1 */
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| 131 | #define REG_SDHC1_MC2R (*(WoReg8 *)0x46000205UL) /**< \brief (SDHC1) MMC Control 2 */
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| 132 | #define REG_SDHC1_ACR (*(RwReg *)0x46000208UL) /**< \brief (SDHC1) AHB Control */
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| 133 | #define REG_SDHC1_CC2R (*(RwReg *)0x4600020CUL) /**< \brief (SDHC1) Clock Control 2 */
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| 134 | #define REG_SDHC1_CACR (*(RwReg *)0x46000230UL) /**< \brief (SDHC1) Capabilities Control */
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| 135 | #define REG_SDHC1_DBGR (*(RwReg8 *)0x46000234UL) /**< \brief (SDHC1) Debug */
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| 136 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 137 |
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| 138 | /* ========== Instance parameters for SDHC1 peripheral ========== */
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| 139 | #define SDHC1_CARD_DATA_SIZE 4
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| 140 | #define SDHC1_CLK_AHB_ID 16
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| 141 | #define SDHC1_GCLK_ID 46
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| 142 | #define SDHC1_GCLK_ID_SLOW 3
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| 143 | #define SDHC1_NB_OF_DEVICES 1
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| 144 | #define SDHC1_NB_REG_PVR 8
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| 145 | #define SDHC1_NB_REG_RR 4
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| 146 |
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| 147 | #endif /* _SAME54_SDHC1_INSTANCE_ */
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