| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame^] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for PAC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_PAC_INSTANCE_
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| 31 | #define _SAME54_PAC_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for PAC peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */
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| 36 | #define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */
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| 37 | #define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */
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| 38 | #define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */
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| 39 | #define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
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| 40 | #define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
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| 41 | #define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
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| 42 | #define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
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| 43 | #define REG_PAC_INTFLAGD (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
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| 44 | #define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
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| 45 | #define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
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| 46 | #define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
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| 47 | #define REG_PAC_STATUSD (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */
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| 48 | #else
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| 49 | #define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */
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| 50 | #define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
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| 51 | #define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
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| 52 | #define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
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| 53 | #define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
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| 54 | #define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
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| 55 | #define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
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| 56 | #define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
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| 57 | #define REG_PAC_INTFLAGD (*(RwReg *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
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| 58 | #define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
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| 59 | #define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
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| 60 | #define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
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| 61 | #define REG_PAC_STATUSD (*(RoReg *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */
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| 62 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 63 |
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| 64 | /* ========== Instance parameters for PAC peripheral ========== */
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| 65 | #define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
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| 66 | #define PAC_CLK_AHB_ID 12 // AHB clock index
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| 67 | #define PAC_HPB_NUM 4 // Number of bridges AHB/APB
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| 68 |
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| 69 | #endif /* _SAME54_PAC_INSTANCE_ */
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