| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame^] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for OSCCTRL
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_OSCCTRL_INSTANCE_
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| 31 | #define _SAME54_OSCCTRL_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for OSCCTRL peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_OSCCTRL_EVCTRL (0x40001000) /**< \brief (OSCCTRL) Event Control */
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| 36 | #define REG_OSCCTRL_INTENCLR (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Clear */
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| 37 | #define REG_OSCCTRL_INTENSET (0x40001008) /**< \brief (OSCCTRL) Interrupt Enable Set */
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| 38 | #define REG_OSCCTRL_INTFLAG (0x4000100C) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
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| 39 | #define REG_OSCCTRL_STATUS (0x40001010) /**< \brief (OSCCTRL) Status */
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| 40 | #define REG_OSCCTRL_XOSCCTRL0 (0x40001014) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
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| 41 | #define REG_OSCCTRL_XOSCCTRL1 (0x40001018) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
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| 42 | #define REG_OSCCTRL_DFLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Control A */
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| 43 | #define REG_OSCCTRL_DFLLCTRLB (0x40001020) /**< \brief (OSCCTRL) DFLL48M Control B */
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| 44 | #define REG_OSCCTRL_DFLLVAL (0x40001024) /**< \brief (OSCCTRL) DFLL48M Value */
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| 45 | #define REG_OSCCTRL_DFLLMUL (0x40001028) /**< \brief (OSCCTRL) DFLL48M Multiplier */
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| 46 | #define REG_OSCCTRL_DFLLSYNC (0x4000102C) /**< \brief (OSCCTRL) DFLL48M Synchronization */
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| 47 | #define REG_OSCCTRL_DPLLCTRLA0 (0x40001030) /**< \brief (OSCCTRL) DPLL Control A 0 */
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| 48 | #define REG_OSCCTRL_DPLLRATIO0 (0x40001034) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
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| 49 | #define REG_OSCCTRL_DPLLCTRLB0 (0x40001038) /**< \brief (OSCCTRL) DPLL Control B 0 */
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| 50 | #define REG_OSCCTRL_DPLLSYNCBUSY0 (0x4000103C) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
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| 51 | #define REG_OSCCTRL_DPLLSTATUS0 (0x40001040) /**< \brief (OSCCTRL) DPLL Status 0 */
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| 52 | #define REG_OSCCTRL_DPLLCTRLA1 (0x40001044) /**< \brief (OSCCTRL) DPLL Control A 1 */
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| 53 | #define REG_OSCCTRL_DPLLRATIO1 (0x40001048) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
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| 54 | #define REG_OSCCTRL_DPLLCTRLB1 (0x4000104C) /**< \brief (OSCCTRL) DPLL Control B 1 */
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| 55 | #define REG_OSCCTRL_DPLLSYNCBUSY1 (0x40001050) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
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| 56 | #define REG_OSCCTRL_DPLLSTATUS1 (0x40001054) /**< \brief (OSCCTRL) DPLL Status 1 */
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| 57 | #else
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| 58 | #define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001000UL) /**< \brief (OSCCTRL) Event Control */
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| 59 | #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
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| 60 | #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
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| 61 | #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x4000100CUL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
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| 62 | #define REG_OSCCTRL_STATUS (*(RoReg *)0x40001010UL) /**< \brief (OSCCTRL) Status */
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| 63 | #define REG_OSCCTRL_XOSCCTRL0 (*(RwReg *)0x40001014UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
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| 64 | #define REG_OSCCTRL_XOSCCTRL1 (*(RwReg *)0x40001018UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
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| 65 | #define REG_OSCCTRL_DFLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Control A */
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| 66 | #define REG_OSCCTRL_DFLLCTRLB (*(RwReg8 *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Control B */
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| 67 | #define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Value */
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| 68 | #define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001028UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
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| 69 | #define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
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| 70 | #define REG_OSCCTRL_DPLLCTRLA0 (*(RwReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Control A 0 */
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| 71 | #define REG_OSCCTRL_DPLLRATIO0 (*(RwReg *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
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| 72 | #define REG_OSCCTRL_DPLLCTRLB0 (*(RwReg *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Control B 0 */
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| 73 | #define REG_OSCCTRL_DPLLSYNCBUSY0 (*(RoReg *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
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| 74 | #define REG_OSCCTRL_DPLLSTATUS0 (*(RoReg *)0x40001040UL) /**< \brief (OSCCTRL) DPLL Status 0 */
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| 75 | #define REG_OSCCTRL_DPLLCTRLA1 (*(RwReg8 *)0x40001044UL) /**< \brief (OSCCTRL) DPLL Control A 1 */
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| 76 | #define REG_OSCCTRL_DPLLRATIO1 (*(RwReg *)0x40001048UL) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
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| 77 | #define REG_OSCCTRL_DPLLCTRLB1 (*(RwReg *)0x4000104CUL) /**< \brief (OSCCTRL) DPLL Control B 1 */
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| 78 | #define REG_OSCCTRL_DPLLSYNCBUSY1 (*(RoReg *)0x40001050UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
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| 79 | #define REG_OSCCTRL_DPLLSTATUS1 (*(RoReg *)0x40001054UL) /**< \brief (OSCCTRL) DPLL Status 1 */
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| 80 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 81 |
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| 82 | /* ========== Instance parameters for OSCCTRL peripheral ========== */
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| 83 | #define OSCCTRL_DFLLS_NUM 1 // Number of DFLLs
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| 84 | #define OSCCTRL_DFLL_IMPLEMENTED 1 // DFLL implemented
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| 85 | #define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0 // DFLL48M bias test mode implemented
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| 86 | #define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2 // Size COARSE DAC STEP
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| 87 | #define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32 // DFLL48M Frequency Coarse Reset Value (Before Calibration)
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| 88 | #define OSCCTRL_DFLL48M_COARSE_SIZE 6 // Size COARSE CALIBRATION
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| 89 | #define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1 // Run oscillator at reset
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| 90 | #define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2 // Size FINE DAC STEP
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| 91 | #define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128 // DFLL48M Frequency Fine Reset Value (Before Calibration)
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| 92 | #define OSCCTRL_DFLL48M_FINE_SIZE 8 // Size FINE CALIBRATION
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| 93 | #define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
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| 94 | #define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
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| 95 | #define OSCCTRL_DFLL48M_TCAL_SIZE 4 // Size TEMP CALIBRATION
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| 96 | #define OSCCTRL_DFLL48M_TCBIAS_SIZE 2 // Size TC BIAS CALIBRATION
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| 97 | #define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3 // Size TEST POINT SELECTOR
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| 98 | #define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1 // Enable Wait Lock Feature
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| 99 | #define OSCCTRL_DPLLS_NUM 2 // Number of DPLLs
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| 100 | #define OSCCTRL_DPLL0_IMPLEMENTED 1 // DPLL0 implemented
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| 101 | #define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
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| 102 | #define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1 // DPLL0 OCC Implemented
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| 103 | #define OSCCTRL_DPLL1_IMPLEMENTED 1 // DPLL1 implemented
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| 104 | #define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
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| 105 | #define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0 // DPLL1 OCC Implemented
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| 106 | #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
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| 107 | #define OSCCTRL_GCLK_ID_FDPLL0 1 // Index of Generic Clock for DPLL0
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| 108 | #define OSCCTRL_GCLK_ID_FDPLL1 2 // Index of Generic Clock for DPLL1
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| 109 | #define OSCCTRL_GCLK_ID_FDPLL032K 3 // Index of Generic Clock for DPLL0 32K
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| 110 | #define OSCCTRL_GCLK_ID_FDPLL132K 3 // Index of Generic Clock for DPLL1 32K
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| 111 | #define OSCCTRL_OSC16M_IMPLEMENTED 0 // OSC16M implemented
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| 112 | #define OSCCTRL_OSC48M_IMPLEMENTED 0 // OSC48M implemented
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| 113 | #define OSCCTRL_OSC48M_NUM 1
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| 114 | #define OSCCTRL_RCOSCS_NUM 1 // Number of RCOSCs (min 1)
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| 115 | #define OSCCTRL_XOSCS_NUM 2 // Number of XOSCs
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| 116 | #define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
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| 117 | #define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
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| 118 | #define OSCCTRL_XOSC0_IMPLEMENTED 1 // XOSC0 implemented
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| 119 | #define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
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| 120 | #define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
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| 121 | #define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
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| 122 | #define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
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| 123 | #define OSCCTRL_XOSC1_IMPLEMENTED 1 // XOSC1 implemented
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| 124 | #define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
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| 125 | #define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
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| 126 | #define OSCCTRL_DFLL48M_VERSION 0x100
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| 127 | #define OSCCTRL_FDPLL_VERSION 0x100
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| 128 | #define OSCCTRL_XOSC_VERSION 0x100
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| 129 |
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| 130 | #endif /* _SAME54_OSCCTRL_INSTANCE_ */
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