| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame^] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for WDT
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_WDT_COMPONENT_
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| 31 | #define _SAME54_WDT_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR WDT */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_WDT Watchdog Timer */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define WDT_U2251
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| 40 | #define REV_WDT 0x110
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| 41 |
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| 42 | /* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t :1; /*!< bit: 0 Reserved */
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| 47 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
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| 49 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
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| 50 | uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
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| 51 | } bit; /*!< Structure used for bit access */
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| 52 | uint8_t reg; /*!< Type used for register access */
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| 53 | } WDT_CTRLA_Type;
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| 54 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 55 |
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| 56 | #define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */
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| 57 | #define WDT_CTRLA_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRLA reset_value) Control */
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| 58 |
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| 59 | #define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */
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| 60 | #define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
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| 61 | #define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
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| 62 | #define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
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| 63 | #define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */
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| 64 | #define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
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| 65 | #define WDT_CTRLA_MASK _U_(0x86) /**< \brief (WDT_CTRLA) MASK Register */
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| 66 |
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| 67 | /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
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| 68 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 69 | typedef union {
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| 70 | struct {
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| 71 | uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
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| 72 | uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
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| 73 | } bit; /*!< Structure used for bit access */
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| 74 | uint8_t reg; /*!< Type used for register access */
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| 75 | } WDT_CONFIG_Type;
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| 76 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 77 |
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| 78 | #define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
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| 79 | #define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
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| 80 |
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| 81 | #define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
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| 82 | #define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
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| 83 | #define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
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| 84 | #define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
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| 85 | #define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
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| 86 | #define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
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| 87 | #define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
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| 88 | #define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
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| 89 | #define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
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| 90 | #define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
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| 91 | #define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
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| 92 | #define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
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| 93 | #define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
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| 94 | #define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
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| 95 | #define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
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| 96 | #define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
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| 97 | #define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
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| 98 | #define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
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| 99 | #define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
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| 100 | #define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
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| 101 | #define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
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| 102 | #define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
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| 103 | #define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
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| 104 | #define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
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| 105 | #define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
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| 106 | #define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
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| 107 | #define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
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| 108 | #define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
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| 109 | #define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
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| 110 | #define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
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| 111 | #define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
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| 112 | #define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
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| 113 | #define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
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| 114 | #define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
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| 115 | #define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
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| 116 | #define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
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| 117 | #define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
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| 118 | #define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
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| 119 | #define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
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| 120 | #define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
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| 121 | #define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
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| 122 | #define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
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| 123 | #define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
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| 124 | #define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
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| 125 | #define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
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| 126 | #define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
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| 127 | #define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
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| 128 | #define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
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| 129 | #define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
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| 130 | #define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
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| 131 | #define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
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| 132 | #define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
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| 133 | #define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
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| 134 | #define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
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| 135 | #define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
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| 136 |
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| 137 | /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
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| 138 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 139 | typedef union {
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| 140 | struct {
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| 141 | uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
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| 142 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
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| 143 | } bit; /*!< Structure used for bit access */
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| 144 | uint8_t reg; /*!< Type used for register access */
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| 145 | } WDT_EWCTRL_Type;
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| 146 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 147 |
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| 148 | #define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
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| 149 | #define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
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| 150 |
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| 151 | #define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
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| 152 | #define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
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| 153 | #define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
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| 154 | #define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
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| 155 | #define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
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| 156 | #define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
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| 157 | #define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
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| 158 | #define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
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| 159 | #define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
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| 160 | #define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
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| 161 | #define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
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| 162 | #define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
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| 163 | #define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
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| 164 | #define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
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| 165 | #define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
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| 166 | #define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 167 | #define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 168 | #define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 169 | #define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 170 | #define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 171 | #define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 172 | #define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 173 | #define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 174 | #define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 175 | #define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 176 | #define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 177 | #define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
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| 178 | #define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
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| 179 |
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| 180 | /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
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| 181 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 182 | typedef union {
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| 183 | struct {
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| 184 | uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
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| 185 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 186 | } bit; /*!< Structure used for bit access */
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| 187 | uint8_t reg; /*!< Type used for register access */
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| 188 | } WDT_INTENCLR_Type;
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| 189 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 190 |
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| 191 | #define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
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| 192 | #define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
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| 193 |
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| 194 | #define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
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| 195 | #define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
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| 196 | #define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
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| 197 |
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| 198 | /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
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| 199 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 200 | typedef union {
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| 201 | struct {
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| 202 | uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
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| 203 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 204 | } bit; /*!< Structure used for bit access */
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| 205 | uint8_t reg; /*!< Type used for register access */
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| 206 | } WDT_INTENSET_Type;
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| 207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 208 |
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| 209 | #define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
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| 210 | #define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
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| 211 |
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| 212 | #define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
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| 213 | #define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
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| 214 | #define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
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| 215 |
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| 216 | /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 217 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 218 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 219 | struct {
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| 220 | __I uint8_t EW:1; /*!< bit: 0 Early Warning */
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| 221 | __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 222 | } bit; /*!< Structure used for bit access */
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| 223 | uint8_t reg; /*!< Type used for register access */
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| 224 | } WDT_INTFLAG_Type;
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| 225 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 226 |
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| 227 | #define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
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| 228 | #define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 229 |
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| 230 | #define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
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| 231 | #define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
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| 232 | #define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
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| 233 |
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| 234 | /* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
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| 235 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 236 | typedef union {
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| 237 | struct {
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| 238 | uint32_t :1; /*!< bit: 0 Reserved */
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| 239 | uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
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| 240 | uint32_t WEN:1; /*!< bit: 2 Window Enable Synchronization Busy */
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| 241 | uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Synchronization Busy */
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| 242 | uint32_t CLEAR:1; /*!< bit: 4 Clear Synchronization Busy */
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| 243 | uint32_t :27; /*!< bit: 5..31 Reserved */
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| 244 | } bit; /*!< Structure used for bit access */
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| 245 | uint32_t reg; /*!< Type used for register access */
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| 246 | } WDT_SYNCBUSY_Type;
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| 247 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 248 |
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| 249 | #define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
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| 250 | #define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
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| 251 |
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| 252 | #define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
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| 253 | #define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
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| 254 | #define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
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| 255 | #define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
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| 256 | #define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
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| 257 | #define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
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| 258 | #define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
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| 259 | #define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
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| 260 | #define WDT_SYNCBUSY_MASK _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
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| 261 |
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| 262 | /* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
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| 263 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 264 | typedef union {
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| 265 | struct {
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| 266 | uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
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| 267 | } bit; /*!< Structure used for bit access */
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| 268 | uint8_t reg; /*!< Type used for register access */
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| 269 | } WDT_CLEAR_Type;
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| 270 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 271 |
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| 272 | #define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */
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| 273 | #define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
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| 274 |
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| 275 | #define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
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| 276 | #define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
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| 277 | #define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
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| 278 | #define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
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| 279 | #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
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| 280 | #define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
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| 281 |
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| 282 | /** \brief WDT hardware registers */
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| 283 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 284 | typedef struct {
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| 285 | __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */
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| 286 | __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
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| 287 | __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
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| 288 | RoReg8 Reserved1[0x1];
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| 289 | __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
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| 290 | __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
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| 291 | __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
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| 292 | RoReg8 Reserved2[0x1];
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| 293 | __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */
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| 294 | __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
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| 295 | } Wdt;
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| 296 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 297 |
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| 298 | /*@}*/
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| 299 |
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| 300 | #endif /* _SAME54_WDT_COMPONENT_ */
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