| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame^] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for RSTC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_RSTC_COMPONENT_
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| 31 | #define _SAME54_RSTC_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR RSTC */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_RSTC Reset Controller */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define RSTC_U2239
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| 40 | #define REV_RSTC 0x400
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| 41 |
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| 42 | /* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t POR:1; /*!< bit: 0 Power On Reset */
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| 47 | uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
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| 48 | uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
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| 49 | uint8_t NVM:1; /*!< bit: 3 NVM Reset */
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| 50 | uint8_t EXT:1; /*!< bit: 4 External Reset */
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| 51 | uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
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| 52 | uint8_t SYST:1; /*!< bit: 6 System Reset Request */
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| 53 | uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */
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| 54 | } bit; /*!< Structure used for bit access */
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| 55 | uint8_t reg; /*!< Type used for register access */
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| 56 | } RSTC_RCAUSE_Type;
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| 57 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 58 |
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| 59 | #define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
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| 60 |
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| 61 | #define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
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| 62 | #define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
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| 63 | #define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
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| 64 | #define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
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| 65 | #define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
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| 66 | #define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
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| 67 | #define RSTC_RCAUSE_NVM_Pos 3 /**< \brief (RSTC_RCAUSE) NVM Reset */
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| 68 | #define RSTC_RCAUSE_NVM (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
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| 69 | #define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
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| 70 | #define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
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| 71 | #define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
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| 72 | #define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
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| 73 | #define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
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| 74 | #define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
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| 75 | #define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */
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| 76 | #define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
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| 77 | #define RSTC_RCAUSE_MASK _U_(0xFF) /**< \brief (RSTC_RCAUSE) MASK Register */
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| 78 |
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| 79 | /* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */
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| 80 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 81 | typedef union {
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| 82 | struct {
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| 83 | uint8_t :1; /*!< bit: 0 Reserved */
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| 84 | uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */
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| 85 | uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */
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| 86 | uint8_t :4; /*!< bit: 3.. 6 Reserved */
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| 87 | uint8_t HIB:1; /*!< bit: 7 Hibernate */
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| 88 | } bit; /*!< Structure used for bit access */
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| 89 | uint8_t reg; /*!< Type used for register access */
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| 90 | } RSTC_BKUPEXIT_Type;
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| 91 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 92 |
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| 93 | #define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
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| 94 | #define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
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| 95 |
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| 96 | #define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
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| 97 | #define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
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| 98 | #define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
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| 99 | #define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
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| 100 | #define RSTC_BKUPEXIT_HIB_Pos 7 /**< \brief (RSTC_BKUPEXIT) Hibernate */
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| 101 | #define RSTC_BKUPEXIT_HIB (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
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| 102 | #define RSTC_BKUPEXIT_MASK _U_(0x86) /**< \brief (RSTC_BKUPEXIT) MASK Register */
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| 103 |
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| 104 | /** \brief RSTC hardware registers */
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| 105 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 106 | typedef struct {
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| 107 | __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
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| 108 | RoReg8 Reserved1[0x1];
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| 109 | __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */
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| 110 | } Rstc;
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| 111 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 112 |
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| 113 | /*@}*/
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| 114 |
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| 115 | #endif /* _SAME54_RSTC_COMPONENT_ */
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