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gerrit.osmocom.org / osmo-ccid-firmware / e6ac4164aff16fce8aabce1f8cb7af84b77c738a / . / sysmoOCTSIM / hri / hri_port_e54.h
blob: 261fcf57d4155cac5f49c8fb55af5819b780db81 [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief SAM PORT
5 *
6 * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Subject to your compliance with these terms, you may use Microchip
13 * software and any derivatives exclusively with Microchip products.
14 * It is your responsibility to comply with third party license terms applicable
15 * to your use of third party software (including open source software) that
16 * may accompany Microchip software.
17 *
18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
29 *
30 * \asf_license_stop
31 *
32 */
33
34#ifdef _SAME54_PORT_COMPONENT_
35#ifndef _HRI_PORT_E54_H_INCLUDED_
36#define _HRI_PORT_E54_H_INCLUDED_
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <stdbool.h>
43#include <hal_atomic.h>
44
45#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
46#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
47#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
48#else
49#define PORT_CRITICAL_SECTION_ENTER()
50#define PORT_CRITICAL_SECTION_LEAVE()
51#endif
52
53typedef uint32_t hri_port_ctrl_reg_t;
54typedef uint32_t hri_port_dir_reg_t;
55typedef uint32_t hri_port_evctrl_reg_t;
56typedef uint32_t hri_port_in_reg_t;
57typedef uint32_t hri_port_out_reg_t;
58typedef uint32_t hri_port_wrconfig_reg_t;
59typedef uint32_t hri_portgroup_ctrl_reg_t;
60typedef uint32_t hri_portgroup_dir_reg_t;
61typedef uint32_t hri_portgroup_evctrl_reg_t;
62typedef uint32_t hri_portgroup_in_reg_t;
63typedef uint32_t hri_portgroup_out_reg_t;
64typedef uint32_t hri_portgroup_wrconfig_reg_t;
65typedef uint8_t hri_port_pincfg_reg_t;
66typedef uint8_t hri_port_pmux_reg_t;
67typedef uint8_t hri_portgroup_pincfg_reg_t;
68typedef uint8_t hri_portgroup_pmux_reg_t;
69
70static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
71{
72 ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask);
73}
74
75static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
76{
77 uint32_t tmp;
78 tmp = ((PortGroup *)hw)->DIR.reg;
79 tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
80 return tmp;
81}
82
83static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw)
84{
85 uint32_t tmp;
86 tmp = ((PortGroup *)hw)->DIR.reg;
87 tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
88 return tmp;
89}
90
91static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data)
92{
93 ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data);
94 ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data);
95}
96
97static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
98{
99 ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask);
100}
101
102static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
103{
104 ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask);
105}
106
107static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
108{
109 ((PortGroup *)hw)->DIRSET.reg = mask;
110}
111
112static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
113{
114 uint32_t tmp;
115 tmp = ((PortGroup *)hw)->DIR.reg;
116 tmp &= mask;
117 return tmp;
118}
119
120static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
121{
122 return ((PortGroup *)hw)->DIR.reg;
123}
124
125static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
126{
127 ((PortGroup *)hw)->DIRSET.reg = data;
128 ((PortGroup *)hw)->DIRCLR.reg = ~data;
129}
130
131static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
132{
133 ((PortGroup *)hw)->DIRCLR.reg = mask;
134}
135
136static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
137{
138 ((PortGroup *)hw)->DIRTGL.reg = mask;
139}
140
141static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
142{
143 ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask);
144}
145
146static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
147{
148 uint32_t tmp;
149 tmp = ((PortGroup *)hw)->OUT.reg;
150 tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
151 return tmp;
152}
153
154static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw)
155{
156 uint32_t tmp;
157 tmp = ((PortGroup *)hw)->OUT.reg;
158 tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
159 return tmp;
160}
161
162static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data)
163{
164 ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data);
165 ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data);
166}
167
168static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
169{
170 ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask);
171}
172
173static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
174{
175 ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask);
176}
177
178static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
179{
180 ((PortGroup *)hw)->OUTSET.reg = mask;
181}
182
183static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
184{
185 uint32_t tmp;
186 tmp = ((PortGroup *)hw)->OUT.reg;
187 tmp &= mask;
188 return tmp;
189}
190
191static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
192{
193 return ((PortGroup *)hw)->OUT.reg;
194}
195
196static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
197{
198 ((PortGroup *)hw)->OUTSET.reg = data;
199 ((PortGroup *)hw)->OUTCLR.reg = ~data;
200}
201
202static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
203{
204 ((PortGroup *)hw)->OUTCLR.reg = mask;
205}
206
207static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
208{
209 ((PortGroup *)hw)->OUTTGL.reg = mask;
210}
211
212static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask)
213{
214 return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
215}
216
217static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw)
218{
219 return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
220}
221
222static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
223{
224 uint32_t tmp;
225 tmp = ((PortGroup *)hw)->IN.reg;
226 tmp &= mask;
227 return tmp;
228}
229
230static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
231{
232 return ((PortGroup *)hw)->IN.reg;
233}
234
235static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
236{
237 PORT_CRITICAL_SECTION_ENTER();
238 ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
239 PORT_CRITICAL_SECTION_LEAVE();
240}
241
242static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
243{
244 uint32_t tmp;
245 tmp = ((PortGroup *)hw)->CTRL.reg;
246 tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
247 return tmp;
248}
249
250static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
251{
252 uint32_t tmp;
253 PORT_CRITICAL_SECTION_ENTER();
254 tmp = ((PortGroup *)hw)->CTRL.reg;
255 tmp &= ~PORT_CTRL_SAMPLING_Msk;
256 tmp |= PORT_CTRL_SAMPLING(data);
257 ((PortGroup *)hw)->CTRL.reg = tmp;
258 PORT_CRITICAL_SECTION_LEAVE();
259}
260
261static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
262{
263 PORT_CRITICAL_SECTION_ENTER();
264 ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
265 PORT_CRITICAL_SECTION_LEAVE();
266}
267
268static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
269{
270 PORT_CRITICAL_SECTION_ENTER();
271 ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
272 PORT_CRITICAL_SECTION_LEAVE();
273}
274
275static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
276{
277 uint32_t tmp;
278 tmp = ((PortGroup *)hw)->CTRL.reg;
279 tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
280 return tmp;
281}
282
283static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
284{
285 PORT_CRITICAL_SECTION_ENTER();
286 ((PortGroup *)hw)->CTRL.reg |= mask;
287 PORT_CRITICAL_SECTION_LEAVE();
288}
289
290static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
291{
292 uint32_t tmp;
293 tmp = ((PortGroup *)hw)->CTRL.reg;
294 tmp &= mask;
295 return tmp;
296}
297
298static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
299{
300 PORT_CRITICAL_SECTION_ENTER();
301 ((PortGroup *)hw)->CTRL.reg = data;
302 PORT_CRITICAL_SECTION_LEAVE();
303}
304
305static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
306{
307 PORT_CRITICAL_SECTION_ENTER();
308 ((PortGroup *)hw)->CTRL.reg &= ~mask;
309 PORT_CRITICAL_SECTION_LEAVE();
310}
311
312static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
313{
314 PORT_CRITICAL_SECTION_ENTER();
315 ((PortGroup *)hw)->CTRL.reg ^= mask;
316 PORT_CRITICAL_SECTION_LEAVE();
317}
318
319static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
320{
321 return ((PortGroup *)hw)->CTRL.reg;
322}
323
324static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
325{
326 PORT_CRITICAL_SECTION_ENTER();
327 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
328 PORT_CRITICAL_SECTION_LEAVE();
329}
330
331static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
332{
333 uint32_t tmp;
334 tmp = ((PortGroup *)hw)->EVCTRL.reg;
335 tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
336 return (bool)tmp;
337}
338
339static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
340{
341 uint32_t tmp;
342 PORT_CRITICAL_SECTION_ENTER();
343 tmp = ((PortGroup *)hw)->EVCTRL.reg;
344 tmp &= ~PORT_EVCTRL_PORTEI0;
345 tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
346 ((PortGroup *)hw)->EVCTRL.reg = tmp;
347 PORT_CRITICAL_SECTION_LEAVE();
348}
349
350static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
351{
352 PORT_CRITICAL_SECTION_ENTER();
353 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
354 PORT_CRITICAL_SECTION_LEAVE();
355}
356
357static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
358{
359 PORT_CRITICAL_SECTION_ENTER();
360 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
361 PORT_CRITICAL_SECTION_LEAVE();
362}
363
364static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
365{
366 PORT_CRITICAL_SECTION_ENTER();
367 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
368 PORT_CRITICAL_SECTION_LEAVE();
369}
370
371static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
372{
373 uint32_t tmp;
374 tmp = ((PortGroup *)hw)->EVCTRL.reg;
375 tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
376 return (bool)tmp;
377}
378
379static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
380{
381 uint32_t tmp;
382 PORT_CRITICAL_SECTION_ENTER();
383 tmp = ((PortGroup *)hw)->EVCTRL.reg;
384 tmp &= ~PORT_EVCTRL_PORTEI1;
385 tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
386 ((PortGroup *)hw)->EVCTRL.reg = tmp;
387 PORT_CRITICAL_SECTION_LEAVE();
388}
389
390static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
391{
392 PORT_CRITICAL_SECTION_ENTER();
393 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
394 PORT_CRITICAL_SECTION_LEAVE();
395}
396
397static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
398{
399 PORT_CRITICAL_SECTION_ENTER();
400 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
401 PORT_CRITICAL_SECTION_LEAVE();
402}
403
404static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
405{
406 PORT_CRITICAL_SECTION_ENTER();
407 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
408 PORT_CRITICAL_SECTION_LEAVE();
409}
410
411static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
412{
413 uint32_t tmp;
414 tmp = ((PortGroup *)hw)->EVCTRL.reg;
415 tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
416 return (bool)tmp;
417}
418
419static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
420{
421 uint32_t tmp;
422 PORT_CRITICAL_SECTION_ENTER();
423 tmp = ((PortGroup *)hw)->EVCTRL.reg;
424 tmp &= ~PORT_EVCTRL_PORTEI2;
425 tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
426 ((PortGroup *)hw)->EVCTRL.reg = tmp;
427 PORT_CRITICAL_SECTION_LEAVE();
428}
429
430static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
431{
432 PORT_CRITICAL_SECTION_ENTER();
433 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
434 PORT_CRITICAL_SECTION_LEAVE();
435}
436
437static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
438{
439 PORT_CRITICAL_SECTION_ENTER();
440 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
441 PORT_CRITICAL_SECTION_LEAVE();
442}
443
444static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
445{
446 PORT_CRITICAL_SECTION_ENTER();
447 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
448 PORT_CRITICAL_SECTION_LEAVE();
449}
450
451static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
452{
453 uint32_t tmp;
454 tmp = ((PortGroup *)hw)->EVCTRL.reg;
455 tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
456 return (bool)tmp;
457}
458
459static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
460{
461 uint32_t tmp;
462 PORT_CRITICAL_SECTION_ENTER();
463 tmp = ((PortGroup *)hw)->EVCTRL.reg;
464 tmp &= ~PORT_EVCTRL_PORTEI3;
465 tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
466 ((PortGroup *)hw)->EVCTRL.reg = tmp;
467 PORT_CRITICAL_SECTION_LEAVE();
468}
469
470static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
471{
472 PORT_CRITICAL_SECTION_ENTER();
473 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
474 PORT_CRITICAL_SECTION_LEAVE();
475}
476
477static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
478{
479 PORT_CRITICAL_SECTION_ENTER();
480 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
481 PORT_CRITICAL_SECTION_LEAVE();
482}
483
484static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
485{
486 PORT_CRITICAL_SECTION_ENTER();
487 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
488 PORT_CRITICAL_SECTION_LEAVE();
489}
490
491static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
492{
493 uint32_t tmp;
494 tmp = ((PortGroup *)hw)->EVCTRL.reg;
495 tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
496 return tmp;
497}
498
499static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
500{
501 uint32_t tmp;
502 PORT_CRITICAL_SECTION_ENTER();
503 tmp = ((PortGroup *)hw)->EVCTRL.reg;
504 tmp &= ~PORT_EVCTRL_PID0_Msk;
505 tmp |= PORT_EVCTRL_PID0(data);
506 ((PortGroup *)hw)->EVCTRL.reg = tmp;
507 PORT_CRITICAL_SECTION_LEAVE();
508}
509
510static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
511{
512 PORT_CRITICAL_SECTION_ENTER();
513 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
514 PORT_CRITICAL_SECTION_LEAVE();
515}
516
517static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
518{
519 PORT_CRITICAL_SECTION_ENTER();
520 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
521 PORT_CRITICAL_SECTION_LEAVE();
522}
523
524static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
525{
526 uint32_t tmp;
527 tmp = ((PortGroup *)hw)->EVCTRL.reg;
528 tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
529 return tmp;
530}
531
532static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
533{
534 PORT_CRITICAL_SECTION_ENTER();
535 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
536 PORT_CRITICAL_SECTION_LEAVE();
537}
538
539static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
540{
541 uint32_t tmp;
542 tmp = ((PortGroup *)hw)->EVCTRL.reg;
543 tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
544 return tmp;
545}
546
547static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
548{
549 uint32_t tmp;
550 PORT_CRITICAL_SECTION_ENTER();
551 tmp = ((PortGroup *)hw)->EVCTRL.reg;
552 tmp &= ~PORT_EVCTRL_EVACT0_Msk;
553 tmp |= PORT_EVCTRL_EVACT0(data);
554 ((PortGroup *)hw)->EVCTRL.reg = tmp;
555 PORT_CRITICAL_SECTION_LEAVE();
556}
557
558static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
559{
560 PORT_CRITICAL_SECTION_ENTER();
561 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
562 PORT_CRITICAL_SECTION_LEAVE();
563}
564
565static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
566{
567 PORT_CRITICAL_SECTION_ENTER();
568 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
569 PORT_CRITICAL_SECTION_LEAVE();
570}
571
572static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
573{
574 uint32_t tmp;
575 tmp = ((PortGroup *)hw)->EVCTRL.reg;
576 tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
577 return tmp;
578}
579
580static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
581{
582 PORT_CRITICAL_SECTION_ENTER();
583 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
584 PORT_CRITICAL_SECTION_LEAVE();
585}
586
587static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
588{
589 uint32_t tmp;
590 tmp = ((PortGroup *)hw)->EVCTRL.reg;
591 tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
592 return tmp;
593}
594
595static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
596{
597 uint32_t tmp;
598 PORT_CRITICAL_SECTION_ENTER();
599 tmp = ((PortGroup *)hw)->EVCTRL.reg;
600 tmp &= ~PORT_EVCTRL_PID1_Msk;
601 tmp |= PORT_EVCTRL_PID1(data);
602 ((PortGroup *)hw)->EVCTRL.reg = tmp;
603 PORT_CRITICAL_SECTION_LEAVE();
604}
605
606static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
607{
608 PORT_CRITICAL_SECTION_ENTER();
609 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
610 PORT_CRITICAL_SECTION_LEAVE();
611}
612
613static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
614{
615 PORT_CRITICAL_SECTION_ENTER();
616 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
617 PORT_CRITICAL_SECTION_LEAVE();
618}
619
620static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
621{
622 uint32_t tmp;
623 tmp = ((PortGroup *)hw)->EVCTRL.reg;
624 tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
625 return tmp;
626}
627
628static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
629{
630 PORT_CRITICAL_SECTION_ENTER();
631 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
632 PORT_CRITICAL_SECTION_LEAVE();
633}
634
635static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
636{
637 uint32_t tmp;
638 tmp = ((PortGroup *)hw)->EVCTRL.reg;
639 tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
640 return tmp;
641}
642
643static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
644{
645 uint32_t tmp;
646 PORT_CRITICAL_SECTION_ENTER();
647 tmp = ((PortGroup *)hw)->EVCTRL.reg;
648 tmp &= ~PORT_EVCTRL_EVACT1_Msk;
649 tmp |= PORT_EVCTRL_EVACT1(data);
650 ((PortGroup *)hw)->EVCTRL.reg = tmp;
651 PORT_CRITICAL_SECTION_LEAVE();
652}
653
654static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
655{
656 PORT_CRITICAL_SECTION_ENTER();
657 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
658 PORT_CRITICAL_SECTION_LEAVE();
659}
660
661static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
662{
663 PORT_CRITICAL_SECTION_ENTER();
664 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
665 PORT_CRITICAL_SECTION_LEAVE();
666}
667
668static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
669{
670 uint32_t tmp;
671 tmp = ((PortGroup *)hw)->EVCTRL.reg;
672 tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
673 return tmp;
674}
675
676static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
677{
678 PORT_CRITICAL_SECTION_ENTER();
679 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
680 PORT_CRITICAL_SECTION_LEAVE();
681}
682
683static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
684{
685 uint32_t tmp;
686 tmp = ((PortGroup *)hw)->EVCTRL.reg;
687 tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
688 return tmp;
689}
690
691static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
692{
693 uint32_t tmp;
694 PORT_CRITICAL_SECTION_ENTER();
695 tmp = ((PortGroup *)hw)->EVCTRL.reg;
696 tmp &= ~PORT_EVCTRL_PID2_Msk;
697 tmp |= PORT_EVCTRL_PID2(data);
698 ((PortGroup *)hw)->EVCTRL.reg = tmp;
699 PORT_CRITICAL_SECTION_LEAVE();
700}
701
702static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
703{
704 PORT_CRITICAL_SECTION_ENTER();
705 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
706 PORT_CRITICAL_SECTION_LEAVE();
707}
708
709static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
710{
711 PORT_CRITICAL_SECTION_ENTER();
712 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
713 PORT_CRITICAL_SECTION_LEAVE();
714}
715
716static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
717{
718 uint32_t tmp;
719 tmp = ((PortGroup *)hw)->EVCTRL.reg;
720 tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
721 return tmp;
722}
723
724static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
725{
726 PORT_CRITICAL_SECTION_ENTER();
727 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
728 PORT_CRITICAL_SECTION_LEAVE();
729}
730
731static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
732{
733 uint32_t tmp;
734 tmp = ((PortGroup *)hw)->EVCTRL.reg;
735 tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
736 return tmp;
737}
738
739static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
740{
741 uint32_t tmp;
742 PORT_CRITICAL_SECTION_ENTER();
743 tmp = ((PortGroup *)hw)->EVCTRL.reg;
744 tmp &= ~PORT_EVCTRL_EVACT2_Msk;
745 tmp |= PORT_EVCTRL_EVACT2(data);
746 ((PortGroup *)hw)->EVCTRL.reg = tmp;
747 PORT_CRITICAL_SECTION_LEAVE();
748}
749
750static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
751{
752 PORT_CRITICAL_SECTION_ENTER();
753 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
754 PORT_CRITICAL_SECTION_LEAVE();
755}
756
757static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
758{
759 PORT_CRITICAL_SECTION_ENTER();
760 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
761 PORT_CRITICAL_SECTION_LEAVE();
762}
763
764static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
765{
766 uint32_t tmp;
767 tmp = ((PortGroup *)hw)->EVCTRL.reg;
768 tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
769 return tmp;
770}
771
772static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
773{
774 PORT_CRITICAL_SECTION_ENTER();
775 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
776 PORT_CRITICAL_SECTION_LEAVE();
777}
778
779static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
780{
781 uint32_t tmp;
782 tmp = ((PortGroup *)hw)->EVCTRL.reg;
783 tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
784 return tmp;
785}
786
787static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
788{
789 uint32_t tmp;
790 PORT_CRITICAL_SECTION_ENTER();
791 tmp = ((PortGroup *)hw)->EVCTRL.reg;
792 tmp &= ~PORT_EVCTRL_PID3_Msk;
793 tmp |= PORT_EVCTRL_PID3(data);
794 ((PortGroup *)hw)->EVCTRL.reg = tmp;
795 PORT_CRITICAL_SECTION_LEAVE();
796}
797
798static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
799{
800 PORT_CRITICAL_SECTION_ENTER();
801 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
802 PORT_CRITICAL_SECTION_LEAVE();
803}
804
805static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
806{
807 PORT_CRITICAL_SECTION_ENTER();
808 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
809 PORT_CRITICAL_SECTION_LEAVE();
810}
811
812static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
813{
814 uint32_t tmp;
815 tmp = ((PortGroup *)hw)->EVCTRL.reg;
816 tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
817 return tmp;
818}
819
820static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
821{
822 PORT_CRITICAL_SECTION_ENTER();
823 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
824 PORT_CRITICAL_SECTION_LEAVE();
825}
826
827static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
828{
829 uint32_t tmp;
830 tmp = ((PortGroup *)hw)->EVCTRL.reg;
831 tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
832 return tmp;
833}
834
835static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
836{
837 uint32_t tmp;
838 PORT_CRITICAL_SECTION_ENTER();
839 tmp = ((PortGroup *)hw)->EVCTRL.reg;
840 tmp &= ~PORT_EVCTRL_EVACT3_Msk;
841 tmp |= PORT_EVCTRL_EVACT3(data);
842 ((PortGroup *)hw)->EVCTRL.reg = tmp;
843 PORT_CRITICAL_SECTION_LEAVE();
844}
845
846static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
847{
848 PORT_CRITICAL_SECTION_ENTER();
849 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
850 PORT_CRITICAL_SECTION_LEAVE();
851}
852
853static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
854{
855 PORT_CRITICAL_SECTION_ENTER();
856 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
857 PORT_CRITICAL_SECTION_LEAVE();
858}
859
860static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
861{
862 uint32_t tmp;
863 tmp = ((PortGroup *)hw)->EVCTRL.reg;
864 tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
865 return tmp;
866}
867
868static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
869{
870 PORT_CRITICAL_SECTION_ENTER();
871 ((PortGroup *)hw)->EVCTRL.reg |= mask;
872 PORT_CRITICAL_SECTION_LEAVE();
873}
874
875static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
876{
877 uint32_t tmp;
878 tmp = ((PortGroup *)hw)->EVCTRL.reg;
879 tmp &= mask;
880 return tmp;
881}
882
883static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
884{
885 PORT_CRITICAL_SECTION_ENTER();
886 ((PortGroup *)hw)->EVCTRL.reg = data;
887 PORT_CRITICAL_SECTION_LEAVE();
888}
889
890static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
891{
892 PORT_CRITICAL_SECTION_ENTER();
893 ((PortGroup *)hw)->EVCTRL.reg &= ~mask;
894 PORT_CRITICAL_SECTION_LEAVE();
895}
896
897static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
898{
899 PORT_CRITICAL_SECTION_ENTER();
900 ((PortGroup *)hw)->EVCTRL.reg ^= mask;
901 PORT_CRITICAL_SECTION_LEAVE();
902}
903
904static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
905{
906 return ((PortGroup *)hw)->EVCTRL.reg;
907}
908
909static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
910{
911 PORT_CRITICAL_SECTION_ENTER();
912 ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
913 PORT_CRITICAL_SECTION_LEAVE();
914}
915
916static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
917 hri_port_pmux_reg_t mask)
918{
919 uint8_t tmp;
920 tmp = ((PortGroup *)hw)->PMUX[index].reg;
921 tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
922 return tmp;
923}
924
925static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
926{
927 uint8_t tmp;
928 PORT_CRITICAL_SECTION_ENTER();
929 tmp = ((PortGroup *)hw)->PMUX[index].reg;
930 tmp &= ~PORT_PMUX_PMUXE_Msk;
931 tmp |= PORT_PMUX_PMUXE(data);
932 ((PortGroup *)hw)->PMUX[index].reg = tmp;
933 PORT_CRITICAL_SECTION_LEAVE();
934}
935
936static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
937{
938 PORT_CRITICAL_SECTION_ENTER();
939 ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
940 PORT_CRITICAL_SECTION_LEAVE();
941}
942
943static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
944{
945 PORT_CRITICAL_SECTION_ENTER();
946 ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
947 PORT_CRITICAL_SECTION_LEAVE();
948}
949
950static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
951{
952 uint8_t tmp;
953 tmp = ((PortGroup *)hw)->PMUX[index].reg;
954 tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
955 return tmp;
956}
957
958static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
959{
960 PORT_CRITICAL_SECTION_ENTER();
961 ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
962 PORT_CRITICAL_SECTION_LEAVE();
963}
964
965static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
966 hri_port_pmux_reg_t mask)
967{
968 uint8_t tmp;
969 tmp = ((PortGroup *)hw)->PMUX[index].reg;
970 tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
971 return tmp;
972}
973
974static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
975{
976 uint8_t tmp;
977 PORT_CRITICAL_SECTION_ENTER();
978 tmp = ((PortGroup *)hw)->PMUX[index].reg;
979 tmp &= ~PORT_PMUX_PMUXO_Msk;
980 tmp |= PORT_PMUX_PMUXO(data);
981 ((PortGroup *)hw)->PMUX[index].reg = tmp;
982 PORT_CRITICAL_SECTION_LEAVE();
983}
984
985static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
986{
987 PORT_CRITICAL_SECTION_ENTER();
988 ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
989 PORT_CRITICAL_SECTION_LEAVE();
990}
991
992static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
993{
994 PORT_CRITICAL_SECTION_ENTER();
995 ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
996 PORT_CRITICAL_SECTION_LEAVE();
997}
998
999static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
1000{
1001 uint8_t tmp;
1002 tmp = ((PortGroup *)hw)->PMUX[index].reg;
1003 tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
1004 return tmp;
1005}
1006
1007static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
1008{
1009 PORT_CRITICAL_SECTION_ENTER();
1010 ((PortGroup *)hw)->PMUX[index].reg |= mask;
1011 PORT_CRITICAL_SECTION_LEAVE();
1012}
1013
1014static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
1015 hri_port_pmux_reg_t mask)
1016{
1017 uint8_t tmp;
1018 tmp = ((PortGroup *)hw)->PMUX[index].reg;
1019 tmp &= mask;
1020 return tmp;
1021}
1022
1023static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
1024{
1025 PORT_CRITICAL_SECTION_ENTER();
1026 ((PortGroup *)hw)->PMUX[index].reg = data;
1027 PORT_CRITICAL_SECTION_LEAVE();
1028}
1029
1030static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
1031{
1032 PORT_CRITICAL_SECTION_ENTER();
1033 ((PortGroup *)hw)->PMUX[index].reg &= ~mask;
1034 PORT_CRITICAL_SECTION_LEAVE();
1035}
1036
1037static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
1038{
1039 PORT_CRITICAL_SECTION_ENTER();
1040 ((PortGroup *)hw)->PMUX[index].reg ^= mask;
1041 PORT_CRITICAL_SECTION_LEAVE();
1042}
1043
1044static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
1045{
1046 return ((PortGroup *)hw)->PMUX[index].reg;
1047}
1048
1049static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1050{
1051 PORT_CRITICAL_SECTION_ENTER();
1052 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
1053 PORT_CRITICAL_SECTION_LEAVE();
1054}
1055
1056static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1057{
1058 uint8_t tmp;
1059 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1060 tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
1061 return (bool)tmp;
1062}
1063
1064static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
1065{
1066 uint8_t tmp;
1067 PORT_CRITICAL_SECTION_ENTER();
1068 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1069 tmp &= ~PORT_PINCFG_PMUXEN;
1070 tmp |= value << PORT_PINCFG_PMUXEN_Pos;
1071 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1072 PORT_CRITICAL_SECTION_LEAVE();
1073}
1074
1075static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1076{
1077 PORT_CRITICAL_SECTION_ENTER();
1078 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
1079 PORT_CRITICAL_SECTION_LEAVE();
1080}
1081
1082static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1083{
1084 PORT_CRITICAL_SECTION_ENTER();
1085 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
1086 PORT_CRITICAL_SECTION_LEAVE();
1087}
1088
1089static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1090{
1091 PORT_CRITICAL_SECTION_ENTER();
1092 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
1093 PORT_CRITICAL_SECTION_LEAVE();
1094}
1095
1096static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1097{
1098 uint8_t tmp;
1099 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1100 tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
1101 return (bool)tmp;
1102}
1103
1104static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
1105{
1106 uint8_t tmp;
1107 PORT_CRITICAL_SECTION_ENTER();
1108 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1109 tmp &= ~PORT_PINCFG_INEN;
1110 tmp |= value << PORT_PINCFG_INEN_Pos;
1111 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1112 PORT_CRITICAL_SECTION_LEAVE();
1113}
1114
1115static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1116{
1117 PORT_CRITICAL_SECTION_ENTER();
1118 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
1119 PORT_CRITICAL_SECTION_LEAVE();
1120}
1121
1122static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1123{
1124 PORT_CRITICAL_SECTION_ENTER();
1125 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
1126 PORT_CRITICAL_SECTION_LEAVE();
1127}
1128
1129static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1130{
1131 PORT_CRITICAL_SECTION_ENTER();
1132 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
1133 PORT_CRITICAL_SECTION_LEAVE();
1134}
1135
1136static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1137{
1138 uint8_t tmp;
1139 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1140 tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
1141 return (bool)tmp;
1142}
1143
1144static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
1145{
1146 uint8_t tmp;
1147 PORT_CRITICAL_SECTION_ENTER();
1148 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1149 tmp &= ~PORT_PINCFG_PULLEN;
1150 tmp |= value << PORT_PINCFG_PULLEN_Pos;
1151 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1152 PORT_CRITICAL_SECTION_LEAVE();
1153}
1154
1155static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1156{
1157 PORT_CRITICAL_SECTION_ENTER();
1158 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
1159 PORT_CRITICAL_SECTION_LEAVE();
1160}
1161
1162static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1163{
1164 PORT_CRITICAL_SECTION_ENTER();
1165 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
1166 PORT_CRITICAL_SECTION_LEAVE();
1167}
1168
1169static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1170{
1171 PORT_CRITICAL_SECTION_ENTER();
1172 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
1173 PORT_CRITICAL_SECTION_LEAVE();
1174}
1175
1176static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1177{
1178 uint8_t tmp;
1179 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1180 tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
1181 return (bool)tmp;
1182}
1183
1184static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
1185{
1186 uint8_t tmp;
1187 PORT_CRITICAL_SECTION_ENTER();
1188 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1189 tmp &= ~PORT_PINCFG_DRVSTR;
1190 tmp |= value << PORT_PINCFG_DRVSTR_Pos;
1191 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1192 PORT_CRITICAL_SECTION_LEAVE();
1193}
1194
1195static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1196{
1197 PORT_CRITICAL_SECTION_ENTER();
1198 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
1199 PORT_CRITICAL_SECTION_LEAVE();
1200}
1201
1202static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1203{
1204 PORT_CRITICAL_SECTION_ENTER();
1205 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
1206 PORT_CRITICAL_SECTION_LEAVE();
1207}
1208
1209static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
1210{
1211 PORT_CRITICAL_SECTION_ENTER();
1212 ((PortGroup *)hw)->PINCFG[index].reg |= mask;
1213 PORT_CRITICAL_SECTION_LEAVE();
1214}
1215
1216static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
1217 hri_port_pincfg_reg_t mask)
1218{
1219 uint8_t tmp;
1220 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1221 tmp &= mask;
1222 return tmp;
1223}
1224
1225static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
1226{
1227 PORT_CRITICAL_SECTION_ENTER();
1228 ((PortGroup *)hw)->PINCFG[index].reg = data;
1229 PORT_CRITICAL_SECTION_LEAVE();
1230}
1231
1232static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
1233{
1234 PORT_CRITICAL_SECTION_ENTER();
1235 ((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
1236 PORT_CRITICAL_SECTION_LEAVE();
1237}
1238
1239static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
1240{
1241 PORT_CRITICAL_SECTION_ENTER();
1242 ((PortGroup *)hw)->PINCFG[index].reg ^= mask;
1243 PORT_CRITICAL_SECTION_LEAVE();
1244}
1245
1246static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
1247{
1248 return ((PortGroup *)hw)->PINCFG[index].reg;
1249}
1250
1251static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
1252{
1253 PORT_CRITICAL_SECTION_ENTER();
1254 ((PortGroup *)hw)->WRCONFIG.reg = data;
1255 PORT_CRITICAL_SECTION_LEAVE();
1256}
1257
1258static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1259{
1260 ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask);
1261}
1262
1263static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index,
1264 hri_port_dir_reg_t mask)
1265{
1266 uint32_t tmp;
1267 tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
1268 tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
1269 return tmp;
1270}
1271
1272static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index)
1273{
1274 uint32_t tmp;
1275 tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
1276 tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
1277 return tmp;
1278}
1279
1280static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
1281{
1282 ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data);
1283 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data);
1284}
1285
1286static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1287{
1288 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask);
1289}
1290
1291static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1292{
1293 ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
1294}
1295
1296static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1297{
1298 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
1299}
1300
1301static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
1302 hri_port_dir_reg_t mask)
1303{
1304 uint32_t tmp;
1305 tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
1306 tmp &= mask;
1307 return tmp;
1308}
1309
1310static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
1311{
1312 return ((Port *)hw)->Group[submodule_index].DIR.reg;
1313}
1314
1315static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
1316{
1317 ((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
1318 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
1319}
1320
1321static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1322{
1323 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
1324}
1325
1326static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1327{
1328 ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
1329}
1330
1331static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1332{
1333 ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask);
1334}
1335
1336static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index,
1337 hri_port_out_reg_t mask)
1338{
1339 uint32_t tmp;
1340 tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
1341 tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
1342 return tmp;
1343}
1344
1345static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index)
1346{
1347 uint32_t tmp;
1348 tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
1349 tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
1350 return tmp;
1351}
1352
1353static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
1354{
1355 ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data);
1356 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data);
1357}
1358
1359static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1360{
1361 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask);
1362}
1363
1364static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1365{
1366 ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask);
1367}
1368
1369static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1370{
1371 ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
1372}
1373
1374static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
1375 hri_port_out_reg_t mask)
1376{
1377 uint32_t tmp;
1378 tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
1379 tmp &= mask;
1380 return tmp;
1381}
1382
1383static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
1384{
1385 return ((Port *)hw)->Group[submodule_index].OUT.reg;
1386}
1387
1388static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
1389{
1390 ((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
1391 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
1392}
1393
1394static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1395{
1396 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
1397}
1398
1399static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1400{
1401 ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
1402}
1403
1404static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index,
1405 hri_port_in_reg_t mask)
1406{
1407 return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
1408}
1409
1410static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index)
1411{
1412 return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
1413}
1414
1415static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
1416 hri_port_in_reg_t mask)
1417{
1418 uint32_t tmp;
1419 tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
1420 tmp &= mask;
1421 return tmp;
1422}
1423
1424static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
1425{
1426 return ((Port *)hw)->Group[submodule_index].IN.reg;
1427}
1428
1429static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1430 hri_port_ctrl_reg_t mask)
1431{
1432 PORT_CRITICAL_SECTION_ENTER();
1433 ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
1434 PORT_CRITICAL_SECTION_LEAVE();
1435}
1436
1437static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1438 hri_port_ctrl_reg_t mask)
1439{
1440 uint32_t tmp;
1441 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1442 tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
1443 return tmp;
1444}
1445
1446static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1447 hri_port_ctrl_reg_t data)
1448{
1449 uint32_t tmp;
1450 PORT_CRITICAL_SECTION_ENTER();
1451 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1452 tmp &= ~PORT_CTRL_SAMPLING_Msk;
1453 tmp |= PORT_CTRL_SAMPLING(data);
1454 ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
1455 PORT_CRITICAL_SECTION_LEAVE();
1456}
1457
1458static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1459 hri_port_ctrl_reg_t mask)
1460{
1461 PORT_CRITICAL_SECTION_ENTER();
1462 ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
1463 PORT_CRITICAL_SECTION_LEAVE();
1464}
1465
1466static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1467 hri_port_ctrl_reg_t mask)
1468{
1469 PORT_CRITICAL_SECTION_ENTER();
1470 ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
1471 PORT_CRITICAL_SECTION_LEAVE();
1472}
1473
1474static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
1475{
1476 uint32_t tmp;
1477 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1478 tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
1479 return tmp;
1480}
1481
1482static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
1483{
1484 PORT_CRITICAL_SECTION_ENTER();
1485 ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
1486 PORT_CRITICAL_SECTION_LEAVE();
1487}
1488
1489static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
1490 hri_port_ctrl_reg_t mask)
1491{
1492 uint32_t tmp;
1493 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1494 tmp &= mask;
1495 return tmp;
1496}
1497
1498static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
1499{
1500 PORT_CRITICAL_SECTION_ENTER();
1501 ((Port *)hw)->Group[submodule_index].CTRL.reg = data;
1502 PORT_CRITICAL_SECTION_LEAVE();
1503}
1504
1505static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
1506{
1507 PORT_CRITICAL_SECTION_ENTER();
1508 ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
1509 PORT_CRITICAL_SECTION_LEAVE();
1510}
1511
1512static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
1513{
1514 PORT_CRITICAL_SECTION_ENTER();
1515 ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
1516 PORT_CRITICAL_SECTION_LEAVE();
1517}
1518
1519static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
1520{
1521 return ((Port *)hw)->Group[submodule_index].CTRL.reg;
1522}
1523
1524static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1525{
1526 PORT_CRITICAL_SECTION_ENTER();
1527 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
1528 PORT_CRITICAL_SECTION_LEAVE();
1529}
1530
1531static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1532{
1533 uint32_t tmp;
1534 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1535 tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
1536 return (bool)tmp;
1537}
1538
1539static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
1540{
1541 uint32_t tmp;
1542 PORT_CRITICAL_SECTION_ENTER();
1543 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1544 tmp &= ~PORT_EVCTRL_PORTEI0;
1545 tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
1546 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1547 PORT_CRITICAL_SECTION_LEAVE();
1548}
1549
1550static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1551{
1552 PORT_CRITICAL_SECTION_ENTER();
1553 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
1554 PORT_CRITICAL_SECTION_LEAVE();
1555}
1556
1557static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1558{
1559 PORT_CRITICAL_SECTION_ENTER();
1560 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
1561 PORT_CRITICAL_SECTION_LEAVE();
1562}
1563
1564static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1565{
1566 PORT_CRITICAL_SECTION_ENTER();
1567 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
1568 PORT_CRITICAL_SECTION_LEAVE();
1569}
1570
1571static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1572{
1573 uint32_t tmp;
1574 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1575 tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
1576 return (bool)tmp;
1577}
1578
1579static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
1580{
1581 uint32_t tmp;
1582 PORT_CRITICAL_SECTION_ENTER();
1583 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1584 tmp &= ~PORT_EVCTRL_PORTEI1;
1585 tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
1586 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1587 PORT_CRITICAL_SECTION_LEAVE();
1588}
1589
1590static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1591{
1592 PORT_CRITICAL_SECTION_ENTER();
1593 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
1594 PORT_CRITICAL_SECTION_LEAVE();
1595}
1596
1597static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1598{
1599 PORT_CRITICAL_SECTION_ENTER();
1600 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
1601 PORT_CRITICAL_SECTION_LEAVE();
1602}
1603
1604static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1605{
1606 PORT_CRITICAL_SECTION_ENTER();
1607 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
1608 PORT_CRITICAL_SECTION_LEAVE();
1609}
1610
1611static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1612{
1613 uint32_t tmp;
1614 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1615 tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
1616 return (bool)tmp;
1617}
1618
1619static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
1620{
1621 uint32_t tmp;
1622 PORT_CRITICAL_SECTION_ENTER();
1623 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1624 tmp &= ~PORT_EVCTRL_PORTEI2;
1625 tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
1626 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1627 PORT_CRITICAL_SECTION_LEAVE();
1628}
1629
1630static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1631{
1632 PORT_CRITICAL_SECTION_ENTER();
1633 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
1634 PORT_CRITICAL_SECTION_LEAVE();
1635}
1636
1637static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1638{
1639 PORT_CRITICAL_SECTION_ENTER();
1640 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
1641 PORT_CRITICAL_SECTION_LEAVE();
1642}
1643
1644static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1645{
1646 PORT_CRITICAL_SECTION_ENTER();
1647 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
1648 PORT_CRITICAL_SECTION_LEAVE();
1649}
1650
1651static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1652{
1653 uint32_t tmp;
1654 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1655 tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
1656 return (bool)tmp;
1657}
1658
1659static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
1660{
1661 uint32_t tmp;
1662 PORT_CRITICAL_SECTION_ENTER();
1663 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1664 tmp &= ~PORT_EVCTRL_PORTEI3;
1665 tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
1666 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1667 PORT_CRITICAL_SECTION_LEAVE();
1668}
1669
1670static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1671{
1672 PORT_CRITICAL_SECTION_ENTER();
1673 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
1674 PORT_CRITICAL_SECTION_LEAVE();
1675}
1676
1677static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1678{
1679 PORT_CRITICAL_SECTION_ENTER();
1680 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
1681 PORT_CRITICAL_SECTION_LEAVE();
1682}
1683
1684static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1685 hri_port_evctrl_reg_t mask)
1686{
1687 PORT_CRITICAL_SECTION_ENTER();
1688 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
1689 PORT_CRITICAL_SECTION_LEAVE();
1690}
1691
1692static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1693 hri_port_evctrl_reg_t mask)
1694{
1695 uint32_t tmp;
1696 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1697 tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
1698 return tmp;
1699}
1700
1701static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1702 hri_port_evctrl_reg_t data)
1703{
1704 uint32_t tmp;
1705 PORT_CRITICAL_SECTION_ENTER();
1706 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1707 tmp &= ~PORT_EVCTRL_PID0_Msk;
1708 tmp |= PORT_EVCTRL_PID0(data);
1709 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1710 PORT_CRITICAL_SECTION_LEAVE();
1711}
1712
1713static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1714 hri_port_evctrl_reg_t mask)
1715{
1716 PORT_CRITICAL_SECTION_ENTER();
1717 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
1718 PORT_CRITICAL_SECTION_LEAVE();
1719}
1720
1721static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1722 hri_port_evctrl_reg_t mask)
1723{
1724 PORT_CRITICAL_SECTION_ENTER();
1725 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
1726 PORT_CRITICAL_SECTION_LEAVE();
1727}
1728
1729static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
1730{
1731 uint32_t tmp;
1732 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1733 tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
1734 return tmp;
1735}
1736
1737static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1738 hri_port_evctrl_reg_t mask)
1739{
1740 PORT_CRITICAL_SECTION_ENTER();
1741 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
1742 PORT_CRITICAL_SECTION_LEAVE();
1743}
1744
1745static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1746 hri_port_evctrl_reg_t mask)
1747{
1748 uint32_t tmp;
1749 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1750 tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
1751 return tmp;
1752}
1753
1754static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1755 hri_port_evctrl_reg_t data)
1756{
1757 uint32_t tmp;
1758 PORT_CRITICAL_SECTION_ENTER();
1759 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1760 tmp &= ~PORT_EVCTRL_EVACT0_Msk;
1761 tmp |= PORT_EVCTRL_EVACT0(data);
1762 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1763 PORT_CRITICAL_SECTION_LEAVE();
1764}
1765
1766static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1767 hri_port_evctrl_reg_t mask)
1768{
1769 PORT_CRITICAL_SECTION_ENTER();
1770 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
1771 PORT_CRITICAL_SECTION_LEAVE();
1772}
1773
1774static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1775 hri_port_evctrl_reg_t mask)
1776{
1777 PORT_CRITICAL_SECTION_ENTER();
1778 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
1779 PORT_CRITICAL_SECTION_LEAVE();
1780}
1781
1782static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
1783{
1784 uint32_t tmp;
1785 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1786 tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
1787 return tmp;
1788}
1789
1790static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1791 hri_port_evctrl_reg_t mask)
1792{
1793 PORT_CRITICAL_SECTION_ENTER();
1794 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
1795 PORT_CRITICAL_SECTION_LEAVE();
1796}
1797
1798static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1799 hri_port_evctrl_reg_t mask)
1800{
1801 uint32_t tmp;
1802 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1803 tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
1804 return tmp;
1805}
1806
1807static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1808 hri_port_evctrl_reg_t data)
1809{
1810 uint32_t tmp;
1811 PORT_CRITICAL_SECTION_ENTER();
1812 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1813 tmp &= ~PORT_EVCTRL_PID1_Msk;
1814 tmp |= PORT_EVCTRL_PID1(data);
1815 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1816 PORT_CRITICAL_SECTION_LEAVE();
1817}
1818
1819static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1820 hri_port_evctrl_reg_t mask)
1821{
1822 PORT_CRITICAL_SECTION_ENTER();
1823 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
1824 PORT_CRITICAL_SECTION_LEAVE();
1825}
1826
1827static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1828 hri_port_evctrl_reg_t mask)
1829{
1830 PORT_CRITICAL_SECTION_ENTER();
1831 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
1832 PORT_CRITICAL_SECTION_LEAVE();
1833}
1834
1835static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
1836{
1837 uint32_t tmp;
1838 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1839 tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
1840 return tmp;
1841}
1842
1843static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1844 hri_port_evctrl_reg_t mask)
1845{
1846 PORT_CRITICAL_SECTION_ENTER();
1847 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
1848 PORT_CRITICAL_SECTION_LEAVE();
1849}
1850
1851static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1852 hri_port_evctrl_reg_t mask)
1853{
1854 uint32_t tmp;
1855 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1856 tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
1857 return tmp;
1858}
1859
1860static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1861 hri_port_evctrl_reg_t data)
1862{
1863 uint32_t tmp;
1864 PORT_CRITICAL_SECTION_ENTER();
1865 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1866 tmp &= ~PORT_EVCTRL_EVACT1_Msk;
1867 tmp |= PORT_EVCTRL_EVACT1(data);
1868 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1869 PORT_CRITICAL_SECTION_LEAVE();
1870}
1871
1872static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1873 hri_port_evctrl_reg_t mask)
1874{
1875 PORT_CRITICAL_SECTION_ENTER();
1876 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
1877 PORT_CRITICAL_SECTION_LEAVE();
1878}
1879
1880static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1881 hri_port_evctrl_reg_t mask)
1882{
1883 PORT_CRITICAL_SECTION_ENTER();
1884 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
1885 PORT_CRITICAL_SECTION_LEAVE();
1886}
1887
1888static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
1889{
1890 uint32_t tmp;
1891 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1892 tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
1893 return tmp;
1894}
1895
1896static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1897 hri_port_evctrl_reg_t mask)
1898{
1899 PORT_CRITICAL_SECTION_ENTER();
1900 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
1901 PORT_CRITICAL_SECTION_LEAVE();
1902}
1903
1904static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1905 hri_port_evctrl_reg_t mask)
1906{
1907 uint32_t tmp;
1908 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1909 tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
1910 return tmp;
1911}
1912
1913static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1914 hri_port_evctrl_reg_t data)
1915{
1916 uint32_t tmp;
1917 PORT_CRITICAL_SECTION_ENTER();
1918 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1919 tmp &= ~PORT_EVCTRL_PID2_Msk;
1920 tmp |= PORT_EVCTRL_PID2(data);
1921 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1922 PORT_CRITICAL_SECTION_LEAVE();
1923}
1924
1925static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1926 hri_port_evctrl_reg_t mask)
1927{
1928 PORT_CRITICAL_SECTION_ENTER();
1929 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
1930 PORT_CRITICAL_SECTION_LEAVE();
1931}
1932
1933static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1934 hri_port_evctrl_reg_t mask)
1935{
1936 PORT_CRITICAL_SECTION_ENTER();
1937 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
1938 PORT_CRITICAL_SECTION_LEAVE();
1939}
1940
1941static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
1942{
1943 uint32_t tmp;
1944 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1945 tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
1946 return tmp;
1947}
1948
1949static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1950 hri_port_evctrl_reg_t mask)
1951{
1952 PORT_CRITICAL_SECTION_ENTER();
1953 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
1954 PORT_CRITICAL_SECTION_LEAVE();
1955}
1956
1957static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1958 hri_port_evctrl_reg_t mask)
1959{
1960 uint32_t tmp;
1961 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1962 tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
1963 return tmp;
1964}
1965
1966static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1967 hri_port_evctrl_reg_t data)
1968{
1969 uint32_t tmp;
1970 PORT_CRITICAL_SECTION_ENTER();
1971 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1972 tmp &= ~PORT_EVCTRL_EVACT2_Msk;
1973 tmp |= PORT_EVCTRL_EVACT2(data);
1974 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1975 PORT_CRITICAL_SECTION_LEAVE();
1976}
1977
1978static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1979 hri_port_evctrl_reg_t mask)
1980{
1981 PORT_CRITICAL_SECTION_ENTER();
1982 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
1983 PORT_CRITICAL_SECTION_LEAVE();
1984}
1985
1986static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1987 hri_port_evctrl_reg_t mask)
1988{
1989 PORT_CRITICAL_SECTION_ENTER();
1990 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
1991 PORT_CRITICAL_SECTION_LEAVE();
1992}
1993
1994static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
1995{
1996 uint32_t tmp;
1997 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1998 tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
1999 return tmp;
2000}
2001
2002static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2003 hri_port_evctrl_reg_t mask)
2004{
2005 PORT_CRITICAL_SECTION_ENTER();
2006 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
2007 PORT_CRITICAL_SECTION_LEAVE();
2008}
2009
2010static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2011 hri_port_evctrl_reg_t mask)
2012{
2013 uint32_t tmp;
2014 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2015 tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
2016 return tmp;
2017}
2018
2019static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2020 hri_port_evctrl_reg_t data)
2021{
2022 uint32_t tmp;
2023 PORT_CRITICAL_SECTION_ENTER();
2024 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2025 tmp &= ~PORT_EVCTRL_PID3_Msk;
2026 tmp |= PORT_EVCTRL_PID3(data);
2027 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
2028 PORT_CRITICAL_SECTION_LEAVE();
2029}
2030
2031static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2032 hri_port_evctrl_reg_t mask)
2033{
2034 PORT_CRITICAL_SECTION_ENTER();
2035 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
2036 PORT_CRITICAL_SECTION_LEAVE();
2037}
2038
2039static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2040 hri_port_evctrl_reg_t mask)
2041{
2042 PORT_CRITICAL_SECTION_ENTER();
2043 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
2044 PORT_CRITICAL_SECTION_LEAVE();
2045}
2046
2047static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
2048{
2049 uint32_t tmp;
2050 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2051 tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
2052 return tmp;
2053}
2054
2055static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2056 hri_port_evctrl_reg_t mask)
2057{
2058 PORT_CRITICAL_SECTION_ENTER();
2059 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
2060 PORT_CRITICAL_SECTION_LEAVE();
2061}
2062
2063static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2064 hri_port_evctrl_reg_t mask)
2065{
2066 uint32_t tmp;
2067 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2068 tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
2069 return tmp;
2070}
2071
2072static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2073 hri_port_evctrl_reg_t data)
2074{
2075 uint32_t tmp;
2076 PORT_CRITICAL_SECTION_ENTER();
2077 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2078 tmp &= ~PORT_EVCTRL_EVACT3_Msk;
2079 tmp |= PORT_EVCTRL_EVACT3(data);
2080 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
2081 PORT_CRITICAL_SECTION_LEAVE();
2082}
2083
2084static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2085 hri_port_evctrl_reg_t mask)
2086{
2087 PORT_CRITICAL_SECTION_ENTER();
2088 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
2089 PORT_CRITICAL_SECTION_LEAVE();
2090}
2091
2092static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2093 hri_port_evctrl_reg_t mask)
2094{
2095 PORT_CRITICAL_SECTION_ENTER();
2096 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
2097 PORT_CRITICAL_SECTION_LEAVE();
2098}
2099
2100static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
2101{
2102 uint32_t tmp;
2103 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2104 tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
2105 return tmp;
2106}
2107
2108static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
2109{
2110 PORT_CRITICAL_SECTION_ENTER();
2111 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
2112 PORT_CRITICAL_SECTION_LEAVE();
2113}
2114
2115static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
2116 hri_port_evctrl_reg_t mask)
2117{
2118 uint32_t tmp;
2119 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2120 tmp &= mask;
2121 return tmp;
2122}
2123
2124static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
2125{
2126 PORT_CRITICAL_SECTION_ENTER();
2127 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
2128 PORT_CRITICAL_SECTION_LEAVE();
2129}
2130
2131static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
2132{
2133 PORT_CRITICAL_SECTION_ENTER();
2134 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
2135 PORT_CRITICAL_SECTION_LEAVE();
2136}
2137
2138static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
2139{
2140 PORT_CRITICAL_SECTION_ENTER();
2141 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
2142 PORT_CRITICAL_SECTION_LEAVE();
2143}
2144
2145static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
2146{
2147 return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2148}
2149
2150static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2151 hri_port_pmux_reg_t mask)
2152{
2153 PORT_CRITICAL_SECTION_ENTER();
2154 ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
2155 PORT_CRITICAL_SECTION_LEAVE();
2156}
2157
2158static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
2159 uint8_t index, hri_port_pmux_reg_t mask)
2160{
2161 uint8_t tmp;
2162 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2163 tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
2164 return tmp;
2165}
2166
2167static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2168 hri_port_pmux_reg_t data)
2169{
2170 uint8_t tmp;
2171 PORT_CRITICAL_SECTION_ENTER();
2172 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2173 tmp &= ~PORT_PMUX_PMUXE_Msk;
2174 tmp |= PORT_PMUX_PMUXE(data);
2175 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
2176 PORT_CRITICAL_SECTION_LEAVE();
2177}
2178
2179static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2180 hri_port_pmux_reg_t mask)
2181{
2182 PORT_CRITICAL_SECTION_ENTER();
2183 ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
2184 PORT_CRITICAL_SECTION_LEAVE();
2185}
2186
2187static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2188 hri_port_pmux_reg_t mask)
2189{
2190 PORT_CRITICAL_SECTION_ENTER();
2191 ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
2192 PORT_CRITICAL_SECTION_LEAVE();
2193}
2194
2195static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
2196 uint8_t index)
2197{
2198 uint8_t tmp;
2199 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2200 tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
2201 return tmp;
2202}
2203
2204static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2205 hri_port_pmux_reg_t mask)
2206{
2207 PORT_CRITICAL_SECTION_ENTER();
2208 ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
2209 PORT_CRITICAL_SECTION_LEAVE();
2210}
2211
2212static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
2213 uint8_t index, hri_port_pmux_reg_t mask)
2214{
2215 uint8_t tmp;
2216 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2217 tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
2218 return tmp;
2219}
2220
2221static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2222 hri_port_pmux_reg_t data)
2223{
2224 uint8_t tmp;
2225 PORT_CRITICAL_SECTION_ENTER();
2226 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2227 tmp &= ~PORT_PMUX_PMUXO_Msk;
2228 tmp |= PORT_PMUX_PMUXO(data);
2229 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
2230 PORT_CRITICAL_SECTION_LEAVE();
2231}
2232
2233static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2234 hri_port_pmux_reg_t mask)
2235{
2236 PORT_CRITICAL_SECTION_ENTER();
2237 ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
2238 PORT_CRITICAL_SECTION_LEAVE();
2239}
2240
2241static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2242 hri_port_pmux_reg_t mask)
2243{
2244 PORT_CRITICAL_SECTION_ENTER();
2245 ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
2246 PORT_CRITICAL_SECTION_LEAVE();
2247}
2248
2249static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
2250 uint8_t index)
2251{
2252 uint8_t tmp;
2253 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2254 tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
2255 return tmp;
2256}
2257
2258static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2259 hri_port_pmux_reg_t mask)
2260{
2261 PORT_CRITICAL_SECTION_ENTER();
2262 ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
2263 PORT_CRITICAL_SECTION_LEAVE();
2264}
2265
2266static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2267 hri_port_pmux_reg_t mask)
2268{
2269 uint8_t tmp;
2270 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2271 tmp &= mask;
2272 return tmp;
2273}
2274
2275static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2276 hri_port_pmux_reg_t data)
2277{
2278 PORT_CRITICAL_SECTION_ENTER();
2279 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
2280 PORT_CRITICAL_SECTION_LEAVE();
2281}
2282
2283static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2284 hri_port_pmux_reg_t mask)
2285{
2286 PORT_CRITICAL_SECTION_ENTER();
2287 ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
2288 PORT_CRITICAL_SECTION_LEAVE();
2289}
2290
2291static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2292 hri_port_pmux_reg_t mask)
2293{
2294 PORT_CRITICAL_SECTION_ENTER();
2295 ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
2296 PORT_CRITICAL_SECTION_LEAVE();
2297}
2298
2299static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
2300{
2301 return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2302}
2303
2304static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2305{
2306 PORT_CRITICAL_SECTION_ENTER();
2307 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
2308 PORT_CRITICAL_SECTION_LEAVE();
2309}
2310
2311static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2312{
2313 uint8_t tmp;
2314 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2315 tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
2316 return (bool)tmp;
2317}
2318
2319static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2320 bool value)
2321{
2322 uint8_t tmp;
2323 PORT_CRITICAL_SECTION_ENTER();
2324 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2325 tmp &= ~PORT_PINCFG_PMUXEN;
2326 tmp |= value << PORT_PINCFG_PMUXEN_Pos;
2327 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2328 PORT_CRITICAL_SECTION_LEAVE();
2329}
2330
2331static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2332{
2333 PORT_CRITICAL_SECTION_ENTER();
2334 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
2335 PORT_CRITICAL_SECTION_LEAVE();
2336}
2337
2338static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2339{
2340 PORT_CRITICAL_SECTION_ENTER();
2341 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
2342 PORT_CRITICAL_SECTION_LEAVE();
2343}
2344
2345static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2346{
2347 PORT_CRITICAL_SECTION_ENTER();
2348 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
2349 PORT_CRITICAL_SECTION_LEAVE();
2350}
2351
2352static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2353{
2354 uint8_t tmp;
2355 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2356 tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
2357 return (bool)tmp;
2358}
2359
2360static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2361 bool value)
2362{
2363 uint8_t tmp;
2364 PORT_CRITICAL_SECTION_ENTER();
2365 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2366 tmp &= ~PORT_PINCFG_INEN;
2367 tmp |= value << PORT_PINCFG_INEN_Pos;
2368 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2369 PORT_CRITICAL_SECTION_LEAVE();
2370}
2371
2372static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2373{
2374 PORT_CRITICAL_SECTION_ENTER();
2375 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
2376 PORT_CRITICAL_SECTION_LEAVE();
2377}
2378
2379static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2380{
2381 PORT_CRITICAL_SECTION_ENTER();
2382 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
2383 PORT_CRITICAL_SECTION_LEAVE();
2384}
2385
2386static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2387{
2388 PORT_CRITICAL_SECTION_ENTER();
2389 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
2390 PORT_CRITICAL_SECTION_LEAVE();
2391}
2392
2393static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2394{
2395 uint8_t tmp;
2396 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2397 tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
2398 return (bool)tmp;
2399}
2400
2401static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2402 bool value)
2403{
2404 uint8_t tmp;
2405 PORT_CRITICAL_SECTION_ENTER();
2406 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2407 tmp &= ~PORT_PINCFG_PULLEN;
2408 tmp |= value << PORT_PINCFG_PULLEN_Pos;
2409 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2410 PORT_CRITICAL_SECTION_LEAVE();
2411}
2412
2413static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2414{
2415 PORT_CRITICAL_SECTION_ENTER();
2416 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
2417 PORT_CRITICAL_SECTION_LEAVE();
2418}
2419
2420static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2421{
2422 PORT_CRITICAL_SECTION_ENTER();
2423 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
2424 PORT_CRITICAL_SECTION_LEAVE();
2425}
2426
2427static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2428{
2429 PORT_CRITICAL_SECTION_ENTER();
2430 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
2431 PORT_CRITICAL_SECTION_LEAVE();
2432}
2433
2434static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2435{
2436 uint8_t tmp;
2437 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2438 tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
2439 return (bool)tmp;
2440}
2441
2442static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2443 bool value)
2444{
2445 uint8_t tmp;
2446 PORT_CRITICAL_SECTION_ENTER();
2447 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2448 tmp &= ~PORT_PINCFG_DRVSTR;
2449 tmp |= value << PORT_PINCFG_DRVSTR_Pos;
2450 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2451 PORT_CRITICAL_SECTION_LEAVE();
2452}
2453
2454static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2455{
2456 PORT_CRITICAL_SECTION_ENTER();
2457 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
2458 PORT_CRITICAL_SECTION_LEAVE();
2459}
2460
2461static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2462{
2463 PORT_CRITICAL_SECTION_ENTER();
2464 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
2465 PORT_CRITICAL_SECTION_LEAVE();
2466}
2467
2468static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2469 hri_port_pincfg_reg_t mask)
2470{
2471 PORT_CRITICAL_SECTION_ENTER();
2472 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
2473 PORT_CRITICAL_SECTION_LEAVE();
2474}
2475
2476static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
2477 uint8_t index, hri_port_pincfg_reg_t mask)
2478{
2479 uint8_t tmp;
2480 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2481 tmp &= mask;
2482 return tmp;
2483}
2484
2485static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2486 hri_port_pincfg_reg_t data)
2487{
2488 PORT_CRITICAL_SECTION_ENTER();
2489 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
2490 PORT_CRITICAL_SECTION_LEAVE();
2491}
2492
2493static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2494 hri_port_pincfg_reg_t mask)
2495{
2496 PORT_CRITICAL_SECTION_ENTER();
2497 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
2498 PORT_CRITICAL_SECTION_LEAVE();
2499}
2500
2501static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2502 hri_port_pincfg_reg_t mask)
2503{
2504 PORT_CRITICAL_SECTION_ENTER();
2505 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
2506 PORT_CRITICAL_SECTION_LEAVE();
2507}
2508
2509static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
2510 uint8_t index)
2511{
2512 return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2513}
2514
2515static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
2516 hri_port_wrconfig_reg_t data)
2517{
2518 PORT_CRITICAL_SECTION_ENTER();
2519 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
2520 PORT_CRITICAL_SECTION_LEAVE();
2521}
2522
2523#ifdef __cplusplus
2524}
2525#endif
2526
2527#endif /* _HRI_PORT_E54_H_INCLUDED */
2528#endif /* _SAME54_PORT_COMPONENT_ */