| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Generic RAMECC related functionality. |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #include <utils.h> |
| 35 | #include <utils_assert.h> |
| 36 | #include <hpl_ramecc.h> |
| 37 | |
| 38 | /* RAMECC device descriptor */ |
| 39 | struct _ramecc_device device; |
| 40 | |
| 41 | /** |
| 42 | * \brief Initialize RAMECC |
| 43 | */ |
| 44 | int32_t _ramecc_init(void) |
| 45 | { |
| 46 | if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { |
| 47 | return ERR_ABORTED; |
| 48 | } |
| 49 | |
| 50 | NVIC_DisableIRQ(RAMECC_IRQn); |
| 51 | NVIC_ClearPendingIRQ(RAMECC_IRQn); |
| 52 | NVIC_EnableIRQ(RAMECC_IRQn); |
| 53 | |
| 54 | return ERR_NONE; |
| 55 | } |
| 56 | |
| 57 | void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) |
| 58 | { |
| 59 | if (RAMECC_DUAL_ERROR_CB == type) { |
| 60 | device.ramecc_cb.dual_bit_err = cb; |
| 61 | hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); |
| 62 | } else if (RAMECC_SINGLE_ERROR_CB == type) { |
| 63 | device.ramecc_cb.single_bit_err = cb; |
| 64 | hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | /** |
| 69 | * \internal RAMECC interrupt handler |
| 70 | */ |
| 71 | void RAMECC_Handler(void) |
| 72 | { |
| 73 | struct _ramecc_device *dev = (struct _ramecc_device *)&device; |
| 74 | volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); |
| 75 | |
| 76 | if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { |
| 77 | dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); |
| 78 | } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { |
| 79 | dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); |
| 80 | } else { |
| 81 | return; |
| 82 | } |
| 83 | } |