Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for PAC |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_PAC_COMPONENT_ |
| 31 | #define _SAME54_PAC_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR PAC */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_PAC Peripheral Access Controller */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define PAC_U2120 |
| 40 | #define REV_PAC 0x120 |
| 41 | |
| 42 | /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ |
| 47 | uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ |
| 48 | uint32_t :8; /*!< bit: 24..31 Reserved */ |
| 49 | } bit; /*!< Structure used for bit access */ |
| 50 | uint32_t reg; /*!< Type used for register access */ |
| 51 | } PAC_WRCTRL_Type; |
| 52 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 53 | |
| 54 | #define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ |
| 55 | #define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */ |
| 56 | |
| 57 | #define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ |
| 58 | #define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos) |
| 59 | #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos)) |
| 60 | #define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ |
| 61 | #define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos) |
| 62 | #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos)) |
| 63 | #define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */ |
| 64 | #define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */ |
| 65 | #define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */ |
| 66 | #define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */ |
| 67 | #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) |
| 68 | #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) |
| 69 | #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) |
| 70 | #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) |
| 71 | #define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */ |
| 72 | |
| 73 | /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ |
| 74 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 75 | typedef union { |
| 76 | struct { |
| 77 | uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ |
| 78 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 79 | } bit; /*!< Structure used for bit access */ |
| 80 | uint8_t reg; /*!< Type used for register access */ |
| 81 | } PAC_EVCTRL_Type; |
| 82 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 83 | |
| 84 | #define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ |
| 85 | #define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */ |
| 86 | |
| 87 | #define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ |
| 88 | #define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos) |
| 89 | #define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */ |
| 90 | |
| 91 | /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ |
| 92 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 93 | typedef union { |
| 94 | struct { |
| 95 | uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ |
| 96 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 97 | } bit; /*!< Structure used for bit access */ |
| 98 | uint8_t reg; /*!< Type used for register access */ |
| 99 | } PAC_INTENCLR_Type; |
| 100 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 101 | |
| 102 | #define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ |
| 103 | #define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ |
| 104 | |
| 105 | #define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ |
| 106 | #define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos) |
| 107 | #define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */ |
| 108 | |
| 109 | /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ |
| 110 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 111 | typedef union { |
| 112 | struct { |
| 113 | uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ |
| 114 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 115 | } bit; /*!< Structure used for bit access */ |
| 116 | uint8_t reg; /*!< Type used for register access */ |
| 117 | } PAC_INTENSET_Type; |
| 118 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 119 | |
| 120 | #define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ |
| 121 | #define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ |
| 122 | |
| 123 | #define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ |
| 124 | #define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos) |
| 125 | #define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */ |
| 126 | |
| 127 | /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ |
| 128 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 129 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 130 | struct { |
| 131 | __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */ |
| 132 | __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */ |
| 133 | __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */ |
| 134 | __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */ |
| 135 | __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */ |
| 136 | __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */ |
| 137 | __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */ |
| 138 | __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */ |
| 139 | __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */ |
| 140 | __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */ |
| 141 | __I uint32_t HPB3_:1; /*!< bit: 10 HPB3 */ |
| 142 | __I uint32_t PUKCC_:1; /*!< bit: 11 PUKCC */ |
| 143 | __I uint32_t SDHC0_:1; /*!< bit: 12 SDHC0 */ |
| 144 | __I uint32_t SDHC1_:1; /*!< bit: 13 SDHC1 */ |
| 145 | __I uint32_t QSPI_:1; /*!< bit: 14 QSPI */ |
| 146 | __I uint32_t BKUPRAM_:1; /*!< bit: 15 BKUPRAM */ |
| 147 | __I uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 148 | } bit; /*!< Structure used for bit access */ |
| 149 | uint32_t reg; /*!< Type used for register access */ |
| 150 | } PAC_INTFLAGAHB_Type; |
| 151 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 152 | |
| 153 | #define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ |
| 154 | #define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ |
| 155 | |
| 156 | #define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ |
| 157 | #define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos) |
| 158 | #define PAC_INTFLAGAHB_FLASH_ALT_Pos 1 /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */ |
| 159 | #define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos) |
| 160 | #define PAC_INTFLAGAHB_SEEPROM_Pos 2 /**< \brief (PAC_INTFLAGAHB) SEEPROM */ |
| 161 | #define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos) |
| 162 | #define PAC_INTFLAGAHB_RAMCM4S_Pos 3 /**< \brief (PAC_INTFLAGAHB) RAMCM4S */ |
| 163 | #define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos) |
| 164 | #define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4 /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */ |
| 165 | #define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos) |
| 166 | #define PAC_INTFLAGAHB_RAMDMAWR_Pos 5 /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */ |
| 167 | #define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos) |
| 168 | #define PAC_INTFLAGAHB_RAMDMACICM_Pos 6 /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */ |
| 169 | #define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos) |
| 170 | #define PAC_INTFLAGAHB_HPB0_Pos 7 /**< \brief (PAC_INTFLAGAHB) HPB0 */ |
| 171 | #define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos) |
| 172 | #define PAC_INTFLAGAHB_HPB1_Pos 8 /**< \brief (PAC_INTFLAGAHB) HPB1 */ |
| 173 | #define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos) |
| 174 | #define PAC_INTFLAGAHB_HPB2_Pos 9 /**< \brief (PAC_INTFLAGAHB) HPB2 */ |
| 175 | #define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos) |
| 176 | #define PAC_INTFLAGAHB_HPB3_Pos 10 /**< \brief (PAC_INTFLAGAHB) HPB3 */ |
| 177 | #define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos) |
| 178 | #define PAC_INTFLAGAHB_PUKCC_Pos 11 /**< \brief (PAC_INTFLAGAHB) PUKCC */ |
| 179 | #define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos) |
| 180 | #define PAC_INTFLAGAHB_SDHC0_Pos 12 /**< \brief (PAC_INTFLAGAHB) SDHC0 */ |
| 181 | #define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos) |
| 182 | #define PAC_INTFLAGAHB_SDHC1_Pos 13 /**< \brief (PAC_INTFLAGAHB) SDHC1 */ |
| 183 | #define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos) |
| 184 | #define PAC_INTFLAGAHB_QSPI_Pos 14 /**< \brief (PAC_INTFLAGAHB) QSPI */ |
| 185 | #define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos) |
| 186 | #define PAC_INTFLAGAHB_BKUPRAM_Pos 15 /**< \brief (PAC_INTFLAGAHB) BKUPRAM */ |
| 187 | #define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos) |
| 188 | #define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */ |
| 189 | |
| 190 | /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ |
| 191 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 192 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 193 | struct { |
| 194 | __I uint32_t PAC_:1; /*!< bit: 0 PAC */ |
| 195 | __I uint32_t PM_:1; /*!< bit: 1 PM */ |
| 196 | __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */ |
| 197 | __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */ |
| 198 | __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */ |
| 199 | __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */ |
| 200 | __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */ |
| 201 | __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */ |
| 202 | __I uint32_t WDT_:1; /*!< bit: 8 WDT */ |
| 203 | __I uint32_t RTC_:1; /*!< bit: 9 RTC */ |
| 204 | __I uint32_t EIC_:1; /*!< bit: 10 EIC */ |
| 205 | __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */ |
| 206 | __I uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 */ |
| 207 | __I uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 */ |
| 208 | __I uint32_t TC0_:1; /*!< bit: 14 TC0 */ |
| 209 | __I uint32_t TC1_:1; /*!< bit: 15 TC1 */ |
| 210 | __I uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 211 | } bit; /*!< Structure used for bit access */ |
| 212 | uint32_t reg; /*!< Type used for register access */ |
| 213 | } PAC_INTFLAGA_Type; |
| 214 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 215 | |
| 216 | #define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ |
| 217 | #define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ |
| 218 | |
| 219 | #define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */ |
| 220 | #define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos) |
| 221 | #define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */ |
| 222 | #define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos) |
| 223 | #define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */ |
| 224 | #define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos) |
| 225 | #define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */ |
| 226 | #define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos) |
| 227 | #define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */ |
| 228 | #define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) |
| 229 | #define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ |
| 230 | #define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) |
| 231 | #define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */ |
| 232 | #define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos) |
| 233 | #define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */ |
| 234 | #define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos) |
| 235 | #define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */ |
| 236 | #define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos) |
| 237 | #define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */ |
| 238 | #define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos) |
| 239 | #define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */ |
| 240 | #define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos) |
| 241 | #define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */ |
| 242 | #define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos) |
| 243 | #define PAC_INTFLAGA_SERCOM0_Pos 12 /**< \brief (PAC_INTFLAGA) SERCOM0 */ |
| 244 | #define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos) |
| 245 | #define PAC_INTFLAGA_SERCOM1_Pos 13 /**< \brief (PAC_INTFLAGA) SERCOM1 */ |
| 246 | #define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos) |
| 247 | #define PAC_INTFLAGA_TC0_Pos 14 /**< \brief (PAC_INTFLAGA) TC0 */ |
| 248 | #define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos) |
| 249 | #define PAC_INTFLAGA_TC1_Pos 15 /**< \brief (PAC_INTFLAGA) TC1 */ |
| 250 | #define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos) |
| 251 | #define PAC_INTFLAGA_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */ |
| 252 | |
| 253 | /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ |
| 254 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 255 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 256 | struct { |
| 257 | __I uint32_t USB_:1; /*!< bit: 0 USB */ |
| 258 | __I uint32_t DSU_:1; /*!< bit: 1 DSU */ |
| 259 | __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ |
| 260 | __I uint32_t CMCC_:1; /*!< bit: 3 CMCC */ |
| 261 | __I uint32_t PORT_:1; /*!< bit: 4 PORT */ |
| 262 | __I uint32_t DMAC_:1; /*!< bit: 5 DMAC */ |
| 263 | __I uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX */ |
| 264 | __I uint32_t EVSYS_:1; /*!< bit: 7 EVSYS */ |
| 265 | __I uint32_t :1; /*!< bit: 8 Reserved */ |
| 266 | __I uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 */ |
| 267 | __I uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 */ |
| 268 | __I uint32_t TCC0_:1; /*!< bit: 11 TCC0 */ |
| 269 | __I uint32_t TCC1_:1; /*!< bit: 12 TCC1 */ |
| 270 | __I uint32_t TC2_:1; /*!< bit: 13 TC2 */ |
| 271 | __I uint32_t TC3_:1; /*!< bit: 14 TC3 */ |
| 272 | __I uint32_t :1; /*!< bit: 15 Reserved */ |
| 273 | __I uint32_t RAMECC_:1; /*!< bit: 16 RAMECC */ |
| 274 | __I uint32_t :15; /*!< bit: 17..31 Reserved */ |
| 275 | } bit; /*!< Structure used for bit access */ |
| 276 | uint32_t reg; /*!< Type used for register access */ |
| 277 | } PAC_INTFLAGB_Type; |
| 278 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 279 | |
| 280 | #define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ |
| 281 | #define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ |
| 282 | |
| 283 | #define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */ |
| 284 | #define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos) |
| 285 | #define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ |
| 286 | #define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos) |
| 287 | #define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ |
| 288 | #define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) |
| 289 | #define PAC_INTFLAGB_CMCC_Pos 3 /**< \brief (PAC_INTFLAGB) CMCC */ |
| 290 | #define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos) |
| 291 | #define PAC_INTFLAGB_PORT_Pos 4 /**< \brief (PAC_INTFLAGB) PORT */ |
| 292 | #define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos) |
| 293 | #define PAC_INTFLAGB_DMAC_Pos 5 /**< \brief (PAC_INTFLAGB) DMAC */ |
| 294 | #define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos) |
| 295 | #define PAC_INTFLAGB_HMATRIX_Pos 6 /**< \brief (PAC_INTFLAGB) HMATRIX */ |
| 296 | #define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos) |
| 297 | #define PAC_INTFLAGB_EVSYS_Pos 7 /**< \brief (PAC_INTFLAGB) EVSYS */ |
| 298 | #define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos) |
| 299 | #define PAC_INTFLAGB_SERCOM2_Pos 9 /**< \brief (PAC_INTFLAGB) SERCOM2 */ |
| 300 | #define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos) |
| 301 | #define PAC_INTFLAGB_SERCOM3_Pos 10 /**< \brief (PAC_INTFLAGB) SERCOM3 */ |
| 302 | #define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos) |
| 303 | #define PAC_INTFLAGB_TCC0_Pos 11 /**< \brief (PAC_INTFLAGB) TCC0 */ |
| 304 | #define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos) |
| 305 | #define PAC_INTFLAGB_TCC1_Pos 12 /**< \brief (PAC_INTFLAGB) TCC1 */ |
| 306 | #define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos) |
| 307 | #define PAC_INTFLAGB_TC2_Pos 13 /**< \brief (PAC_INTFLAGB) TC2 */ |
| 308 | #define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos) |
| 309 | #define PAC_INTFLAGB_TC3_Pos 14 /**< \brief (PAC_INTFLAGB) TC3 */ |
| 310 | #define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos) |
| 311 | #define PAC_INTFLAGB_RAMECC_Pos 16 /**< \brief (PAC_INTFLAGB) RAMECC */ |
| 312 | #define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos) |
| 313 | #define PAC_INTFLAGB_MASK _U_(0x00017EFF) /**< \brief (PAC_INTFLAGB) MASK Register */ |
| 314 | |
| 315 | /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ |
| 316 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 317 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 318 | struct { |
| 319 | __I uint32_t CAN0_:1; /*!< bit: 0 CAN0 */ |
| 320 | __I uint32_t CAN1_:1; /*!< bit: 1 CAN1 */ |
| 321 | __I uint32_t GMAC_:1; /*!< bit: 2 GMAC */ |
| 322 | __I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */ |
| 323 | __I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */ |
| 324 | __I uint32_t TC4_:1; /*!< bit: 5 TC4 */ |
| 325 | __I uint32_t TC5_:1; /*!< bit: 6 TC5 */ |
| 326 | __I uint32_t PDEC_:1; /*!< bit: 7 PDEC */ |
| 327 | __I uint32_t AC_:1; /*!< bit: 8 AC */ |
| 328 | __I uint32_t AES_:1; /*!< bit: 9 AES */ |
| 329 | __I uint32_t TRNG_:1; /*!< bit: 10 TRNG */ |
| 330 | __I uint32_t ICM_:1; /*!< bit: 11 ICM */ |
| 331 | __I uint32_t PUKCC_:1; /*!< bit: 12 PUKCC */ |
| 332 | __I uint32_t QSPI_:1; /*!< bit: 13 QSPI */ |
| 333 | __I uint32_t CCL_:1; /*!< bit: 14 CCL */ |
| 334 | __I uint32_t :17; /*!< bit: 15..31 Reserved */ |
| 335 | } bit; /*!< Structure used for bit access */ |
| 336 | uint32_t reg; /*!< Type used for register access */ |
| 337 | } PAC_INTFLAGC_Type; |
| 338 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 339 | |
| 340 | #define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ |
| 341 | #define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ |
| 342 | |
| 343 | #define PAC_INTFLAGC_CAN0_Pos 0 /**< \brief (PAC_INTFLAGC) CAN0 */ |
| 344 | #define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos) |
| 345 | #define PAC_INTFLAGC_CAN1_Pos 1 /**< \brief (PAC_INTFLAGC) CAN1 */ |
| 346 | #define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos) |
| 347 | #define PAC_INTFLAGC_GMAC_Pos 2 /**< \brief (PAC_INTFLAGC) GMAC */ |
| 348 | #define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos) |
| 349 | #define PAC_INTFLAGC_TCC2_Pos 3 /**< \brief (PAC_INTFLAGC) TCC2 */ |
| 350 | #define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos) |
| 351 | #define PAC_INTFLAGC_TCC3_Pos 4 /**< \brief (PAC_INTFLAGC) TCC3 */ |
| 352 | #define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos) |
| 353 | #define PAC_INTFLAGC_TC4_Pos 5 /**< \brief (PAC_INTFLAGC) TC4 */ |
| 354 | #define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos) |
| 355 | #define PAC_INTFLAGC_TC5_Pos 6 /**< \brief (PAC_INTFLAGC) TC5 */ |
| 356 | #define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos) |
| 357 | #define PAC_INTFLAGC_PDEC_Pos 7 /**< \brief (PAC_INTFLAGC) PDEC */ |
| 358 | #define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos) |
| 359 | #define PAC_INTFLAGC_AC_Pos 8 /**< \brief (PAC_INTFLAGC) AC */ |
| 360 | #define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos) |
| 361 | #define PAC_INTFLAGC_AES_Pos 9 /**< \brief (PAC_INTFLAGC) AES */ |
| 362 | #define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos) |
| 363 | #define PAC_INTFLAGC_TRNG_Pos 10 /**< \brief (PAC_INTFLAGC) TRNG */ |
| 364 | #define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos) |
| 365 | #define PAC_INTFLAGC_ICM_Pos 11 /**< \brief (PAC_INTFLAGC) ICM */ |
| 366 | #define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos) |
| 367 | #define PAC_INTFLAGC_PUKCC_Pos 12 /**< \brief (PAC_INTFLAGC) PUKCC */ |
| 368 | #define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos) |
| 369 | #define PAC_INTFLAGC_QSPI_Pos 13 /**< \brief (PAC_INTFLAGC) QSPI */ |
| 370 | #define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos) |
| 371 | #define PAC_INTFLAGC_CCL_Pos 14 /**< \brief (PAC_INTFLAGC) CCL */ |
| 372 | #define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos) |
| 373 | #define PAC_INTFLAGC_MASK _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */ |
| 374 | |
| 375 | /* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ |
| 376 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 377 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 378 | struct { |
| 379 | __I uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 */ |
| 380 | __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */ |
| 381 | __I uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 */ |
| 382 | __I uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 */ |
| 383 | __I uint32_t TCC4_:1; /*!< bit: 4 TCC4 */ |
| 384 | __I uint32_t TC6_:1; /*!< bit: 5 TC6 */ |
| 385 | __I uint32_t TC7_:1; /*!< bit: 6 TC7 */ |
| 386 | __I uint32_t ADC0_:1; /*!< bit: 7 ADC0 */ |
| 387 | __I uint32_t ADC1_:1; /*!< bit: 8 ADC1 */ |
| 388 | __I uint32_t DAC_:1; /*!< bit: 9 DAC */ |
| 389 | __I uint32_t I2S_:1; /*!< bit: 10 I2S */ |
| 390 | __I uint32_t PCC_:1; /*!< bit: 11 PCC */ |
| 391 | __I uint32_t :20; /*!< bit: 12..31 Reserved */ |
| 392 | } bit; /*!< Structure used for bit access */ |
| 393 | uint32_t reg; /*!< Type used for register access */ |
| 394 | } PAC_INTFLAGD_Type; |
| 395 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 396 | |
| 397 | #define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */ |
| 398 | #define PAC_INTFLAGD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */ |
| 399 | |
| 400 | #define PAC_INTFLAGD_SERCOM4_Pos 0 /**< \brief (PAC_INTFLAGD) SERCOM4 */ |
| 401 | #define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos) |
| 402 | #define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */ |
| 403 | #define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos) |
| 404 | #define PAC_INTFLAGD_SERCOM6_Pos 2 /**< \brief (PAC_INTFLAGD) SERCOM6 */ |
| 405 | #define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos) |
| 406 | #define PAC_INTFLAGD_SERCOM7_Pos 3 /**< \brief (PAC_INTFLAGD) SERCOM7 */ |
| 407 | #define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos) |
| 408 | #define PAC_INTFLAGD_TCC4_Pos 4 /**< \brief (PAC_INTFLAGD) TCC4 */ |
| 409 | #define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos) |
| 410 | #define PAC_INTFLAGD_TC6_Pos 5 /**< \brief (PAC_INTFLAGD) TC6 */ |
| 411 | #define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos) |
| 412 | #define PAC_INTFLAGD_TC7_Pos 6 /**< \brief (PAC_INTFLAGD) TC7 */ |
| 413 | #define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos) |
| 414 | #define PAC_INTFLAGD_ADC0_Pos 7 /**< \brief (PAC_INTFLAGD) ADC0 */ |
| 415 | #define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos) |
| 416 | #define PAC_INTFLAGD_ADC1_Pos 8 /**< \brief (PAC_INTFLAGD) ADC1 */ |
| 417 | #define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos) |
| 418 | #define PAC_INTFLAGD_DAC_Pos 9 /**< \brief (PAC_INTFLAGD) DAC */ |
| 419 | #define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos) |
| 420 | #define PAC_INTFLAGD_I2S_Pos 10 /**< \brief (PAC_INTFLAGD) I2S */ |
| 421 | #define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos) |
| 422 | #define PAC_INTFLAGD_PCC_Pos 11 /**< \brief (PAC_INTFLAGD) PCC */ |
| 423 | #define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos) |
| 424 | #define PAC_INTFLAGD_MASK _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */ |
| 425 | |
| 426 | /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ |
| 427 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 428 | typedef union { |
| 429 | struct { |
| 430 | uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ |
| 431 | uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */ |
| 432 | uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */ |
| 433 | uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */ |
| 434 | uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */ |
| 435 | uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */ |
| 436 | uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */ |
| 437 | uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */ |
| 438 | uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */ |
| 439 | uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */ |
| 440 | uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */ |
| 441 | uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */ |
| 442 | uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Protect Enable */ |
| 443 | uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Protect Enable */ |
| 444 | uint32_t TC0_:1; /*!< bit: 14 TC0 APB Protect Enable */ |
| 445 | uint32_t TC1_:1; /*!< bit: 15 TC1 APB Protect Enable */ |
| 446 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 447 | } bit; /*!< Structure used for bit access */ |
| 448 | uint32_t reg; /*!< Type used for register access */ |
| 449 | } PAC_STATUSA_Type; |
| 450 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 451 | |
| 452 | #define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ |
| 453 | #define PAC_STATUSA_RESETVALUE _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ |
| 454 | |
| 455 | #define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */ |
| 456 | #define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos) |
| 457 | #define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ |
| 458 | #define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos) |
| 459 | #define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ |
| 460 | #define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos) |
| 461 | #define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ |
| 462 | #define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos) |
| 463 | #define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ |
| 464 | #define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos) |
| 465 | #define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ |
| 466 | #define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) |
| 467 | #define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ |
| 468 | #define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos) |
| 469 | #define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ |
| 470 | #define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos) |
| 471 | #define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ |
| 472 | #define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos) |
| 473 | #define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ |
| 474 | #define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos) |
| 475 | #define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ |
| 476 | #define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos) |
| 477 | #define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */ |
| 478 | #define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos) |
| 479 | #define PAC_STATUSA_SERCOM0_Pos 12 /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */ |
| 480 | #define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos) |
| 481 | #define PAC_STATUSA_SERCOM1_Pos 13 /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */ |
| 482 | #define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos) |
| 483 | #define PAC_STATUSA_TC0_Pos 14 /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */ |
| 484 | #define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos) |
| 485 | #define PAC_STATUSA_TC1_Pos 15 /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */ |
| 486 | #define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos) |
| 487 | #define PAC_STATUSA_MASK _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */ |
| 488 | |
| 489 | /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ |
| 490 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 491 | typedef union { |
| 492 | struct { |
| 493 | uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */ |
| 494 | uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ |
| 495 | uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ |
| 496 | uint32_t CMCC_:1; /*!< bit: 3 CMCC APB Protect Enable */ |
| 497 | uint32_t PORT_:1; /*!< bit: 4 PORT APB Protect Enable */ |
| 498 | uint32_t DMAC_:1; /*!< bit: 5 DMAC APB Protect Enable */ |
| 499 | uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Protect Enable */ |
| 500 | uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Protect Enable */ |
| 501 | uint32_t :1; /*!< bit: 8 Reserved */ |
| 502 | uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Protect Enable */ |
| 503 | uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Protect Enable */ |
| 504 | uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Protect Enable */ |
| 505 | uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Protect Enable */ |
| 506 | uint32_t TC2_:1; /*!< bit: 13 TC2 APB Protect Enable */ |
| 507 | uint32_t TC3_:1; /*!< bit: 14 TC3 APB Protect Enable */ |
| 508 | uint32_t :1; /*!< bit: 15 Reserved */ |
| 509 | uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Protect Enable */ |
| 510 | uint32_t :15; /*!< bit: 17..31 Reserved */ |
| 511 | } bit; /*!< Structure used for bit access */ |
| 512 | uint32_t reg; /*!< Type used for register access */ |
| 513 | } PAC_STATUSB_Type; |
| 514 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 515 | |
| 516 | #define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ |
| 517 | #define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ |
| 518 | |
| 519 | #define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */ |
| 520 | #define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos) |
| 521 | #define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ |
| 522 | #define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos) |
| 523 | #define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ |
| 524 | #define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos) |
| 525 | #define PAC_STATUSB_CMCC_Pos 3 /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */ |
| 526 | #define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos) |
| 527 | #define PAC_STATUSB_PORT_Pos 4 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */ |
| 528 | #define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos) |
| 529 | #define PAC_STATUSB_DMAC_Pos 5 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */ |
| 530 | #define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos) |
| 531 | #define PAC_STATUSB_HMATRIX_Pos 6 /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */ |
| 532 | #define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos) |
| 533 | #define PAC_STATUSB_EVSYS_Pos 7 /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */ |
| 534 | #define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos) |
| 535 | #define PAC_STATUSB_SERCOM2_Pos 9 /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */ |
| 536 | #define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos) |
| 537 | #define PAC_STATUSB_SERCOM3_Pos 10 /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */ |
| 538 | #define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos) |
| 539 | #define PAC_STATUSB_TCC0_Pos 11 /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */ |
| 540 | #define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos) |
| 541 | #define PAC_STATUSB_TCC1_Pos 12 /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */ |
| 542 | #define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos) |
| 543 | #define PAC_STATUSB_TC2_Pos 13 /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */ |
| 544 | #define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos) |
| 545 | #define PAC_STATUSB_TC3_Pos 14 /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */ |
| 546 | #define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos) |
| 547 | #define PAC_STATUSB_RAMECC_Pos 16 /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */ |
| 548 | #define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos) |
| 549 | #define PAC_STATUSB_MASK _U_(0x00017EFF) /**< \brief (PAC_STATUSB) MASK Register */ |
| 550 | |
| 551 | /* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ |
| 552 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 553 | typedef union { |
| 554 | struct { |
| 555 | uint32_t CAN0_:1; /*!< bit: 0 CAN0 APB Protect Enable */ |
| 556 | uint32_t CAN1_:1; /*!< bit: 1 CAN1 APB Protect Enable */ |
| 557 | uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Protect Enable */ |
| 558 | uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */ |
| 559 | uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */ |
| 560 | uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */ |
| 561 | uint32_t TC5_:1; /*!< bit: 6 TC5 APB Protect Enable */ |
| 562 | uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Protect Enable */ |
| 563 | uint32_t AC_:1; /*!< bit: 8 AC APB Protect Enable */ |
| 564 | uint32_t AES_:1; /*!< bit: 9 AES APB Protect Enable */ |
| 565 | uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Protect Enable */ |
| 566 | uint32_t ICM_:1; /*!< bit: 11 ICM APB Protect Enable */ |
| 567 | uint32_t PUKCC_:1; /*!< bit: 12 PUKCC APB Protect Enable */ |
| 568 | uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Protect Enable */ |
| 569 | uint32_t CCL_:1; /*!< bit: 14 CCL APB Protect Enable */ |
| 570 | uint32_t :17; /*!< bit: 15..31 Reserved */ |
| 571 | } bit; /*!< Structure used for bit access */ |
| 572 | uint32_t reg; /*!< Type used for register access */ |
| 573 | } PAC_STATUSC_Type; |
| 574 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 575 | |
| 576 | #define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ |
| 577 | #define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ |
| 578 | |
| 579 | #define PAC_STATUSC_CAN0_Pos 0 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */ |
| 580 | #define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos) |
| 581 | #define PAC_STATUSC_CAN1_Pos 1 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */ |
| 582 | #define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos) |
| 583 | #define PAC_STATUSC_GMAC_Pos 2 /**< \brief (PAC_STATUSC) GMAC APB Protect Enable */ |
| 584 | #define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos) |
| 585 | #define PAC_STATUSC_TCC2_Pos 3 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ |
| 586 | #define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos) |
| 587 | #define PAC_STATUSC_TCC3_Pos 4 /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */ |
| 588 | #define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos) |
| 589 | #define PAC_STATUSC_TC4_Pos 5 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */ |
| 590 | #define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos) |
| 591 | #define PAC_STATUSC_TC5_Pos 6 /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */ |
| 592 | #define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos) |
| 593 | #define PAC_STATUSC_PDEC_Pos 7 /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */ |
| 594 | #define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos) |
| 595 | #define PAC_STATUSC_AC_Pos 8 /**< \brief (PAC_STATUSC) AC APB Protect Enable */ |
| 596 | #define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos) |
| 597 | #define PAC_STATUSC_AES_Pos 9 /**< \brief (PAC_STATUSC) AES APB Protect Enable */ |
| 598 | #define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos) |
| 599 | #define PAC_STATUSC_TRNG_Pos 10 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */ |
| 600 | #define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos) |
| 601 | #define PAC_STATUSC_ICM_Pos 11 /**< \brief (PAC_STATUSC) ICM APB Protect Enable */ |
| 602 | #define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos) |
| 603 | #define PAC_STATUSC_PUKCC_Pos 12 /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */ |
| 604 | #define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos) |
| 605 | #define PAC_STATUSC_QSPI_Pos 13 /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */ |
| 606 | #define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos) |
| 607 | #define PAC_STATUSC_CCL_Pos 14 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */ |
| 608 | #define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos) |
| 609 | #define PAC_STATUSC_MASK _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */ |
| 610 | |
| 611 | /* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */ |
| 612 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 613 | typedef union { |
| 614 | struct { |
| 615 | uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Protect Enable */ |
| 616 | uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */ |
| 617 | uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Protect Enable */ |
| 618 | uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Protect Enable */ |
| 619 | uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Protect Enable */ |
| 620 | uint32_t TC6_:1; /*!< bit: 5 TC6 APB Protect Enable */ |
| 621 | uint32_t TC7_:1; /*!< bit: 6 TC7 APB Protect Enable */ |
| 622 | uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Protect Enable */ |
| 623 | uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Protect Enable */ |
| 624 | uint32_t DAC_:1; /*!< bit: 9 DAC APB Protect Enable */ |
| 625 | uint32_t I2S_:1; /*!< bit: 10 I2S APB Protect Enable */ |
| 626 | uint32_t PCC_:1; /*!< bit: 11 PCC APB Protect Enable */ |
| 627 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
| 628 | } bit; /*!< Structure used for bit access */ |
| 629 | uint32_t reg; /*!< Type used for register access */ |
| 630 | } PAC_STATUSD_Type; |
| 631 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 632 | |
| 633 | #define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */ |
| 634 | #define PAC_STATUSD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */ |
| 635 | |
| 636 | #define PAC_STATUSD_SERCOM4_Pos 0 /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */ |
| 637 | #define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos) |
| 638 | #define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */ |
| 639 | #define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos) |
| 640 | #define PAC_STATUSD_SERCOM6_Pos 2 /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */ |
| 641 | #define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos) |
| 642 | #define PAC_STATUSD_SERCOM7_Pos 3 /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */ |
| 643 | #define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos) |
| 644 | #define PAC_STATUSD_TCC4_Pos 4 /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */ |
| 645 | #define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos) |
| 646 | #define PAC_STATUSD_TC6_Pos 5 /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */ |
| 647 | #define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos) |
| 648 | #define PAC_STATUSD_TC7_Pos 6 /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */ |
| 649 | #define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos) |
| 650 | #define PAC_STATUSD_ADC0_Pos 7 /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */ |
| 651 | #define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos) |
| 652 | #define PAC_STATUSD_ADC1_Pos 8 /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */ |
| 653 | #define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos) |
| 654 | #define PAC_STATUSD_DAC_Pos 9 /**< \brief (PAC_STATUSD) DAC APB Protect Enable */ |
| 655 | #define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos) |
| 656 | #define PAC_STATUSD_I2S_Pos 10 /**< \brief (PAC_STATUSD) I2S APB Protect Enable */ |
| 657 | #define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos) |
| 658 | #define PAC_STATUSD_PCC_Pos 11 /**< \brief (PAC_STATUSD) PCC APB Protect Enable */ |
| 659 | #define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos) |
| 660 | #define PAC_STATUSD_MASK _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */ |
| 661 | |
| 662 | /** \brief PAC hardware registers */ |
| 663 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 664 | typedef struct { |
| 665 | __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ |
| 666 | __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ |
| 667 | RoReg8 Reserved1[0x3]; |
| 668 | __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ |
| 669 | __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ |
| 670 | RoReg8 Reserved2[0x6]; |
| 671 | __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ |
| 672 | __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ |
| 673 | __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ |
| 674 | __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ |
| 675 | __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ |
| 676 | RoReg8 Reserved3[0x10]; |
| 677 | __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ |
| 678 | __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ |
| 679 | __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ |
| 680 | __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ |
| 681 | } Pac; |
| 682 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 683 | |
| 684 | /*@}*/ |
| 685 | |
| 686 | #endif /* _SAME54_PAC_COMPONENT_ */ |