Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for OSC32KCTRL |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_OSC32KCTRL_COMPONENT_ |
| 31 | #define _SAME54_OSC32KCTRL_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR OSC32KCTRL */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_OSC32KCTRL 32kHz Oscillators Control */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define OSC32KCTRL_U2400 |
| 40 | #define REV_OSC32KCTRL 0x100 |
| 41 | |
| 42 | /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ |
| 47 | uint32_t :1; /*!< bit: 1 Reserved */ |
| 48 | uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */ |
| 49 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
| 50 | } bit; /*!< Structure used for bit access */ |
| 51 | uint32_t reg; /*!< Type used for register access */ |
| 52 | } OSC32KCTRL_INTENCLR_Type; |
| 53 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 54 | |
| 55 | #define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ |
| 56 | #define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ |
| 57 | |
| 58 | #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ |
| 59 | #define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) |
| 60 | #define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */ |
| 61 | #define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos) |
| 62 | #define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ |
| 63 | |
| 64 | /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ |
| 65 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 66 | typedef union { |
| 67 | struct { |
| 68 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ |
| 69 | uint32_t :1; /*!< bit: 1 Reserved */ |
| 70 | uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */ |
| 71 | uint32_t :29; /*!< bit: 3..31 Reserved */ |
| 72 | } bit; /*!< Structure used for bit access */ |
| 73 | uint32_t reg; /*!< Type used for register access */ |
| 74 | } OSC32KCTRL_INTENSET_Type; |
| 75 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 76 | |
| 77 | #define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ |
| 78 | #define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ |
| 79 | |
| 80 | #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ |
| 81 | #define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) |
| 82 | #define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */ |
| 83 | #define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos) |
| 84 | #define OSC32KCTRL_INTENSET_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ |
| 85 | |
| 86 | /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ |
| 87 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 88 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 89 | struct { |
| 90 | __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ |
| 91 | __I uint32_t :1; /*!< bit: 1 Reserved */ |
| 92 | __I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */ |
| 93 | __I uint32_t :29; /*!< bit: 3..31 Reserved */ |
| 94 | } bit; /*!< Structure used for bit access */ |
| 95 | uint32_t reg; /*!< Type used for register access */ |
| 96 | } OSC32KCTRL_INTFLAG_Type; |
| 97 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 98 | |
| 99 | #define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ |
| 100 | #define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| 101 | |
| 102 | #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ |
| 103 | #define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) |
| 104 | #define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */ |
| 105 | #define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos) |
| 106 | #define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ |
| 107 | |
| 108 | /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ |
| 109 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 110 | typedef union { |
| 111 | struct { |
| 112 | uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ |
| 113 | uint32_t :1; /*!< bit: 1 Reserved */ |
| 114 | uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */ |
| 115 | uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */ |
| 116 | uint32_t :28; /*!< bit: 4..31 Reserved */ |
| 117 | } bit; /*!< Structure used for bit access */ |
| 118 | uint32_t reg; /*!< Type used for register access */ |
| 119 | } OSC32KCTRL_STATUS_Type; |
| 120 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 121 | |
| 122 | #define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ |
| 123 | #define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ |
| 124 | |
| 125 | #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ |
| 126 | #define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) |
| 127 | #define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */ |
| 128 | #define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos) |
| 129 | #define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */ |
| 130 | #define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos) |
| 131 | #define OSC32KCTRL_STATUS_MASK _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */ |
| 132 | |
| 133 | /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */ |
| 134 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 135 | typedef union { |
| 136 | struct { |
| 137 | uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ |
| 138 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| 139 | } bit; /*!< Structure used for bit access */ |
| 140 | uint8_t reg; /*!< Type used for register access */ |
| 141 | } OSC32KCTRL_RTCCTRL_Type; |
| 142 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 143 | |
| 144 | #define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */ |
| 145 | #define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */ |
| 146 | |
| 147 | #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ |
| 148 | #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| 149 | #define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)) |
| 150 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ |
| 151 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ |
| 152 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ |
| 153 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ |
| 154 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| 155 | #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| 156 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| 157 | #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) |
| 158 | #define OSC32KCTRL_RTCCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ |
| 159 | |
| 160 | /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ |
| 161 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 162 | typedef union { |
| 163 | struct { |
| 164 | uint16_t :1; /*!< bit: 0 Reserved */ |
| 165 | uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ |
| 166 | uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ |
| 167 | uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ |
| 168 | uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ |
| 169 | uint16_t :1; /*!< bit: 5 Reserved */ |
| 170 | uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ |
| 171 | uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ |
| 172 | uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ |
| 173 | uint16_t :1; /*!< bit: 11 Reserved */ |
| 174 | uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ |
| 175 | uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */ |
| 176 | uint16_t :1; /*!< bit: 15 Reserved */ |
| 177 | } bit; /*!< Structure used for bit access */ |
| 178 | uint16_t reg; /*!< Type used for register access */ |
| 179 | } OSC32KCTRL_XOSC32K_Type; |
| 180 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 181 | |
| 182 | #define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| 183 | #define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| 184 | |
| 185 | #define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ |
| 186 | #define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) |
| 187 | #define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ |
| 188 | #define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) |
| 189 | #define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ |
| 190 | #define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) |
| 191 | #define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ |
| 192 | #define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) |
| 193 | #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ |
| 194 | #define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) |
| 195 | #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ |
| 196 | #define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) |
| 197 | #define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ |
| 198 | #define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) |
| 199 | #define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos)) |
| 200 | #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ |
| 201 | #define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) |
| 202 | #define OSC32KCTRL_XOSC32K_CGM_Pos 13 /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */ |
| 203 | #define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos) |
| 204 | #define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos)) |
| 205 | #define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */ |
| 206 | #define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */ |
| 207 | #define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos) |
| 208 | #define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos) |
| 209 | #define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ |
| 210 | |
| 211 | /* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */ |
| 212 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 213 | typedef union { |
| 214 | struct { |
| 215 | uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */ |
| 216 | uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */ |
| 217 | uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */ |
| 218 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| 219 | } bit; /*!< Structure used for bit access */ |
| 220 | uint8_t reg; /*!< Type used for register access */ |
| 221 | } OSC32KCTRL_CFDCTRL_Type; |
| 222 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 223 | |
| 224 | #define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */ |
| 225 | #define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */ |
| 226 | |
| 227 | #define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */ |
| 228 | #define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos) |
| 229 | #define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */ |
| 230 | #define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos) |
| 231 | #define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */ |
| 232 | #define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos) |
| 233 | #define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */ |
| 234 | |
| 235 | /* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */ |
| 236 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 237 | typedef union { |
| 238 | struct { |
| 239 | uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */ |
| 240 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 241 | } bit; /*!< Structure used for bit access */ |
| 242 | uint8_t reg; /*!< Type used for register access */ |
| 243 | } OSC32KCTRL_EVCTRL_Type; |
| 244 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 245 | |
| 246 | #define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */ |
| 247 | #define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */ |
| 248 | |
| 249 | #define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */ |
| 250 | #define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos) |
| 251 | #define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */ |
| 252 | |
| 253 | /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ |
| 254 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 255 | typedef union { |
| 256 | struct { |
| 257 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 258 | uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */ |
| 259 | uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */ |
| 260 | uint32_t :5; /*!< bit: 3.. 7 Reserved */ |
| 261 | uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */ |
| 262 | uint32_t :1; /*!< bit: 14 Reserved */ |
| 263 | uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ |
| 264 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 265 | } bit; /*!< Structure used for bit access */ |
| 266 | uint32_t reg; /*!< Type used for register access */ |
| 267 | } OSC32KCTRL_OSCULP32K_Type; |
| 268 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 269 | |
| 270 | #define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| 271 | #define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| 272 | |
| 273 | #define OSC32KCTRL_OSCULP32K_EN32K_Pos 1 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */ |
| 274 | #define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos) |
| 275 | #define OSC32KCTRL_OSCULP32K_EN1K_Pos 2 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */ |
| 276 | #define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos) |
| 277 | #define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ |
| 278 | #define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos) |
| 279 | #define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos)) |
| 280 | #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ |
| 281 | #define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) |
| 282 | #define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ |
| 283 | |
| 284 | /** \brief OSC32KCTRL hardware registers */ |
| 285 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 286 | typedef struct { |
| 287 | __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ |
| 288 | __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ |
| 289 | __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ |
| 290 | __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ |
| 291 | __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */ |
| 292 | RoReg8 Reserved1[0x3]; |
| 293 | __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
| 294 | __IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */ |
| 295 | __IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */ |
| 296 | RoReg8 Reserved2[0x4]; |
| 297 | __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
| 298 | } Osc32kctrl; |
| 299 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 300 | |
| 301 | /*@}*/ |
| 302 | |
| 303 | #endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ |